Commit graph

5636 commits

Author SHA1 Message Date
Tom Rini
e3288e1d15 Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2013-05-02 16:21:20 -04:00
Anatolij Gustschin
b91363cd34 mpc512x: remove dead code
The prt_mpc512x_clks() function isn't referenced
anywhere and its prototype is wrong. Remove it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-05-02 20:43:38 +02:00
Andreas Bießmann
d2eae43ba8 lib: consolidate hang()
Delete all occurrences of hang() and provide a generic function.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01 16:41:08 -04:00
Andreas Bießmann
63495ad77a nios2: fix style in board.c.
Make nios2's board.c checkpatch clean.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-01 16:24:02 -04:00
Andreas Bießmann
50ffb1174c microblaze: fix style in board.c
Make microblaze's board.c checkpatch clean.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Reviewed-by: Michal Simek <monstr@monstr.eu>
2013-05-01 16:24:02 -04:00
Simon Glass
39042d821e sandbox: Allow -c argument to provide a command list
This allows passing of entire scripts to sandbox with the -c argument,
which is useful for testing. Commands can be delimited with a newline
or semicolon.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-01 11:17:21 -04:00
Simon Glass
f828bf25fe sandbox: Add CONFIG_OF_HOSTFILE to read FDT from host file
With sandbox it is tricky to add an FDT to the image at build time (or
later) since we build an ELF file, not a plain binary, and the address
space of the whole U-Boot is not accessible in the emulated memory map
of sandbox.

Sandbox can read files directly from the host, though, so add an option
to read an FDT from a host file on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-01 11:17:21 -04:00
Simon Glass
a733b06b69 sandbox: Switch over to generic board
Add generic board support for sandbox. and remove the old board init code.

Select CONFIG_SYS_GENERIC_BOARD for sandbox now that this is supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-01 11:17:21 -04:00
Simon Glass
781adb5710 sandbox: Provide a way to map from host RAM to U-Boot RAM
In many cases, pointers to memory are passed around, and these pointers
refer to U-Boot memory, not host memory. This in itself is not a
problem.

However, in a few places, we cast that pointer back to a ulong (being
a U-Boot memory address). It is possible to convert many of these cases
to avoid this. However there are data structures (e.g. struct
bootm_headers) which use pointers. We could with a lot of effort adjust
the structs and all code that uses them to use ulong instead of pointers.

This seems like an unacceptable cost, since our objective with sandbox
is to minimise the impact on U-Boot code while maximising the features
available to sandbox.

Therefore, create a map_to_sysmem() function which converts from a
pointer to a U-Boot address. This can be used sparingly when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-01 11:17:21 -04:00
Tom Rini
92daa4d2cf Merge branch 'microblaze' of git://www.denx.de/git/u-boot-microblaze 2013-05-01 10:37:35 -04:00
Michal Simek
8934f78465 i2c: zynq: Add support for Xilinx Zynq
Support Xilinx Zynq i2c controller.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:28 +02:00
Michal Simek
293eb33fcb mmc: Add support for Xilinx Zynq sdhci controller
Add support for SD, MMC and eMMC card on Xilinx Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:27 +02:00
Michal Simek
7193653e8d zynq: Move macros to hardware.h
Add all fixed addresses to hardware.h and change petalinux
configuration to support this.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:21 +02:00
Michal Simek
80243528ef net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:19 +02:00
Michal Simek
4b21284b8c zynq: Move scutimer baseaddr to hardware.h
Move baseaddr to hardware.h to be shared between
configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:12 +02:00
Michal Simek
e072b5f5dc arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addresses
XPSS prefix was used in past and it is obsolete for quite
some time. Let's use correct SoC name which is Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:11 +02:00
David Andrey
d54cc00787 arm: zynq: U-Boot udelay < 1000 FIX
Rework the __udelay function of U-Boot Zynq Arch to handle
delay < 1000 usec

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:10 +02:00
Michal Simek
0f21f98dd4 watchdog: Add support for Xilinx Microblaze watchdog
Watchdog can be used on Microblaze, PPC and Zynq hw designs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:22:43 +02:00
Marek Vasut
6cb83829a0 tools: arm: imx: Implement BOOT_OFFSET command for imximage
Implement BOOT_OFFSET command for imximage. This command is parallel
to current BOOT_FROM command, but allows more flexibility in configuring
arbitrary image header offset. Also add an imximage.cfg with default
offset values into arm/arch/imx-common/ so the board-specific imximage.cfg
can include this file to avoid magic constants.

The syntax of BOOT_OFFSET command is "BOOT_OFFSET <u32 offset>".

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2013-04-28 11:18:03 +02:00
Benoît Thébaudeau
7e2173cf82 imx: iomux-v3: Include PKE and PUE to pad control pull definitions
PUE requires PKE to mean something, as do pull values with PUE, so do not
compell users to explicitly use PKE and PUE everywhere. This is also what is
done on Linux and what has already been done for i.MX51.

By the way, remove some unused pad control definitions.

There is no change of behavior.

Note that SPI_PAD_CTRL was defined by several boards with a pull value, but
without PKE or PUE, which means that no pull was actually enabled in the pad.
This might be a bug in those boards, but this patch does not change the
behavior, so it just removes the meaningless pull value from those definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:07 +02:00
Benoît Thébaudeau
246952083a imx: iomux-v3: Restore Linux's NEW_PAD_CTRL() macro
This macro will be useful for future changes.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:07 +02:00
Benoît Thébaudeau
79a34d3ccc imx: iomux-v3: cosmetic: Reorganize definitions
Keep pad control definitions together, and organize definitions in a more
legible way.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:06 +02:00
Benoît Thébaudeau
d73b97604b imx: iomux-v3: Fix common pad control definitions
Commit dc88403 "iomux-v3: Place pad control definitions into common file" broke
mx51_efikamx because it made i.MX6's pad control definitions conflict with
i.MX51's.

i.MX51's pad control definitions are actually common to some other i.MX
(25/35/53), so move them to the common iomux-v3.h (just like what is done in
Linux's), and select the correct definitions depending on whether CONFIG_MX6 is
defined or not.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:06 +02:00
Benoît Thébaudeau
112fd2ec6c Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:43 +02:00
Benoît Thébaudeau
83306927de mpc: iim: Switch to common fsl_iim
Make all mpc512x code point to the new common fsl_iim driver, and remove the
former mpc512x-specific iim driver.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Benoît Thébaudeau
0f67e09e9e Add fsl_iim driver
Add a fsl_iim driver common to i.MX and MPC.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:41 +02:00
Benoît Thébaudeau
6adbd30203 imx: Add useful fuse definitions
Define the UID (SoC unique ID) fuses, and the fuses available for the user.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:40 +02:00
Benoît Thébaudeau
8f3ff11c1f imx: Homogenize and fix fuse register definitions
IIM:
 - Homogenize prg_p naming (the reference manuals are not always self-consistent
   for that).
 - Add missing SCSx and bank registers.
 - Fix the number of banks on i.MX53.

OCOTP:
 - Rename iim to ocotp in order to avoid confusion.
 - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
   reference manual.
 - Merge the existing spinoff gp1 fuse definition on i.MX6.
 - Fix the number of banks on i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-28 11:07:40 +02:00
Fabio Estevam
cdc203682f mx23: Put back RAM voltage level to its original value
commit 5c2f444c9 (mxs: Reset the EMI block on mx23) changed the DDR voltage
level, which causes mx23evk to fail to load a kernel.

Put back the original values, so that mx23evk can boot a kernel again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
2013-04-28 11:06:27 +02:00
Fabio Estevam
1155d555d6 mx53ard: Move register masks into imx-regs.h
imx-regs.h is more appropriate location for containing register masks.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-04-25 21:48:21 +02:00
Fabio Estevam
11c08d4ec5 mx5: Define a common get_board_rev()
When booting a FSL kernel based on 2.6.35 it is necessary to pass the revision
tag to the kernel.

Place a common weak function into soc.c for such purpose.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-04-25 21:48:21 +02:00
Otavio Salvador
5ed15738d9 wandboard: Add support for Carrier Board MicroSD card
Allow use of the carrier board MicroSD card available in the
Wandboard; this allow for loading alternative system from the other
card for testing or upgrade proposes.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-25 21:34:28 +02:00
Otavio Salvador
08f32f7d25 wandboard: Add card detection for SOM MicroSD card
This add support to identify if the card is connected or not; so it
does not try to communicate with the controller if no card is
available.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-25 21:34:02 +02:00
Fabio Estevam
492938a334 nitrogen6x: Setup CCM_CCOSR register
CKO1 drives sgtl5000 codec clock on nitrogen boards and wandboard.

Doing this setup in the bootloader will allow us to remove a lot of code in
arch/arm/mach-imx/mach-imx6q.c from the mainline kernel.

Also, according to Eric Nelson: "enabling the clock <in the bootloader> will
remove squeal after an ungraceful reboot (watchdog) if hooked up to speakers."

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-25 21:15:49 +02:00
Philip Paeps
3f21501114 mx35 iomux: correct input select register index
Prior to this fix, calls to mxc_iomux_set_input() for registers
after MUX_IN_GPIO2_IN_19 would write to the wrong registers,
possibly resulting in unexpected behaviour.

Signed-off-by: Philip Paeps <philip@paeps.cx>
2013-04-25 21:10:00 +02:00
Stefan Roese
51f329a774 arm: imx: Codingstyle enhancement of include/asm/arch-mx6/crm_regs.h
Add spaces before and after "<<".

Please note that I intentionally didn't wrap the > 80 lines for
the sake of better readability.

Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-25 21:06:56 +02:00
Stefan Roese
b29ca4a158 imx: Add titanium board support (i.MX6 based)
Titanium is a i.MX6 based board from ProjectionDesign / Barco. This
patch adds support for this board with the newly introduced NAND
support for i.MX6.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:40 +02:00
Stefan Roese
ae695b18df mtd: mxs_nand: Add support for i.MX6
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:36 +02:00
Stefan Roese
99193e30b4 dma: Add i.MX6 support to drivers/dma/apbh_dma.c
This will be used by the i.MX6 NAND support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:13 +02:00
Stefan Roese
8870e45996 imx: Move some i.MX common functions into the imx-common directory
This patch moves the following functions into the imx-common
directory:

- mxs_wait_mask_set()
- mxs_wait_mask_clr()
- mxs_reset_block()

These are currently used by i.MX28. But the upcoming GPMI NAND port
for i.MX6 will also use these functions. So lets move them to a
common location to re-use them.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:23:42 +02:00
Stefan Roese
0499218dbc imx: Move some header files from arch-mxs to imx-common
The following headers are moved to a i.MX common location:

- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h

This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:22:22 +02:00
Fabio Estevam
25b4aa146a mx6: Add solo-lite variant support
mx6 solo-lite is another member of the mx6 series.

For more information about mx6 solo-lite, please visit:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:57:44 +02:00
Fabio Estevam
dc88403e6c iomux-v3: Place pad control definitions into common file
Instead of having the same PAD control definition in each MX6 variant pin file,
place it into a common location.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:56:20 +02:00
Stefan Roese
98f99e9f16 ppc4xx: Add SPL support
This patch adds SPL booting support (NOR flash) for the
PPC4xx platforms.

This SPL booting (Falcon mode) will be used by the upcoming
lcd4_lwmon5 board port (lwmon5 variant).

Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-22 09:53:53 +02:00
Stefano Babic
cd53034613 Merge branch 'next' 2013-04-21 11:32:19 +02:00
Tom Rini
17dcbfb087 Merge branch 'master' of git://git.denx.de/u-boot-arm into HEAD
Quick manual fixup to merge the USB boot related defines and TPM related
defines.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-04-18 16:16:01 -04:00
Simon Glass
dc47e2bc7d exynos: Correct use of 64-bit division
The current code is causing errors like this on my toolchains:

/usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/
ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/
armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o)

Use do_div() to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-17 10:00:40 +09:00
Tom Rini
314dd4fecc Merge branch 'master' of git://git.denx.de/u-boot-x86 2013-04-16 16:12:33 -04:00
Stefan Roese
59efa051cd arm: imx: Change iomux functions to void type
They never return anything also than 0, so lets change the function
to void instead.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2013-04-16 18:58:47 +02:00
Philip Paeps
04f79536c3 mx35 iomux: correct offsets of IOMUX registers
This makes mxc_iomux_set_input() work correctly.  Previously, the
incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input()
to write to the wrong register, possibly resulting in unexpected
behaviour.

Signed-off-by: Philip Paeps <philip@paeps.cx>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-16 18:58:47 +02:00
Simon Glass
8b42dfc3b6 x86: Fix DRAM bank size init with generic board
The intention of the memory init code is that it should work the same with
CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init()
is called prior to relocation with generic board (matching other archs)
and after relocation without generic board.

Adjust the init sequence so that dram_init() is not called in the generic
board case, which seems like the easiest fix for now. Also ensure that
relocation addresses are still calculated.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-15 16:26:09 -07:00
Tom Warren
49493cb714 Tegra: Split tegra_get_chip_type() into soc & sku funcs
As suggested by Stephen Warren, use tegra_get_chip() to return
the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for
Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true
function, i.e. tegra_get_chip_sku(), which returns an ID like
TEGRA_SOC_T25, TEGRA_SOC_T33, etc.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
d94c2dbd0a Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
b40f734af9 Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
d0edce4fa3 Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
3ebbbfe4c7 Tegra: Restore cp15 VBAR _start vector write for ARMv7
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53),
and caused the old monilithic Tegra builds to hang due to an undefined
instruction trap. Previously, the code needed to run on both the
AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register.
I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but
now that we use SPL, and boot the AVP w/o any ARMv7 code, I can
revert my change, and make Aneesh's change apply to Tegra.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-04-15 11:01:37 -07:00
Stephen Warren
eb222d1d7d ARM: tegra: support T33 SKU of Tegra30
Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically
to any other Tegra30.

An alternative would be to simply remove the SKU checking from
tegra_get_chip_type(); most use of the value most likely simply wants
to know the current chip, not the specific SKU. Or, the function could
be split into separate tegra_get_chip() and tegra_get_sku() for the
cases where differentiation really is required.

I wonder whether tegra_get_chip_type() should printf() whenever any
unkown chip/SKU is found, although perhaps the function is called so
early that the printf() wouldn't actually make it to the UART anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-04-15 11:01:37 -07:00
Andre Przywara
c4a4e2e20c ARMv7: start.S: stay in HYP mode if u-boot is entered in it
The KVM and Xen hypervisors for the Cortex-A15 virtualization
implementation need to be entered in HYP mode. Should the primary
board firmware already enter HYP mode (Calxeda firmware does that),
we should not deliberately drop back to SVC mode.
Since U-boot does not use the MMU, running in HYP mode is just fine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-04-15 18:30:59 +02:00
Albert ARIBAUD
6ebc346111 ARM: fix CONFIG_SPL_MAX_SIZE semantics
Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds
as this file is never used for SPL builds.

Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds
to separately test image (text,data,rodata...) size,
BSS size, and full footprint each against its own max,
and make Tegra boards check full footprint.

Also, output section mmutable is not used in SPL builds.
Remove it.

Finally, update README regarding the (now homogeneous)
semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new
CONFIG_SPL_MAX_FOOTPRINT macro.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-14 16:07:14 +02:00
Albert ARIBAUD
8dc16cf9dd Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-14 10:38:37 +02:00
Albert ARIBAUD
f84a7b8f54 ARM: Fix __bss_start and __bss_end in linker scripts
Commit 3ebd1cbc introduced compiler-generated __bss_start
and __bss_end__ and commit c23561e7 rewrote all __bss_end__
as __bss_end. Their merge caused silent and harmless but
potentially bug-inducing clashes between compiler- and linker-
generated __bss_end symbols.

Make __bss_end and __bss_start compiler-only, and create
__bss_base and __bss_limit for linker-only use.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-13 22:37:20 +02:00
Fabio Estevam
0f1411bc8d spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).

Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.

Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-13 17:46:42 +02:00
Tetsuyuki Kobayashi
4411b2aea7 BUGFIX: arm: data abort in get_bad_stack_swi
When swi instruction is executed, it is expected to get message
"software interrupt" in console and dump registers and reboot, as
do_software_interrupt() in arch/arm/lib/interrupts.c.
But, actually it causes data abort accessing wrong address in get_bad_stack_swi
macro in arch/arm/cpu/v7/start.S.
This patch fixes this problem.

The same mistake in arch/arm/cpu/{arm1136,arm1176,pxa}/start.S.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2013-04-13 11:12:46 +02:00
Albert ARIBAUD
0c669fd17a Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-04-13 09:39:29 +02:00
Albert ARIBAUD
1812201997 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/video/exynos_fb.c
2013-04-12 22:07:57 +02:00
man.huber@arcor.de
9d0fd10ca1 omap3: Display MHz instead of mHz on the console
The processor is hopefully running with M(ega)Hz and not with m(illi)Hz.

Signed-off-by: Manfred Huber <man.huber@arcor.de>
2013-04-12 15:29:23 -04:00
Tom Rini
86fdb1619a am335x: Really correct DDR timings on new BeagleBone part
The previous timings were done on the internal-only A1 board which has
different DDR part than all later revs.  The timings need a slight
adjustment to be correct in all cases with later revs.

Signed-off-by: Tom Rini <trini@ti.com>
2013-04-12 12:38:16 -04:00
Albert ARIBAUD
c97b6df1ae Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-04-12 08:51:41 +02:00
Benoît Thébaudeau
1a9a91dcfa arm: Make all linker scripts compatible with per-symbol sections
Let all ARM linker scripts handle properly -ffunction-sections
and -fdata-sections. This will be useful for future changes in order to create
symbol-specific sections in common .S files.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
9ce8e2386c arm1176: Remove unused MMU setup from start.S
Following the removal of the smdk6400 board, the MMU setup code in
arm1176/start.S becomes unused, so remove it. It will still be possible to
restore it later from the Git history if necessary, in which case it should be
moved out of the relocate_code() function.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
66f30bf983 arm: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
e53232250b arm: Remove support for unused s3c64xx
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
52587f1ef8 arm: Remove support for smdk6400
The migration of boards from Makefile to boards.cfg was due for v2012.03, but
smdk6400 did not follow, and it does not build, so move it to scrapyard. It will
still be possible to restore it from the Git history before fixing it.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
7d5a5c79ca imx: Add u-boot-with-nand-spl.imx make target
This image combines the SPL with the i.MX header, the FCB and U-Boot.

For i.MX25/35/51, the FCB is ignored by the boot ROM, so this image is just
useful because it can be programmed on a NAND Flash page boundary.

For i.MX53, the FCB is required by the boot ROM.

This does not support i.MX6 so far because its FCB is more complicated.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
ba5976092f imx: Add u-boot-with-spl.imx make target
This image combines the SPL with the i.MX header and U-Boot. This is a
convenient way of having a single image to program on some boot devices.

The i.MX header has to be added to the SPL before appending U-Boot, so that the
boot ROM loads only the SPL.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
5c6db120fc arm: Remove unused relocate_code() parameters
Commit e05e5de7fa made the 2 1st parameters of
ARM's relocate_code() useless since it moved the code handling them to crt0.S.
So, drop these parameters.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
ac415a5720 arm926ejs: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
da962b7175 nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
8b7cd098dd imx: Fix automatic make targets for imx images
Automatically build the 'u-boot.imx' (i.e. imx header + u-boot.bin) and 'SPL'
(i.e. imx header + u-boot-spl.bin) make targets for all imx processors
supporting this header, so for arm926ejs, arm1136 and armv7. Some combinations
were missing.

At the same time, fix the build of SPL targets not supporting the imx header on
arm1136. For arm1136, the 'SPL' make target was forced to build in all cases if
CONFIG_SPL_BUILD was defined, even for non-imx platforms or imx setups without
an imx header.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:06 +02:00
Benoît Thébaudeau
9c5feab76f arm: crt0.S: Remove bogus .globl
The purpose of .globl is to export symbols for ld, not to declare external
symbols.

By the way, use the ENTRY() and ENDPROC() macros to define functions rather than
using .global directly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:06 +02:00
Benoît Thébaudeau
7086e91b0e arm: relocate_code(): Use __image_copy_end for end of relocation
Use __image_copy_end instead of __bss_start for the end of the image to
relocate. This is the same as commit 033ca72, but applied to all ARM start.S.

This is a more appropriate symbol naming for an image copy & relocate feature,
and this also saves a useless copy of data put between __image_copy_end and
__bss_start in linker scripts (e.g. relocation information, or MMU
initialization tables used only before jumping to the relocated image).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
4b3db1cd31 arm: relocate_code(): Remove useless relocation offset computation
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
1dd1276fd8 arm1136: Remove redundant relocate_code() return
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
959eaa74b8 arm: relocate_code() is no longer noreturn
Commit e05e5de7fa made ARM's relocate_code()
return to its caller, but it did not update its declaration accordingly.

Fixing this function declaration fixes dropped C code following calls to
relocate_code().

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
508611bcb7 arm: start.S: Fix _TEXT_BASE for SPL
_TEXT_BASE must be set to CONFIG_SPL_TEXT_BASE for generic SPL, and to
CONFIG_SYS_TEXT_BASE for non-SPL builds.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
e78b140801 imx: mx5: lowlevel_init: Simplify code
Don't use several instructions to build constant values.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-12 07:55:04 +02:00
Tom Rini
980464a4fc Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-04-11 14:31:50 -04:00
Jon Hunter
eef6da0326 omap5912-osk: Fix get_timer() and CONFIG_SYS_HZ
The function get_timer() should return time in ms and CONFIG_SYS_HZ
should be set to 1000 by default. Fix both of these items.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-10 16:03:02 -04:00
Lubomir Popov
a1c8fb9132 OMAP4: Fix bug in omap4460_volts struct
The omap4460_volts struct was incorrectly referencing tps62361
instead of twl6030 as PMIC for the core and mm voltages (the
tps is used for mpu supply only). This shall lead to bad OPP
settings while booting kernel. Fixing it.

Fix some comments as well.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-04-10 13:05:32 -04:00
Mats Kärrman
fac150e83f powerpc/lib: fix unsafe register handling in wait_ticks
If watchdog is enabled, the arch/powerpc/lib/ticks.S::wait_ticks() function
calls the function specified by the WATCHDOG_RESET macro.
The wait_ticks function depends on the registers r0, r6 and r7 being
preserved however that is not guaranteed, e.g. if the reset function is a
C function this will probably overwrite r0 and cause an endless loop.

The following patch changes to using r14+r15 instead of r6+r7 (to resemble
what would have been generated by a C compiler) and saves all necessary
registers on the stack.

The patch has been tested on a custom MPC5125 based machine using the 512x
powerpc architecture.

Signed-off-by: Mats Karrman <mats.karrman@tritech.se>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Tested-by: Stefan Roese <sr@denx.de>
2013-04-10 10:31:02 -04:00
Tom Rini
b996a3e9a8 am335x: Update timings for the beaglebone again
After further testing we can run DDR at 400MHz so update the timings
again.

Tested-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tom Rini <trini@ti.com>
2013-04-10 10:04:40 -04:00
ramneek mehresh
dda48e8eff powerpc/usb: Fix usb device-tree fix-up
Fix USB device-tree fixup to properly handle device-tree fixup and
print appropriate message when wrong/junk "dr_mode" or "phy_type"
are mentioned in hwconfig string

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-04-10 15:22:25 +02:00
Tom Rini
74f40ea1bc am335x/ti814x: Correct MMC_BOOT_DEVICES_START/END
Given that on TI814x we have MMC1/2 swapped, we also need to swap them
in MMC_BOOT_DEVICES_START/END

Reported-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-04-09 11:40:40 -04:00
Tom Rini
c3d2c24f6c OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMC
In the case of booting from certain peripherals, such as UART, we must
not see what the device descriptor says for RAW or FAT mode because in
addition to being nonsensical, it leads to a hang.  This is why we have
a test currently for the boot mode being within range.  The problem
however is that on some platforms we get MMC2_2 as the boot mode and not
the defined value for MMC2, and in others we get the value for MMC2_2.
This is required to fix eMMC booting on omap5_uevm.

Tested on am335x_evm (UART, NAND, SD), omap3_beagle (NAND, SD on
classic, SD only on xM rev C5) and omap5_uevm (SD, eMMC).

Signed-off-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:34 -04:00
Lokesh Vutla
d3d82e9fc6 arm: omap4: Fix SDRAM AUTO DETECTION
Commit "8602114 omap: emif: configure emif only when required"
breaks SDRAM_AUTO_DETECTION.
The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection)
done in do_sdram_init(). The above commit moves dmm_init() above
do_sdram_init() because of which dmm_init() uses uninitialized
emif_sizes[].
So instead of using global emif_sizes[], get sdram details locally
and calculate emif sizes.

Reported-by: Michael Cashwell <mboards@prograde.net>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-04-08 11:29:34 -04:00
Lubomir Popov
a8f408a8c4 OMAP: Fix copy-paste bug that did not enable UART4 clock
V2 fixes line wrap issue of the patch itself.

UART3 was enabled twice instead of UART4.

One more cosmetic change in a comment on EMIF clock.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Reviewed-by: R Sricharan <r.sricharan@ti.com>
2013-04-08 11:29:05 -04:00
Hunter, Jon
d1da76e9f8 omap2420-h4: Fix get_timer() and CONFIG_SYS_HZ
The function get_timer() should return time in ms and CONFIG_SYS_HZ
should be set to 1000 by default. Fix both of these items.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-08 11:29:05 -04:00
Hunter, Jon
47f58a7357 omap2420-h4: Fix booting from NOR flash
The omap2420-h4 board is using a RAM based address as the linker
location for code. This is causing several problems when attempting
to run the latest u-boot code base on this board from flash. Update
the default linker location for code to be in NOR flash. Please note
that OMAP maps the NOR flash to address 0x08000000 by default and so
use this as the default address for the NOR flash.

Also remove legacy code that attempts to calculate where in flash the
sdata structure, that holds the memory interface configuration data,
is located. By changing the default linker location for code to flash
this is no longer necessary.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
da634ae356 omap_gpmc: change nandecc command
With uppcoming BCH support on OMAP devices we need to decide between differnt
algorithms when switching the ECC engine.  Currently we support 1-bit hammign
and 8-bit BCH on HW backend.

In order to switch between differnet ECC algorithms we need to change the
interface of omap_nand_switch_ecc() also.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
c0ed9179b8 omap3/omap_gpmc.h: add ooblayout for BCH8 as in kernel
This patch adds BCH8 ooblayout for NAND as provided by
0e618ef0a6a33cf7ef96c2c824402088dd8ef48c in linux kernel. This Layout is
currently only provided for 64 byte OOB.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
5bf299bc4f asm/omap_gpmc.h: consolidate common defines
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.

Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
86b128d6f7 omap3/cpu.h: add BCH support
This patch adds the BCH result registers to register mapping for OMAP3 gpmc.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Tom Rini
5aa014d613 am335x: Enable MMC1 clock
We must not assume ROM has enabled the clock for MMC1.

Reported-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-04-08 11:29:05 -04:00
Albert ARIBAUD
fed029f3c3 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-04-04 15:44:57 +02:00
Minkyu Kang
4fdebefa45 exynos: change indentation of defines in cpu.h
Fix the indentation of some defines by tab.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-04 20:17:50 +09:00
Albert ARIBAUD
be08abc242 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-04 11:49:32 +02:00
Stephen Warren
5eaa215607 ARM: bcm2835: fix get_timer() to return ms
Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer
driver to conform to this.

Have the timer implementation export a custom API get_timer_us() for use
by the BCM2835 MMC API, which needs us resolution for a HW workaround.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-04-04 08:14:54 +02:00
Fabio Estevam
38e7007725 mx6: Fix get_board_rev() for the mx6 solo case
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev()
returns 0x62xxx, which is not a value understood by the VPU
(Video Processing Unit) library in the kernel and causes the video playback to
fail.

The expected values for get_board_rev are:
0x63xxx: For mx6quad/dual
0x61xxx: For mx6dual-lite/solo

So adjust get_board_rev() accordingly and make it as weak function, so that we
do not need to define it in every mx6 board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-03 11:36:34 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Akshay Saraswat
07cd5c7495 Exynos: pwm: Remove dead code of function exynos5_get_pwm_clk
As we shall now be using clock_get_periph_rate function.
We find no reason for keeping code in function exynos5_get_pwm_clk.
Hence, removing it.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Padmavathi Venna
e2338704c0 Exynos: pwm: Use generic api to get pwm clk freq
Use generic api to get the pwm clock frequency

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Padmavathi Venna
12a46a384d Exynos: clock: Add generic api to get the clk freq
Add generic api to get the frequency of the required peripherial. This
API gets the source clock frequency and returns the required frequency
by dividing with first and second dividers based on the requirement.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Padmavathi Venna
394d64e45b Exynos: Add peripherial id for pwm
Add peripherial id for pwm inorder to support
generic api to get the clk frequency

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Gabe Black
92809eeed2 Exynos: Tidy up the pwm_config function in the exynos pwm driver
Some small fixes in the exynos pwm driver:

1. NS_IN_HZ is non-sensical since these are not compatible units. This
constant actually describes the number of nanoseconds in a second. Renamed it
to NS_IN_SEC. Also dropped the unnecessary parenthesis.
2. The variable "period" is not used to hold a period, it's used to hold a
frequency. Renamed it to "frequency".
3. tcmp is an unsigned value, so (tcmp < 0) will never be true and the if
which checks that condition will never execute. Also, there should be no
problem if the pwm never switches, so there's no reason to subtract one from
tcmp and therefore no reason to compare it against zero. Removed both ifs. If
they weren't removed, tcmp should be a signed value.
4. Add a check for a 0 period.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Gabe Black
34b5ee1f6a Exynos: Avoid a divide by zero by specifying a non-zero period for pwm 4
The pwm_config function in the exynos pwm driver divides by its period
period parameter. A function was calling pwm_config with a 0ns period and a
0ns duty cycle. That doesn't actually make any sense physically, and results
in a divide by zero in the driver. This change changes the parameters to be a
100000ns period and duty cycle.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Gabe Black
c059f274ad Exynos: pwm: Fix two bugs in the exynos pwm configuration code
First, the "div" value was being used incorrectly to compute the frequency of
the PWM timer. The value passed in is a constant which reflects the value
that would be found in a configuration register, 0 to 4. That should
correspond to a scaling factor of 1, 2, 4, 8, or 16, 1 << div, but div + 1 was
being used instead.

Second, the reset value of the timers were being calculated to give an overall
frequency, thrown out, and set to a maximum value. This was done so that PWM 4
could be used as the system clock by counting down from a high value, but it
was applied indiscriminantly. It should at most be applied only to PWM 4.

This change also takes the opportunity to tidy up the pwm_init function.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Che-Liang Chiou
f24869d3a8 Exynos: Add timer_get_us function
timer_get_us returns the time in microseconds since a certain reference
point of history.  However, it does not guarantee to return an accurate
time after a long period; instead, it wraps around (that is, the
reference point is reset to some other point of history) after some
periods. The frequency of wrapping around is about an hour (or 2^32
microseconds).

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Simon Glass
3d00c0cb96 Exynos: Change get_timer() to work correctly
At present get_timer() does not return sane values. It should count up
smoothly in milliscond intervals.

We can change the PWM to count down at 1MHz, providing a resolution
of 1us and a range of about an hour between required get_timer() calls.

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01 14:02:08 +09:00
Anatolij Gustschin
d0f34f10f1 Merge branch 'for-v2013.04'
Conflicts:
	drivers/video/Makefile

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-29 13:54:10 +01:00
Akshay Saraswat
acbb1eb772 Exynos: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using ACE hardware.

Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-03-29 20:10:42 +09:00
Albert ARIBAUD
009d75ccc1 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/spi/tegra20_sflash.c
	include/fdtdec.h
	lib/fdtdec.c
2013-03-28 18:50:01 +01:00
Vincent Stehlé
d53e340edf armv7: do not relocate _start twice
The _start symbol is already relocated, so do not add the relocation the second
time in c_runtime_cpu_setup.

This fixes e.g. the abort exception handling path, which ended in double fault
due to bad address in VBAR.

Signed-off-by: Vincent Stehlé <v-stehle@ti.com>
Reported-by: Lubomir Popov <lpopov@mm-sol.com>
2013-03-28 10:15:06 +01:00
R Sricharan
de63ac278c ARM: mmu: Set domain permissions to client access
The 'XN' execute never bit is set in the pagetables. This will
 prevent speculative prefetches to non executable regions. But the
 domain permissions are set as master in the DACR register.
 So the pagetable attribute for 'XN' is not effective. Change the
 permissions to client.

 This fixes lot of speculative prefetch aborts seen on OMAP5
 secure devices.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Tested-by: Vincent Stehle <v-stehle@ti.com>
Cc: Vincent Stehle <v-stehle@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-28 09:10:58 +01:00
R Sricharan
96fdbec2f9 ARM: mmu: Introduce weak dram_bank_setup function
Introduce a weak version of dram_bank_setup function
to allow a platform specific function.

This is used in the subsequent patch to setup dram region
without 'XN' attribute in order to enable the region
under client permissions.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Vincent Stehle <v-stehle@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-28 09:06:49 +01:00
Vincent Stehlé
dfa4138715 ARM: cache: declare set_section_dcache
We declare the set_section_dcache function globally in the cache header, for
later use by e.g. machine specific code.

Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com>
Cc: Tom Rini <trini <at> ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-28 09:06:43 +01:00
Ajay Kumar
71e6ba4655 EXYNOS5: Add device node for DP
Add DT node and bindings documentaion for DP.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:23:18 +09:00
Ajay Kumar
9a1313e1c1 EXYNOS5: Add device node for FIMD
Add DT node and bindings documentation for FIMD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:19:09 +09:00
Ajay Kumar
c18222bee8 video: exynos_dp: Remove callbacks from the driver
Replaced the functionality of callbacks by using a standard set of functions.
Instead of implementing and hooking up a callback, put the same code in one of
the standard set of functions by overriding it.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:17:15 +09:00
Rajeshwari Shinde
7ee68fe85f EXYNOS5: Add L2 Cache Support.
This patch set adds L2 Cache Support to EXYNOS.

Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 16:53:37 +09:00
Albert ARIBAUD
ebd749da69 Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-03-26 10:40:13 +01:00
Albert ARIBAUD
412665b461 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-03-26 09:51:09 +01:00
Tom Warren
2a04a31791 Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table
SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup
before the MMC driver is added.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Tom Warren
e9cd20654c Tegra114: fdt: Add SDMMC (sdhci) nodes for T114 boards (Dalmore for now)
Took these values directly from the kernel dts files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Allen Martin
77c42e80b9 tegra114: add SPI driver
Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00
Allen Martin
9a38fb4d94 tegra114: fdt: add SPI blocks
Add nodes for t114 SPI controller hardware

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
6a3742fe7a tegra114: fdt: add apbdma block
Add node for apbdma controller hardware.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
78f47b7353 spi: add common fdt SPI driver interface
Add a common interface to fdt based SPI drivers.  Each driver is
represented by a table entry in fdt_spi_drivers[].  If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Allen Martin
7a49ba6e5b tegra: spi: pull register structs out of headers
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
ff1da6fb5f tegra: spi: rename tegra SPI drivers
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Allen Martin
9000652da0 tegra: remove support for UART SPI switch
This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins.  These boards were never manufactured, so
remove this support to clean up SPI driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:05 -07:00
Albert ARIBAUD
b6379e15a7 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-03-24 17:52:22 +01:00
Tom Rini
bd380cf4cf arm: Correct CONFIG_STANDALONE_LOAD_ADDR for AM33XX/OMAP* platforms
All of these platforms have memory starting at 0x80000000, so this is
the correct CONFIG_STANDALONE_LOAD_ADDR for all of them.

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:12 -04:00
Tom Rini
c7ba18ad4b am335x_evm: Add better timings for the new BeagleBoard DDR3 part
Tested-by: Rao Bodapati <rao@circuitco.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:12 -04:00
Matt Porter
ea7b96b6aa ti814x_evm: add ti814x evm board support
Add TI814X EVM board directory, config file, and MAINTAINERS
entry. Enable build.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Adapt to recent omap_hsmmc requirements, Matt re-tested]
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:12 -04:00
Matt Porter
26fa57842b am33xx: support ti814x mmc reference clock
TI814x has a 192MHz hsmmc reference clock. Select that clock rate
when building for TI814x.

Signed-off-by: Matt Porter <mporter@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
4fab8d7bbd am33xx: add dmm support to emif4 library
Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
8b029f22a6 am33xx: add ti814x specific register definitions
Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
b2e682f7a0 am33xx: refactor am33xx mux support and add ti814x support
AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-24 12:49:11 -04:00
Matt Porter
b43c17cba6 am33xx: refactor am33xx clocks and add ti814x support
Split clock.c for am335x and ti814x and add ti814x specific
clock support.

Signed-off-by: Matt Porter <mporter@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
3ba65f97cb am33xx: refactor emif4/ddr to support multiple EMIF instances
The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Matt Porter
81df2bab46 am33xx: convert defines from am33xx-specific to generic names
Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Tom Rini
98f92001b3 am33xx: Add required includes to some omap/am33xx code
- In arch/arm/cpu/armv7/omap-common/timer.c,
  drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
  that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
  <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
  as that is the only include which defines things the config uses.

Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Enric Balletbo i Serra
244044e151 ARM: AM33XX: Fix typo that causes an AM duplication in CPU name.
Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see
something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-03-24 12:49:10 -04:00
Vaibhav Hiremath
59dcf970d1 am335x: Enable DDR PHY dynamic power down bit for DDR3 boards
Enable DDR PHY dynamic power down bit, which enables
powering down the IO receiver when not performing read.

This also helps in reducing overall power consumption in
low power states (suspend/standby).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:05 -04:00
Stephen Warren
c5d4752c05 ARM: implement erratum 716044 workaround
Add common code to enable the workaround for ARM erratum 716044. This
will be enabled for Tegra.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-22 16:45:22 +01:00
Steve Kipisz
1e7e374b35 am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.

Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
           Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
2013-03-22 11:12:53 -04:00
Mark Jackson
296de3bbec Initialise correct GPMC WAITx irq for AM33xx
Currently WAIT0 irq is reset and then WAIT1 irq is enabled.
Fix it such that WAIT0 irq is enabled instead.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-22 10:57:00 -04:00
Mark Jackson
fc33705e66 Allow AM335x MPU core clock speed to be specified in the board config file
Allow AM335x MPU core clock speed to be specified in the board config file.
To use, add the following to the board's config file:-

#define CONFIG_SYS_MPUCLK	<desired clock freq in MHz>

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-22 10:57:00 -04:00
Jeroen Hofstee
0698095af6 lcd, pxafb: move the pxafb to drivers/video
Since the lcd code was compiled unconditionally for pxa also add
CONFIG_PXA_LCD to the boards using this framebuffer. Since
driver/video contains video and lcd drivers, add lcd to the name
to make clear it belongs to common/lcd.c.

cc: Anatolij Gustschin <agust@denx.de>
cc: Cliff Brake <cliff.brake@gmail.com>
cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-03-21 09:38:21 +01:00
Jeroen Hofstee
59155f4c50 lcd, mpc8xx: move the mpc8xx driver to drivers/video
Since the lcd code was compiled unconditionally in arch also
add CONFIG_MPC8XX_LCD to the boards using this driver.

cc: Anatolij Gustschin <agust@denx.de>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-03-21 09:17:39 +01:00
Wolfgang Denk
46d1d5dd43 common/lcd.c: cleanup use of global variables
lcd_color_fg and lcd_color_bg had to be declared in board specific
code, but were not actually used there; in addition, we have getter /
setter functions for these, which were not used either.

Get rid of the global variables, and use the getter function where
needed (so far no setter calls are needed).

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[agust: also fixed cm_t35 board while rebasing]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-21 09:05:08 +01:00
Stephen Warren
131a1e603b ARM: rpi_b: enable SD controller, add related env/cmds
Enable the SD controller driver for the Raspberry Pi. Enable a number
of useful MMC, partition, and filesystem-related commands. Set up the
environment to provide standard locations for loading a kernel, DTB,
etc. Provide a boot command that loads and executes boot.scr.uimg from
the SD card; this is written considering future extensibilty to USB
storage.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-03-20 15:32:16 +01:00
Stephen Warren
9a4fbe4fbd mmc: add bcm2835 driver
This adds a simple driver for the BCM2835's SD controller.

Workarounds are implemented for:
* Register writes can't be too close to each-other in time, or they will
  be lost.
* Register accesses must all be 32-bit, so implement custom accessors.

This code was extracted from:
git://github.com/gonzoua/u-boot-pi.git master
which was created by Oleksandr Tymoshenko.

Portions of the code there were obviously based on the Linux kernel at:
git://github.com/raspberrypi/linux.git rpi-3.6.y
commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley.

swarren changed the following for upstream:
* Removed hack udelay()s in bcm2835_sdhci_raw_writel(); setting
  SDHCI_QUIRK_WAIT_SEND_CMD appears to solve the issues.
* Remove register logging from read*/write* functions.
* Sort out confusion with min/max_freq values passed to add_sdhci().
* Use more descriptive variable names and calculations in IO accessors.
* Simplified and commented twoticks_delay calculation.
* checkpatch fixes.

Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Andy Fleming <afleming@gmail.com>
2013-03-20 15:31:25 +01:00
Stephen Warren
88077280c4 ARM: bcm2835: add mailbox driver
The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
and the ARM CPU. The ARM CPU is often thought of as the main CPU.
However, the VideoCore actually controls the initial SoC boot, and hides
much of the hardware behind a protocol. This protocol is transported
using the SoC's mailbox hardware module.

Here, we add a very simplistic driver for the mailbox module, and define
a few structures for the property messages.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-03-20 15:29:20 +01:00
Fabio Estevam
e2d282a1b4 Add initial support for Wandboard dual lite and solo.
Wandboard is a development board that has two variants: one version based
on mx6 dual lite and another one based on mx6 solo.

For more details about Wandboard, please refer to: http://www.wandboard.org/

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-03-20 11:47:37 +01:00
Eric Nelson
99e2dc59cb i.MX6: Add hdmidet command to detect attached HDMI monitor
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-03-20 11:43:19 +01:00
Knut Wohlrab
982a3c410e imx-common: timer: fix 32-bit overflow
The i.MX6 common timer uses the 32-bit variable tbl (time base lower)
to record the overflow of the 32-bit counter. I.e. if the counter
overflows, the variable tbl does overflow, too.

To capture this overflow, use the variable tbu (time base upper), too.
Return the combined value of tbl and tbu.

lastinc is unused then, remove it.

Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-03-20 11:36:11 +01:00
Fabio Estevam
b33426caf6 mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Currently the following kernel hang happens when loading a 2.6.35 kernel from
Freeescale on a mx28evk board:

RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Bus freq driver module loaded
IMX usb wakeup probe
usb h1 wakeup device is registered
mxs_cpu_init: cpufreq init finished
...

Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01
package, the hang does not occur.

Comparing the DDR2 initialization from the bootlets code against the U-boot
one, we can notice some mismatches, and after applying the same initialization
into U-boot the 2.6.35 kernel can boot normally.

Also tested with 'mtest' command, which runs succesfully.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Marek Vasut <marex@denx.de>
2013-03-20 11:05:32 +01:00
Simon Glass
192868b061 x86: Move PCI init before SPI init
It is possible that our PCI bus will provide the SPI controller, so change
the init order to make this work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Simon Glass
68794b9f73 sparc: Fix build warnings in serial.c
These macros are already defined in io.h so should not be declared in
serial.c.

serial.c:38:0: warning: "READ_BYTE" redefined
/home/sjg/c/src/third_party/u-boot/files/include/asm/io.h:36:0: note: this is the location of the previous definition
serial.c:39:0: warning: "READ_HWORD" redefined
/home/sjg/c/src/third_party/u-boot/files/include/asm/io.h:37:0: note: this is the location of the previous definition
serial.c:40:0: warning: "READ_WORD" redefined
/home/sjg/c/src/third_party/u-boot/files/include/asm/io.h:38:0: note: this is the location of the previous definition
serial.c:41:0: warning: "READ_DWORD" redefined
/home/sjg/c/src/third_party/u-boot/files/include/asm/io.h:39:0: note: this is the location of the previous definition

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:02 -04:00
Simon Glass
eb33809f70 sparc: Fix out-of-tree building
It isn't clear why the sparc cpu Makefile has its own compile line, but
it does not work correctly with an out-of-tree build. Removing it fixes
this problem. Perhaps it does not introduce others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:01 -04:00
Simon Glass
81e2ff0bf1 avr32: Fix cast warning in board.c
The frame buffer pointer in global_data is not a pointer, so we should
remove these casts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-15 16:14:01 -04:00
Simon Glass
9e97834867 blackfin: Remove noreturn attribute from cpu_init_f()
Now that board_init_f() is not marked as noreturn, we need to do the same
to blackfin's cpu_init_f() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:01 -04:00
Simon Glass
4da2551efa blackfin: Fix up board_type global data
This should be in arch_global_data but was dropped in the change-over.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:01 -04:00
Simon Glass
949747b17f x86: Enable generic board
This will be used exclusively on x86, so enable it for the whole
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:01 -04:00
Simon Glass
e424c15c1f x86: Enable generic board support
This enables generic board support so that x86 boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
86cfb6bdec x86: Use sections header to obtain link symbols
These are defined in asm-generic/sections.h, so remove them from
architecture-specific files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
660c60c4e7 ppc: Enable generic board support
This enables generic board support so that ppc boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
959daa21d4 arm: Enable generic board support
This enables generic board support so that ARM boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
6f6430d72b Introduce generic post-relocation board_r.c
This file handles common post-relocation init for boards which use
the generic framework.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:59 -04:00
Simon Glass
1938f4a5b6 Introduce generic pre-relocation board_f.c
This file handles common pre-relocation init for boards which use
the generic framework.

It starts up the console, DRAM, performs relocation and then jumps
to post-relocation init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-03-15 16:13:59 -04:00
Simon Glass
a6741bce50 Declare watchdog functions in watchdog.h
These functions are only available for powerpc and are not declared in a
header file. We want to use the rest function in two places (board_f and
board_r), so declare the functions in watchdog.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:59 -04:00
Simon Glass
716cc8cc7f Change stub example to use asm-generic/sections.h
We can use the declarations of __bss_start and _end from this header
instead of declaring them locally.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
e103b7ae90 arm: Use sections header to obtain link symbols
Include this header to get access to link symbols, which are otherwise
removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
1865286466 Introduce generic link section.h symbol files
We create a separate header file for link symbols defined by the link
scripts. It is helpful to have these all in one place and try to
make them common across architectures. Since Linux already has a similar
file, we bring this in even though many of the symbols there are not
relevant to us.

Each architecture has its own asm/sections.h where symbols specifc to
that architecture can be added. For now everything except AVR32 just
includes the generic header.

One change is needed in arch/avr32/lib/board.c to make this conversion
work.

Reviewed-by: Tom Rini <trini@ti.com> (version 5)
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
3929fb0a14 Replace __bss_end__ with __bss_end
Note this is a tree-wide change affecting multiple architectures.

At present we use __bss_start, but mostly __bss_end__. This seems
inconsistent and in a number of places __bss_end is used instead.

Change to use __bss_end for the BSS end symbol throughout U-Boot. This
makes it possible to use the asm-generic/sections.h file on all
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:54 -04:00
Albert ARIBAUD
b27673ccbd Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-03-15 20:50:43 +01:00
Albert ARIBAUD
6579d15c58 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-03-15 15:18:31 +01:00
Tom Warren
477393e787 Tegra114: Dalmore: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, no padcfg entries exist. SDIO3CFG will be added when the
MMC driver is added as per the TRM to work with the SD-card slot on
Dalmore E1611.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:49:14 -07:00
Tom Warren
5647c03431 Tegra114: fdt: Move aliases from dtsi to dts file as per other Tegras
All other Tegra boards have their alias nodes in the .dts file

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:49:07 -07:00
Tom Warren
36c48be110 Tegra114: Fix/update GP padcfg register struct
Differences in padcfg registers (some removed, some added) between
Tegra30 and Tegra114 weren't picked up when I first ported this file.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:48:05 -07:00
Tom Warren
b3b6ddff0b Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entry
This caused CAM_MCLK's pinmux reg to be locked out, since the
table parsing code couldn't find a matching entry for VI_ALT3
and wrote garbage to the register.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:08:57 -07:00
Tom Warren
38797bcb1f Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30
Removed SDMMC base addresses from tegra.h since they're no longer used.
Added additional vendor-specific SD/MMC registers and bus power defines.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:44 -07:00
Tom Warren
1baa4e72c6 Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)
Took these values directly from the kernel dts files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:44 -07:00
Tom Warren
8ca79b2ff4 Tegra30: Cardhu: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, only SDIO1CFG is changed as per the TRM to work with
the SD-card slot on Cardhu.

Thanks to StephenW for the suggestion/original idea.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
8b7776b9f9 Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 init
Use the latest tables & code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
19a970af28 Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)
Minor edit to tegra_car node, add gpio node.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Stephen Warren
16bb08d19a ARM: tegra: implement WAR for Tegra114 CPU reset vector
A Tegra114 HW bug prevents the main CPU vector from being modified under
certain circumstances. Tegra114 A01P and later with a patched boot ROM
set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing
an arbitrary jump instruction at that location, in order to redirect to
the desired reset vector location. Modify Tegra114's start_cpu() to make
use of this feature. This allows CPUs with the patched boot ROM to boot.

Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
527519ae69 Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)
Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:43 -07:00
Tom Warren
c9aa831ee2 Tegra: MMC: Add DT support to MMC driver for all T20 boards
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
126685ad44 Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files
Linux dts files were used for those boards that didn't already
have sdhci info populated. Tamonten has their own dtsi file with
common sdhci nodes (sourced from Linux).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
6c5be646b4 Tegra: fdt: Change /include/ to #include for C preprocessor
dts Makefile has the arch & board include paths added to DTS_CPPFLAGS.
This allows the use of '#include "xyz"' in the dts/dtsi file which
helps the C preprocessor find common dtsi include files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
b77c3547e8 Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Tom Warren
e32624ef82 Tegra: I2C: Add T114 clock support to tegra_i2c driver
T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.

Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-03-14 11:06:41 -07:00
Tom Warren
702b872894 Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to work
I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives).
This is needed so that the SDIO slot power can be brought up for
the MMC driver, so it has to precede those commits.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
d7a55e1a4b tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]
The ehci_hcd entry points were just calling into the Tegra USB
functions. Now that they are in the same file we can just move over the
implementation.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
7ae18f3725 tegra: usb: move implementation into right directory
This moves the Tegra USB implementation into the drivers/usb/host
directory. Note that this merges the old
/arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code
changes, just moving stuff around.

v2: While at it also move some defines and the usb.h header file to make
usb driver usable for Tegra30.
NOTE: A lot more work is required to properly init the PHYs and PLL_U on
Tegra30, this is just to make porting easier and it does no harm here.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
a63eb6bbcc tegra: usb: various small cleanups
Remove unneeded headers, function prototype and stale comment, that
doesn't match the actual codebase anymore.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
fdb4b9a71c tegra: usb: move controller init into start_port
There is no need to init a USB controller before the upper layers indicate
that they are actually going to use it.

board_usb_init now only parses the device tree and sets up the common pll.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:41 -07:00
Lucas Stach
a4bdcc38c9 tegra: usb: remove unneeded function parameter
Just a dead parameter, never actually used.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:40 -07:00
Lucas Stach
b0bbab8a14 tegra: usb: make controller init functions more self contained
There is no need to pass around all those parameters. The init functions
are able to easily extract all the needed setup info on their own.

This allows to move out the controller init into ehci_hcd_init later
on, without having to save away global state for later use  and thus
bloating the file global state.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:40 -07:00
Lucas Stach
2f3ec34027 tegra: usb: set USB_PORTS_MAX to correct value
Both Tegra20 and Tegra30 have a max of 3 USB controllers.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14 11:06:40 -07:00
Stephen Warren
0678587fb6 ARM: implement some Cortex-A9 errata workarounds
Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.

This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-03-13 22:24:11 +01:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00
Albert ARIBAUD
3ebd1cbc49 arm: make __bss_start and __bss_end__ compiler-generated
Turn __bss_start and __bss_end__ from linker-generated
to compiler-generated symbols, causing relocations for
these symbols to change type, from R_ARM_ABS32 to
R_ARM_RELATIVE.

This should have no functional impact, as it affects
references to __bss_start and __bss_end__ only before
relocation, and no such references are done.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:32 +01:00
Albert ARIBAUD
65cdd6430e Remove linker lists (LGAs) from SPL linker scripts
Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.

This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:29 +01:00
Albert ARIBAUD
2fd34f2636 arm: omap: map u_boot_lists section to .sram
Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.

Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.

This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:26 +01:00
Albert ARIBAUD
1acba3345c Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-03-12 17:27:44 +01:00
Jesse Gilles
08f0533a14 ARM: sam9x5: fix ethernet pins in MII mode
Fix pin setting in MII mode

Signed-off-by: Jesse Gilles <jgilles@multitech.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-12 13:02:20 +01:00
Bo Shen
fc14fbace4 ARM: at91sam9x5: Using CPU string directly
As the CPU name is not configurable, using CPU string directly

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-03-12 13:02:13 +01:00
Akshay Saraswat
3a0b1dae5b Exynos5: TMU: Add hardware tripping
This adds hardware tripping at 110 degrees celsius which must enable
forced system shutdown in case TMU fails to power off.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:07:31 +09:00
Akshay Saraswat
618766c098 Exynos5: FDT: Add TMU device node values
Fdt entry for Exynos TMU driver specific pre-defined values used for
calibration of current temperature and defining threshold values.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:06:06 +09:00
Akshay Saraswat
39d182d3de Exynos5: TMU: Add driver for Thermal Management Unit
Adding Exynos Thermal Management Unit driver to monitor SOC
temperature and take actions corresponding to states of TMU.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:06:03 +09:00
Simon Glass
c42ffff02a EXYNOS: Correct ordering of SPL machine_params
The mem_manuf is not in the correct order according to the string table.
This causes cros_bundle_firmware to get the BL2 settings in the wrong
order. This patch fixes the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 10:35:09 +09:00
Stefan Roese
7c9e89bd1f ppc: Remove PCIPPC2 and PCIPPC6 boards
These boards seem to be unmaintained for quite some time. So lets
remove support for them completely. This also cleans up some
common drivers/files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Guillaume Alexandre <guillaume.alexandre@gespac.ch>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-03-11 17:00:28 -04:00
Tom Rini
76b40ab41e Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 12:16:13 -04:00
Lokesh Vutla
de62688bb6 arm: dra7xx: Add silicon id support for DRA752 soc
Adding CPU detection support for the DRA752 ES1.0 soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:39:57 -04:00
Lokesh Vutla
687054a7e0 arm: dra7xx: Add board files for DRA7XX socs
Adding new board files for DRA7XX socs.
The pad registers layout is changed completely from OMAP5
So introducing the new structure here and also adding the
minimal data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishant Kamat <nskamat@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Adapt omap_mmc_init call for last 2 params]
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 11:39:30 -04:00
Lokesh Vutla
7831419d7b arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
8b12f1779e arm: dra7xx: Add control module changes
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
ea8eff1fe0 arm: dra7xx: clock: Add the dplls data
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4e4129c31 arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4d986ee27 ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
	 The 1 in wkup domain is not enabled because smart i/os
	 of wkup domain work with default compensation code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
9100edecf8 ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
47abc3df70 ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.

While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x

Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
afc2f9dcf1 ARM: OMAP5: clock: Add the prcm register changes required for ES2.0
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
eed7c0f727 ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
ef1697e99f ARM: OMAP5: Clean up iosettings code
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
c43c8339fe ARM: OMAP4+: Make control module register structure generic
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
e05a4f1f54 ARM: OMAP4+: Cleanup emif specific files
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change reduces code addition for future Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
3fcdd4a5f8 ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
ee9447bfe3 ARM: OMAP4+: Cleanup the clocks layer
Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
SRICHARAN R
01b753ff7b ARM: OMAP4+: Change the PRCM structure prototype common for all Socs
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-03-11 11:06:09 -04:00
Lokesh Vutla
9ca8bfea80 ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
Mark Jackson
6b3dcc45c4 Allow AM33xx boards to setup GPMC chipselects.
Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects.

Changes in V4:
- Fix checkpatch errors (TAB -> space mangling)

Changes in V3:
- Fix line wrapping

Changes in V2:
- Indicate this is for AM33xx (not OMAP2)

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-11 11:06:08 -04:00
Enric Balletbo i Serra
b51a5e3a0a OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.
In order to use SPL boot from OneNAND we should initialize the gpmc.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-11 11:06:08 -04:00
Anatolij Gustschin
a615dfda8c mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:23:02 +01:00
Anatolij Gustschin
fcc7fe4251 mpc512x: add ifm ac14xx board
Add new mpc5121e based ac14xx board and a new pinmux config
function for setting individual pinmux bit groups. This
function is used in ac14xx board code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:57 +01:00
Anatolij Gustschin
5643709ede mpc512x: allow configuring board specific IPS divider
Boards may define own IPS divider in the config file if
the default IPS divider doesn't fit their needs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:50 +01:00
Anatolij Gustschin
1d63b8ffdb mpc512x: optionally configure DIU, LPC and NFC deviders
If a board config file defines DIU, LPC and NFC deviders,
configure them in the SCFR1 register.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:22:45 +01:00
Anatolij Gustschin
e5f538649c mpc512x: use common code for clock setting for all mpc512x boards
Only define enabled clocks in the config file and enable
the clocks in common code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Wolfgang Denk <wd@denx.de>
2013-03-09 08:22:23 +01:00
Anatolij Gustschin
b84d6d27fc mpc512x: add common LAW and Chip Select configuration
Currently each mpc512x board has its own LAW and CS config code,
we should avoid this code duplication. Allow all boards to use
common code by only defining LAW and CS config macros like
CONFIG_SYS_CSx_START, CONFIG_SYS_CSx_SIZE and CONFIG_SYS_CSx_CFG.

Also allow common configuration of additional CS parameters by
CONFIG_SYS_CS_ALETIMING, CONFIG_SYS_CS_BURST, CONFIG_SYS_CS_DEADCYCLE
and CONFIG_SYS_CS_HOLDCYCLE options.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-03-09 08:20:54 +01:00
Stefan Roese
b4dc0bddbf mpc5200: spl_boot.c: Change init oder to first enable printf
On MPC5200, the initial RAM (and gd) is located in the internal
SRAM. So we can actually call the preloader console init code
before calling initdram(). This makes serial output (printf)
available very early, even before SDRAM init, which has been
an U-Boot priciple from day 1.

Signed-off-by: Stefan Roese <sr@denx.de>
2013-03-09 08:14:24 +01:00
Enric Balletbo i Serra
66c7f39923 SPL: ONENAND: Fix some ONENAND related defines.
Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-08 16:41:14 -05:00
Nikita Kiryanov
bcc6cc9b37 omap3: allow dynamic selection of gfx_format
Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded
in the code. This forces anyone who wants to use a different gfx_format to make
adjustments after calling omap3_dss_panel_config(). This could be avoided if the
value of gfx_format were parameterized as input for omap3_dss_panel_config().

Make gfx_format a field in struct panel_config, and update existing structs to
set this field to the value that was originally hard coded.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
bc84b18f75 omap3: add useful dss defines
Add useful omap3 dss defines for: polarity, TFT data lines, lcd
display type, gfx burst size, and gfx format

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
e3913f56a2 omap_hsmmc: add driver check for write protection
Add check for write protection in omap mmc driver.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
e874d5b001 omap_hsmmc: implement driver check for card detection
Implement driver check for card detection.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:13 -05:00
Nikita Kiryanov
fa3a69289f omap: consolidate common mmc definitions
The various mmc_host_def.h files are almost identical.
Reduce code duplication by moving the similar definitions to a common
header file.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2013-03-08 16:41:12 -05:00
Tom Rini
1c382ead7a am33xx: Update DDR3 EMIF configuration sequence
Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence.  In our current (incorrect)
sequence some edge cases may fail to initalize correctly.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-08 16:41:12 -05:00
Rajeshwari Shinde
a006076b15 EXYNOS5: Add function to enable XXTI clock source
This patch adds funtion to enable XXTI clock source
required by MAX98095 codec.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-08 22:34:18 +09:00
Stephen Warren
8f3937761b ARM: mx6: use common CPU errata config options
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2013-03-07 18:20:37 +01:00
Fabio Estevam
1b097cff51 mx6: Provide a structure for accessing HDMI registers
Provide a structure for accessing HDMI registers, so that we can use proper
read/write accessors.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 18:03:44 +01:00
Fadil Berisha
3e9dc93051 mxs: timrot: Rename local macros
Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:50:55 +01:00
Fadil Berisha
6ecd05d2f5 mxs: timrot: Add support to i.MX23
This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:58 +01:00
Otavio Salvador
eb2996024b mxs: Fix iomux.h to not break build during assembly stage
This fixes the build failure when included in mx23_olinuxino.h board
config; the addition of "asm/types.h" is due "u32" being otherwise
undefined.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:57 +01:00
Otavio Salvador
89075d3f4f mx23: Document the tRAS lockout setting in memory initialization
Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to
enable the 'Fast Auto Pre-Charge' found in the memory chip. The
setting is applied after memory initialization and it is worth
document it.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:57 +01:00
Otavio Salvador
a74dbf2734 mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT
The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2013-03-07 17:22:57 +01:00
Marek Vasut
47f1331506 mxs: Squash the header file usage in ehci-mxs
The ehci-mxs driver included the register definitions directly.
Use imx-regs.h instead since it contains proper handling of the
differences between mx23 and mx28.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:57 +01:00
Marek Vasut
3430e0bd2a mxs: mmc: spi: dma: Better wrap the MXS differences
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.

First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.

Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.

Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.

Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Marek Vasut
5c2f444c9b mxs: Reset the EMI block on mx23
The real reason for memory instability was the fact that the EMI block
was gated and not reset throughout the boards' operation. This patch
resets the EMI block properly while also reverts the memory voltage bump.
The memory stability issues were caused by the EMI not being reset properly
and thus there is no longer need to run the memory at higher voltage than
it ought to run at.

This partly reverts 8303ed128a .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-03-07 17:22:56 +01:00
Eric Nelson
690417236f i.MX6: Add DDR controller registers
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:47 +01:00
Eric Nelson
828bd14c10 i.MX6DL: define IOMUX pads NANDF_CS1-3 for use as GPIO
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:46 +01:00
Eric Nelson
714afa64f3 i.MX6: crm_regs: define IOMUXC_GPR4/6/7
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:46 +01:00
Eric Nelson
4f60c49a70 i.MX6: crm_regs: define CCM_CCGRx for use in board config files
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:46 +01:00
Eric Nelson
cfb8b9d335 i.MX6: consolidate pad names for multi-CPU boards
Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the proper header.

Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd
only support MX6Q, so they include mx6q_pins.h.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:46 +01:00
Simon Glass
62f7970a5a x86: Add error checking to x86 relocation code
This does not actually change normal behaviour, but adds a check that
should detect corruption of relocation data (e.g. by using BSS data
prior to relocation).

Also add additional debugging output when enabled.

During this investigation, two situations have been seen:
1. calculate_relocation_address():
	uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;

turns into
     111166f:	b8 83 c4 17 01       	mov    $0x117c483,%eax

whih is beyond the end of bss:

0117b484 g       .bss	00000000 __bss_end

Somehow the __bss_end here is 255 bytes ahead.

2. do_elf_reloc_fixups():

	uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;

Here the __text_start is 0 in the file:

 1111d9f:	bb a0 e0 13 01       	mov    $0x113e0a0,%ebx
1111da4:	81 ef 00 00 00 00    	sub    $0x0,%edi

As it happens, both of these are in pre-relocation code.

For these reasons we silent check and ignore bad relocations.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:48 -08:00
Simon Glass
f697d528ca x86: Support relocation of FDT on start-up
With CONFIG_OF_CONTROL we may have an FDT in the BSS region. Relocate
it up with the rest of U-Boot to keep the rest of memory free.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:47 -08:00
Simon Glass
f82d15ead1 x86: Rearrange the output input to remove BSS
At present BSS data is including in the image, which wastes binary space.
Remove it by rearranging the sections so that BSS is last.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:40 -08:00
Simon Glass
4b491b8dde x86: Add an __end symbol to signal the end of the U-Boot binary
With this symbol we can easy append something (e.g. an FDT) to the U-Boot
binary and access it from within U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:38 -08:00
Simon Glass
bc2df1afb9 x86: Permit bootstage and timer data to be used prior to relocation
It is useful to be able to access the timer before U-Boot has relocated
so that we can fully support bootstage.

Add new global_data members to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:36 -08:00
Simon Glass
8937140957 x86: Add basic cache operations
At present most x86 cache operations are undefined. Add a basic
implementation for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:34 -08:00
Simon Glass
5e98947f9b x86: Add function to get top of usable ram
The memory layout calculations are done in calculate_relocation_address(),
and coreboot has its own version of this function. But in fact all we
really need is to set the top of usable RAM, and then the base version
will work as is.

So instead of allowing the whole calculate_relocation_address() function
to be replaced, create board_get_usable_ram_top() which can be used by
a board to specify the top of the area where U-Boot relocations to.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:56:46 -08:00
Simon Glass
62584db191 sandbox: Add a way of obtaining directory listings
This implementation uses opendir()/readdir() to access the directory
information and then puts it in a linked list for the caller's use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-04 14:19:56 -05:00
Tom Rini
1c9f47ab2a Merge branch 'mem' of git://git.denx.de/u-boot-x86 2013-03-04 11:14:27 -05:00
Steven Miao
9faf4f08e7 blackfin: bf60x: add resume from hibernate
Add Bf60x resume from hibernate support

Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:08 +08:00
Bob Liu
49c2da53b7 blackfin: bf60x: add hw watchdog support
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:07 +08:00
Scott Jiang
4a207e8b9a blackfin: add bf6xx spi driver
Spi driver for bf60x is different from old one, so implement a new
driver for it.

Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:07 +08:00
Sonic Zhang
187f32fac3 blackfin: bf60x: add rsi/sdh support
Add rsi/sdh support for bf60x.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:07 +08:00
Bob Liu
c34346d85d blackfin: bf60x: add gpio support
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:07 +08:00
Bob Liu
7677d65f65 blackfin: bf60x: support big cplb page
BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them.
So that bf609-ezkit can use it's 128M memory.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:07 +08:00
Bob Liu
ee8259623e blackfin: bf60x: add dma support
Add dma support for bf60x.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:06 +08:00
Sonic Zhang
a12c51f640 blackfin: bf60x: add serial support
Add serial for bf60x.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:06 +08:00
Sonic Zhang
a2979dcdbe blackfin: bf60x: Port blackfin core architecture code to boot on bf60x.
Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:06 +08:00
Bob Liu
3ead92c571 blackfin: bf60x: new processor header files
Add header files for blackfin new processor bf60x.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
2013-03-04 13:42:06 +08:00
Simon Glass
4213fc2913 sandbox: Add un/map_sysmen() to deal with sandbox's ram_buf
Sandbox doesn't actually provide U-Boot access to the machine's physical
memory. Instead it provides a RAM buffer of configurable size, and all
memory accesses are within that buffer. Sandbox memory starts at 0 and
is CONFIG_DRAM_SIZE bytes in size. Allowing access outside this buffer
might produce unpredictable results in the event of an error, and would
expose the host machine's memory architecture to the sandbox U-Boot.

Most U-Boot functions assume that they can just access memory at given
address. For sandbox this is not true.

Add a map_sysmem() call which converts a U-Boot address to a system
address. In most cases this is a NOP, but for sandbox it returns a
pointer to that memory inside the RAM buffer.

To get a U-Boot feature to work correctly within sandbox, you should call
map_sysmem() to get a pointer to the address, and then use that address for
any U-Boot memory accesses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-28 19:09:22 -08:00
Taylor Hutt
e101550a9a sandbox: Improve sandbox serial port keyboard interface
Implements the tstc() interface for the serial driver.  Multiplexing
the console between the serial port and a keyboard uses a polling
method of checking if characters are available; this means that the
serial console must be non-blocking when attempting to read
characters.

Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-28 19:09:21 -08:00
Allen Martin
8ec21bbe5c sandbox: fix compiler warning
Add back return statement to fix compiler warning about control flow
reaching end of non void function that was introduced with:

	e05e5de arm: move C runtime setup code in crt0.S

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-02-28 19:09:21 -08:00
Stefano Babic
9cd9b34dc7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-23 10:13:40 +01:00
Albert ARIBAUD
a5627914da Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-02-21 21:30:47 +01:00
Albert ARIBAUD
03268374db Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'
This pulls the three following ZYNQ commits into ARM master:

7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f4: arm: zynq: Add SLCR support with system reset
00ed3458: arm: zynq: Add lowlevel initialization to C
2013-02-21 16:43:19 +01:00
Holger Hans Peter Freyther
c8876f1c72 mac: Fix the condition check for setting the MAC from the EEPROM
The issue got introduced in a cleanup by Manjunath Hadli in commit
826e99136e. The eth_getenv_enetaddr_by_index
method will validate the MAC addr and if none is set in the environment
0 will be returned. Set the MAC from the eeprom if no valid address
is found in environment.

Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
2013-02-20 08:52:41 -05:00
Holger Hans Peter Freyther
03414ac45e gpio: Build the da8xx_gpio code for the davinci644x device
The differences include the number of GPIOs and that one is
not required to set the pinmux on request.

Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
2013-02-20 08:52:41 -05:00
Rajeshwari Shinde
51ff1eda6f EXYNOS5: Add function to setup set ps hold
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition goes away(e.g. power button).

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-02-20 16:48:17 +09:00
Gabor Juhos
7b395232da malloc: make malloc_bin_reloc static
On architectures where manual relocation
is needed, the 'malloc_bin_reloc' function
must be called after 'mem_malloc_init'.

Make the 'malloc_bin_reloc' function static
and call it directly from 'mem_malloc_init'
instead of calling that from board_init_{r,f}
functions of the affected architectures.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andreas Bießmann <andreas.devel@gmail.com>
Cc: Jason Jin <Jason.jin@freescale.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-02-19 17:01:26 -05:00
Ilya Yanok
da07c21b77 am33xx: support for booting via usbeth
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2013-02-18 13:48:04 -05:00
Tomas Novotny
b9f56698c7 da8xx: Add the missing pinmux for da830 to the gpio driver
The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of
kernel version 3.7.5. If the driver is used for the da850, then SoC
variant must be specified by CONFIG_SOC_DA850.

Signed-off-by: Tomas Novotny <tomas@novotny.cz>
Cc: Tom Rini <trini@ti.com>
2013-02-18 13:48:03 -05:00
Simon Glass
ea6bd08b77 nds32: Add a basic errno.h
This is available on other architectures, and nds32 will start to break
without it as code starts to use error numbers more.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-18 15:29:07 +08:00
Tom Rini
9f024f62e4 Merge branch 'fixes' of git://git.denx.de/u-boot-mips 2013-02-15 12:23:42 -05:00
Daniel Schwierzeck
455fbfb668 MIPS: board.c: remove manual relocation of env_name_spec
Remove the manual relocation of env_name_spec. This has been missed
in the previous patch series for introducing dynamic relocation
on MIPS.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-15 18:00:04 +01:00
Simon Glass
96dfc0633a x86: Remove unused real mode code
This code is pretty old and we want to support only 32-bit systems now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14 20:19:03 -08:00
Simon Glass
588a13f742 x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTOR
Invert the polarity of this option to simplify the Makefile logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gabe Black <gabeblack@chromium.org>
2013-02-14 20:18:58 -08:00
Simon Glass
1f3a581495 x86: Remove sc520 cpu
This x86 CPU variant is no longer required as the boards that use it have
been removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14 20:18:58 -08:00
Tom Rini
9c748e02d9 Merge branch 'next' of git://git.denx.de/u-boot-mips 2013-02-12 19:03:59 -05:00
Gabor Juhos
04380c651a MIPS: add dynamic relocation support
The code handles relocation entries with the
following relocation types only:
  mips32: R_MIPS_REL32
  mips64: R_MIPS_REL+R_MIPS_64
  xburst: R_MIPS_REL32

Other relocation entries are skipped without
processing. The code must be extended if other
relocation types must be supported.

Add -pie to LDFLAGS_FINAL to generate the .rel.dyn
fixup table, which will be applied to the relocated
image before transferring control to it.

The CONFIG_NEEDS_MANUAL_RELOC is not needed
after the patch, so remove that as well.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Gabor Juhos
0ba8926e08 MIPS: u-boot.lds: add relocation specific sections
This section contain the table needed for dynamic
relocation. Also provide symbols for the relocation
code to access the table.

Discard all sections which are not needed in the final
ELF binary and U-Boot image. Section .dynsym cannot be
discarded or GNU ld crashes otherwise. This section
will be stripped by GNU objcpy in a later patch.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Daniel Schwierzeck
28875e2c47 MIPS: start.S: use symbol __image_copy_end for U-Boot image relocation
Use the newly introduced symbol __image_copy_end as end address for
relocation of U-Boot image. This is needed for dynamic relocation added
in later patches. This patch obsoletes the symbols uboot_end and
uboot_end_data which are removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Daniel Schwierzeck
696a3b2a53 MIPS: start.S: optimize BSS initialization
Get the start and end address for clearing BSS from the newly
introduced symbols __bss_start and __bss_end. After GOT is
relocated, those symbols are already pointing to the correct
addresses.

Also optimize the loop by moving the address incrementation
to the delay slot to avoid the initial sub instruction.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:13 +01:00
Daniel Schwierzeck
eea8a320e1 MIPS: board.c: switch to new symbols __bss_end and __image_copy_end
Use the newly introduced symbols __image_copy_end and __bss_end
for setting up the memory area for the relocated U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
3420bf1ca0 MIPS: u-boot.lds: introduce symbol __image_copy_end
This symbol is used in later patches as end address
for relocation of the U-Boot image into RAM.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
a52852c5a6 MIPS: u-boot.lds: merge all BSS sections and introduce symbols __bss_[start|end]
These symbols are used in later patches for as addresses for
clearing the BSS area in the relocated U-Boot image.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Gabor Juhos
45397816b2 MIPS: compute num_got_entries from .got section's size
The '__got_start' and '__got_end' symbols are used
only in the linker script to compute the value of
the 'num_got_entries' symbol.

Remove the symbols and use the SIZEOF(.got) command
to get the size of the .got section.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
8b1c7345c6 MIPS: start.S: unify and simplify reset vector handling
Adopt reset vector handling from Yamon.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
4dc7412afa MIPS: start.S: remove obsolete 64 bit handling in setup_c0_status
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 22:22:12 +01:00
Daniel Schwierzeck
97b920dab1 MIPS: xburst: fix broken access to global_data
Fix access to global_data which is broken since commits:

commit 035cbe99cd
Author: Simon Glass <sjg@chromium.org>
Date:   Thu Dec 13 20:49:08 2012 +0000

    mips: Move per_clk and dev_clk to arch_global_data

    Move these field into arch_global_data and tidy up. The other
    CONFIG_JZSOC fields are used by various architectures, so just remove
    the #ifdef bracketing for these.

    Signed-off-by: Simon Glass <sjg@chromium.org>

commit 582601da2f
Author: Simon Glass <sjg@chromium.org>
Date:   Thu Dec 13 20:48:35 2012 +0000

    arm: Move lastinc to arch_global_data

    Move this field into arch_global_data and tidy up.

    Signed-off-by: Simon Glass <sjg@chromium.org>

commit 66ee692347
Author: Simon Glass <sjg@chromium.org>
Date:   Thu Dec 13 20:48:34 2012 +0000

    arm: Move tbl to arch_global_data

    Move this field into arch_global_data and tidy up.

    Signed-off-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-02-12 22:22:12 +01:00
Otavio Salvador
291b3dcd49 build: imx: Fix 'u-boot.imx' build without full OBJTREE reference
When calling 'make u-boot.imx' the build were failing as it were
expecting the full path for the file; this regression has been
included by commit 71a988a (imximage.cfg: run files through C
preprocessor).

The direct references for u-boot.imx were replaced by $(obj) as
config.mk handles the proper setting of it making it set to $(OBJTREE)
when required.

The build has been test using:

 - ./MAKEALL -s mx5 -s mx6
 - make u-boot.imx
 - make O=/tmp/build

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-02-12 18:39:08 +01:00
Tom Rini
951c6baaf4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-12 10:18:31 -05:00
Fabio Estevam
76c91e668a mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.

Comparing the watchdog behaviour on a revB versus revC board:

- On a mx6qsabresd revB:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...

- On a mx6qsabresd revC:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR

So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.

Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-12 13:54:34 +01:00
Lucas Stach
fd8e1c3866 arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
2013-02-11 10:35:26 -07:00
Tom Warren
8aff009585 Tegra114: Dalmore: Add DT files
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
e23bb6a438 Tegra114: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
ec1885cee1 Tegra114: Add CPU (armv7) files
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
4040ec10df Tegra114: Add AVP (arm720t) files
This provides SPL support for T114 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Tom Warren
2fc65e2834 Tegra114: Add arch-tegra114 include files
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Allen Martin
b19f57491a tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver.  This controller is
similar to the tegra20 SPI "SFLASH" controller.  The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices.  In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH.  Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.

This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings.  Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.

To enable this driver, use CONFIG_TEGRA_SLINK

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00
Allen Martin
91673e2adf tegra: add addresses of SPI SLINK controllers
Add I/O addresses of SPI SLINK controllers 1-6

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Allen Martin
23e3158f34 tegra30: fdt: add SPI SLINK nodes
Add tegra30 SPI SLINK nodes to fdt.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Allen Martin
7d54f022bb tegra30: add SBC1 to periph id mapping table
SBC1 is SPI controller 1 on tegra30

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Allen Martin
c98f03fae0 tegra20: fdt: add SPI SFLASH node
Add node for tegra20 SPI SFLASH controller to fdt.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Stephen Warren
4727a13bde tegra: rename FUNCMUX_UART2_UARTB
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Tom Warren
f29f086a09 Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c

Some T30 tables needed whitespace fixes due to checkpatch complaints.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:24 -07:00
Tom Warren
d83152d8e4 Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entry
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:23 -07:00
Gerald Van Baren
58864ddc72 Clean up libfdt.h includes
The libfdt.h file is the definition file for libfdt.  It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).

Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2013-02-08 22:32:38 -05:00
Kim Phillips
8aa5ec6e16 common/fdt_support.c: sparse fixes
trivial:

fdt_support.c:89:64: warning: Using plain integer as NULL pointer
fdt_support.c:325:65: warning: Using plain integer as NULL pointer
fdt_support.c:352:65: warning: Using plain integer as NULL pointer

For the following bad constant expression, We hardcode the max. number of
memory banks to four for the foreseeable future, and add an error with
instructions on what to do once it's exceeded:

fdt_support.c:397:22: error: bad constant expression

For the rest below, sparse found a couple of wrong endian conversions
in of_bus_default_translate() and fdt_get_base_address(), but
otherwise the rest is mostly annotation fixes:

fdt_support.c:64:24: warning: cast to restricted __be32
fdt_support.c:192:21: warning: incorrect type in assignment (different base types)
fdt_support.c:192:21:    expected unsigned int [unsigned] [usertype] tmp
fdt_support.c:192:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:201:21: warning: incorrect type in assignment (different base types)
fdt_support.c:201:21:    expected unsigned int [unsigned] [addressable] [usertype] tmp
fdt_support.c:201:21:    got restricted __be32 [usertype] <noident>
fdt_support.c:304:13: warning: incorrect type in assignment (different base types)
fdt_support.c:304:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:304:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:333:13: warning: incorrect type in assignment (different base types)
fdt_support.c:333:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:333:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:359:13: warning: incorrect type in assignment (different base types)
fdt_support.c:359:13:    expected unsigned int [unsigned] [usertype] val
fdt_support.c:359:13:    got restricted __be32 [usertype] <noident>
fdt_support.c:373:21: warning: cast to restricted __be32
fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:963:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:963:48:    got unsigned int [usertype] *<noident>
fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:971:48:    expected restricted __be32 const [usertype] *p
fdt_support.c:971:48:    got unsigned int [usertype] *<noident>
fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types)
fdt_support.c:984:29:    expected restricted __be32 const [usertype] *cell
fdt_support.c:984:29:    got unsigned int [usertype] *addr
fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types)
fdt_support.c:996:32:    expected restricted __be32 const [usertype] *cell
fdt_support.c:996:32:    got unsigned int [usertype] *addr
fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1041:41:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1041:41:    got unsigned int [usertype] *addr
fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1053:41:    expected restricted __be32 const [usertype] *range
fdt_support.c:1053:41:    got unsigned int const [usertype] *[assigned] ranges
fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1064:53:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1064:53:    got unsigned int [usertype] *addr
fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1110:50:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1110:50:    got unsigned int *<noident>
fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1121:49:    expected restricted __be32 const [usertype] *cell
fdt_support.c:1121:49:    got unsigned int *<noident>
fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1147:60:    expected restricted __be32 const [usertype] *addr
fdt_support.c:1147:60:    got unsigned int *<noident>
fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static?
fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types)
fdt_support.c: In function 'fdt_node_offset_by_compat_reg':
fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]

See also linux kernel commit 0131d897 "of/address: use proper
endianess in get_flags".

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Kim Phillips
12e06fe03f treewide: include libfdt_env.h before fdt.h
and, if including libfdt.h which includes libfdt_env.h in
the correct order, don't include fdt.h before libfdt.h.

this is needed to get the fdt type definitions set from
the project environment before fdt.h uses them.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Jeff Lance
13526f7157 Add DDR3 support for AM335x-EVM (Version 1.5A)
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.

[Hebbar Gururaja <gururaja.hebbar@ti.com>]
	- Resolve merge conflict while rebasing. File structure is
	  changed in the mainline. So re-arrange the code accordingly.
	- Update commit message to reflect the DDR3 part number

Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
2013-02-07 10:36:26 -05:00
Lars Poeschel
1c1b7c3739 pcm051: Add support for Phytec phyCORE-AM335x
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: RV-4162-C7
I2C-EEPROM: CAT32WC32
NAND: MT29F4G08_VFPGA63
PMIC: TPS65910A3
LCD

Supported:
UART 1
MMC/SD
ETH 1
USB
I2C
SPI

Not yet supported:
NAND
RTC
LCD

Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
[trini: Add #define CONFIG_PHY_ADDR 0 to config]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-07 10:36:26 -05:00
Lars Poeschel
aca0b8b4f7 am33xx: add a pulldown macro to pinmux config
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
2013-02-07 10:36:25 -05:00
Michal Simek
00ed345898 arm: zynq: Add lowlevel initialization to C
Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00
Michal Simek
59c651f4e2 arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00
Tom Rini
2d795c9621 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2013-02-04 09:14:22 -05:00
Simon Glass
43cff66e03 x86: Use generic global_data
Move x86 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
1e5f8bd0bc sparc: Use generic global_data
Move sparc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
a987902753 sh: Use generic global_data
Move sh over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
07d59bb243 sandbox: Use generic global_data
Move sandbox over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
2ab575e05d powerpc: Use generic global_data
Move powerpc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
6f8b28520d openrisc: Use generic global_data
Move openrisc over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
1f7559ec38 nios2: Use generic global_data
Move nios2 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
2013-02-04 09:05:46 -05:00
Simon Glass
ee22c1a214 nds32: Use generic global_data
Move nds32 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
9572202026 mips: Use generic global_data
Move mips over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
eef5415036 microblaze: Use generic global_data
Move microblaze over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <monstr@monstr.eu>
2013-02-04 09:05:45 -05:00
Simon Glass
e56b250735 m68k: Use generic global_data
Move m68k over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
06b507b85c blackfin: Use generic global_data
Move blackfin over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
47a9789f25 avr32: Use generic global_data
Move avr32 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
baa1e53683 arm: Use generic global_data
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
8ee666a76f sandbox: Move ram_buf to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
3d0f8c8f80 avr32: Move cpu_hz to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:45 -05:00
Simon Glass
1c865d5897 avr32: Move stack_end to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
035cbe99cd mips: Move per_clk and dev_clk to arch_global_data
Move these field into arch_global_data and tidy up. The other
CONFIG_JZSOC fields are used by various architectures, so just remove
the #ifdef bracketing for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7e2592fd5a m68k: Move CONFIG_EXTRA_CLOCK to arch_global_data
Move inp_clk, vco_clk and flb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
fa25c6f0cc sparc: Drop kbd_status and reset_status from global_data
These fields is not used on sparc, so punt them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
e9adeca3fc ppc: arm: Move sdhc_clk into arch_global_data
This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
225ca83dfe ppc: Move kbd_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
a0d3c820c4 ppc: Move wdt_last to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
923a662f2f ppc: Move fpga_state to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7273ccec61 ppc: Remove console_addr from global data
This does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
7e15d6dbf3 ppc: Move mirror_hack to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:44 -05:00
Simon Glass
3a1dc8f125 arm: Move uart_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
6bb9ba7260 ppc: Move dp_alloc_base, dp_alloc_top to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
43e60814b3 ppc: Move arbiter fields to arch_global_data
Move arbiter_event_attributes and arbiter_event_address into
arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
3c4c308c00 ppc: Move reset_status to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
1c356135fa ppc: Move mpc8220 clocks to arch_global_data
Move these fields into arch_global_data and tidy up. The bExtUart field
does not appear to be used, so punt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
fefb098b18 ppc: Move mpc512x clocks to arch_global_data
Move ips_clk and csb_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
b28774966c ppc: Move mpc5xxx clocks to arch_global_data
Move ipb_clk and pci_clk into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
7c80c6c51a ppc: Move used_tlb_cams to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
8670dbc953 ppc: Move used_laws to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:43 -05:00
Simon Glass
45bae2e3cf ppc: Move CONFIG_QE to arch_global_data
Move the quantative easing fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
609e6ec3f6 ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_data
Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:42 -05:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
David Holsgrove
2281ba5172 microblaze: Add muldi3.c which contains routines for _muldi3
Referenced arch/blackfin/lib/muldi3.c and the linux kernel.
Resolves issue seen when building u-boot for HW_MUL=0;

PLATFORM_CPPFLAGS += -mxl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-multiply-high

which resulted in error while linking to libgcc.a without mul hw (bs / m);

libgcc.a(_muldi3.o): In function `__muldi3':
.... src/gcc-4.6.2/libgcc/libgcc2.c:550: undefined reference to `_GLOBAL_OFFSET_TABLE_'

This link failure would not occur if we used gcc instead of ld directly, as
gcc will correctly use the crt's to resolve this link.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04 12:07:09 +01:00
Rob Herring
2ff467c051 ARM: add wfi assembly macro
Since wfi instruction is only available on ARMv7, add a conditional
macro for it.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-02-03 14:43:58 +01:00
Albert ARIBAUD
e5f5c4a977 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-02-02 19:29:59 +01:00
Simon Glass
c6731fe22a ppc: Move mpc83xx clock fields to arch_global_data
Move al mpc83xx fields into arch_global_data and tidy up. Also indent
the nested #ifdef for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
748cd0591a ppc: Move clock fields to arch_global_data
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
9fb23624a6 ppc: Remove extra pci_clk fields from global_data
PPC has several of these fields, selected by chip type, although only one
is ever compiled in.

Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
1206c18403 ppc: Move brg_clk to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:42:45 -05:00
Simon Glass
6cb49c13f6 x86: Remove reset_status, relocoff from global_data
These fields are not used on x86, so punt them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:40:31 -05:00
Simon Glass
5a35e6c48e x86: Move gd_addr into arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add arch/x86/cpu/cpu.c changes after Graeme's comments]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:39:42 -05:00
Simon Glass
0cecc3b679 x86: Set up the global data pointer in C instead of asm
We currently assume that the global data pointer is at the start of
struct global_data. We want to remove this restriction, and it is
easiest to do this in C.

Remove the asm code and add equivalent code in C.

This idea was proposed by Graeme Russ here:
   http://patchwork.ozlabs.org/patch/199741/

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Apply Graeme Russ' comments
http://patchwork.ozlabs.org/patch/206305/ here, re-order]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:36:53 -05:00
Simon Glass
df4aa625a2 x86: Remove gdt_addr from arch_global_data
Remove this unused field.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:35:15 -05:00
Simon Glass
34fd5d253d arm: Move tlb_addr and tlb_size to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Address tlb_size in this patch as well]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:21:58 -05:00
Simon Glass
37434783bb nds32: Drop tlb_addr from global data
This field doesn't appear to be used for anything important, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
b4d51db86b ixp: Move timestamp to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
5f70714c2f arm: Move timer_reset_value to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
582601da2f arm: Move lastinc to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
66ee692347 arm: Move tbl to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
8ff43b03e9 arm: Move tbu to arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:50 -05:00
Simon Glass
b339051c0d arm: Move timer_rate_hz into arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Simon Glass
f47e6ecd5d at91: Move at91 global data into arch_global_data
Move these fields into arch_global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Simon Glass
5cb48582ac Add architecture-specific global data
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.

As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.

This patch applies to all archs at once. I can split it if this is really
a pain.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Lucas Stach
4e5eb45898 arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
2013-01-30 19:33:01 -05:00
Tom Rini
b6832af850 Merge branch 'master' of git://git.denx.de/u-boot-mips 2013-01-30 19:26:38 -05:00
Gabor Juhos
cb5dbca899 MIPS: add unified u-boot.lds file
The patch adds an unified linker script file which
can be used for all currently supported MIPS targets.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Stefan Roese <sr@denx.de>
2013-01-31 00:26:59 +01:00
Gabor Juhos
9950b90d38 MIPS: remove OUTPUT_FORMAT from linker scripts
The OUTPUT_FORMAT command in linker scripts
was always misused due to some endianess and
toolchain problems.

Use GCC flags to ensure proper output format,
and get rid of the OUTPUT_FORMAT commands in
the board specific u-boot.lds files.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30 23:34:10 +01:00
Gabor Juhos
6d86227880 MIPS: xburst: simplify relocation offset calculation
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.

The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.

This approach makes the code a bit simpler because
it needs two instructions only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30 23:33:27 +01:00
Gabor Juhos
025f2b3380 MIPS: simplify relocated _G_O_T_ address calculation
The difference between the address of the original
and the relocated _GLOBAL_OFFSET_TABLE_ is always
the same as the relocation offset.

The relocation offset is already computed and it is
available in the 's1/t6' register. Use that to adjust
the relocated _G_O_T_ address, instead of calculating
the offset again from the _gp value.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30 23:32:52 +01:00
Shengzhou Liu
72bd83cd0a powerpc/t4240: Adding workaround errata A-005871
When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.

This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.

The Workaround is for the T4240 silicon rev 1.0.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Vakul Garg
5e95e2d84b powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Anatolij Gustschin
5b93394318 mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE
Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in
the board config file doesn't work and memory is always initialized
to the value 0xdeadbeef. Only use this default value if a board doesn't
define CONFIG_MEM_INIT_VALUE.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Scott Wood
31d084ddda powerpc/mpc85xx: add support for MMUv2 page sizes
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Prabhakar Kushwaha
35fe948e3b powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
James Yang
e8ba6c503f powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands
This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable.  Commands are separated using ';'.

ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
James Yang
5926ee3800 Add copy command to FSL DDR interactive
Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
James Yang
992f2fb28c Fix data stage name matching issue
This fix allows the name of the stage to be specifed after the
controler and DIMM is specified.  Prior to this fix, if the
data stage name is not the first entry on the command line,
the operation is applied to all controller and DIMMs.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
James Yang
bf4189307f Move DDR command parsing to separate function
Move the FSL DDR prompt command parsing to a separate function
so that it can be reused.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:13 -06:00
York Sun
e750cfaa01 powerpc/mpc8xxx: Enable entering DDR debugging by key press
Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.

CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:12 -06:00
Prabhakar Kushwaha
db9a807054 powerpc/mpc85xx:Fix Core cluster configuration loop
Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e1dbdd8152 powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e394ceb17f powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
York Sun
2d9f26b693 powerpc/mpc85xx: Reserve default boot page
The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Tom Rini
06b02c58d2 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2013-01-29 15:36:23 -05:00
Marek Vasut
90bc2bf297 mxs: mmc: Allow overriding default card detect implementation
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
f3801e2b9b mxs: ssp: Add SSP registers map for MX23
The MX23 SSP register layout differs from MX28 in certain bits,
adjust the register layout accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
0e5c05efb4 mxs: dma: Fix APBH DMA driver for MX23
The MX23 has less channels for the APBH DMA, sligtly different register
layout and some bits in those registers are placed differently. Reflect
this in the driver. This patch fixes MMC/DMA issue on MX23.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:00 +01:00
Fabio Estevam
f093088214 mxs: Use __weak annotation to simplify code
Using the __weak annotation can make the code cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-28 06:54:19 +01:00
Marek Vasut
8303ed128a mxs: Boost the memory power supply
The memory power supply on MX23 didn't pump out enough juice into
the DRAM chip, thus caused occasional memory corruption. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-01-28 06:40:38 +01:00
Gabor Juhos
67d80c9f97 MIPS: start.S: don't save flush_cache parameters in advance
Saving the parameters in advance unnecessarily complicates
the code. The destination address is already saved in the
's2' register, and that register is not clobbered by the
copy loop. The size of the copied data can be computed
after the copy loop is done.

Change the code to compute the size parameter right
before calling flush_cache, and set the destination
address parameter in the delay slot of the actuall
call.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:40:15 +01:00
Gabor Juhos
248fe03f53 MIPS: start.S: simplify relocation offset calculation
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.

The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.

This approach makes the code a bit simpler because
it needs two instructions only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:40:07 +01:00
Gabor Juhos
b2fe86f887 MIPS: start.S: save reused arguments earlier in relocate_code
Save the reused parameters at the beginning
of the 'relocate_code' function. This makes
the function a bit more readable.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:59 +01:00
Gabor Juhos
f321b0f99f MIPS: start.S: set sp register directly
The current code uses two instructions to load
the stack pointer into the 'sp' register.

This results in the following assembly code:

    468:   3c088040        lui     t0,0x8040
    46c:   251d0000        addiu   sp,t0,0

The first instuction loads the stack pointer into
the 't0' register then the value of the 'sp' register
is computed by adding zero to the value of the 't0'
register. The same issue present on the 64-bit version
as well:

    56c:   3c0c8040        lui     t0,0x8040
    570:   659d0000        daddiu  sp,t0,0

Change the code to load the stack pointer directly
into the 'sp' register. The generated code is functionally
equivalent to the previous version but it is simpler.

  32-bit:
    468:   3c1d8040        lui     sp,0x8040

  64-bit:
    56c:   3c1d8040        lui     sp,0x8040

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:51 +01:00
Gabor Juhos
5b7dd8163d MIPS: start.S: fix boundary check in relocate_code
The loop code copies more data with one than
necessary due to the 'ble' instuction. Use the
'blt' instruction instead to fix that.

Due to the lack of suitable hardware the Xburst
specific code is compile tested only. However the
change is quite obvious.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:43 +01:00
Gabor Juhos
14fdd1a8bf MIPS: start{, 64}.S: fill branch delay slots with NOP instructions
The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 21:09:34 +01:00
Gabor Juhos
0ef48d4c89 MIPS: convert IO port accessor functions to 'static inline'
The currently used 'extern inline' directive causes
the following compiler warnings if CONFIG_SWAP_IO_SPACE
is defined:

  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw' which is not static [enabled by default]

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 21:07:19 +01:00
Gabor Juhos
be002d0070 MIPS: use inline directive for __in*s functions
All other IO accessor functions are using the
'inline' directive. Use that also for the __in*s
to make it consistent with the other variants.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 20:52:08 +01:00
Troy Kisky
71a988aa63 imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.

The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile

.gitignore was updated to ignore .cfgtmp files.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-22 10:20:13 +01:00
Otavio Salvador
0023997709 mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Otavio Salvador
30af6c0bca mxs: Fix the memory init for MX23
The memory init is slightly different on MX23, thus split the memory
init for mx23 and mx28 into different functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Marek Vasut
7788bf067d mxs: Add function to ungate the power block on MX23
The power block on MX23 must first be ungated before it can be operated.
Add function to MXS power init that ungates it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00
Otavio Salvador
e6d93c26c7 mx23: config: Enable building of u-boot.sb binary
For i.MX23 we need to pass imx23 as elftosb param.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
1ddf386e23 mx23: SPL: Initialize DDR at 133MHz
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
f942f7d962 mx23: SPL: Add boot mode support
This adds the boot mode support for i.MX23 processors.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
a8b2884d94 mx23: Add boot mode description
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:21 +01:00
Otavio Salvador
f69077e420 mx23: Add support on print_cpuinfo()
Add information to identify i.MX23 chips and its known revisions.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
95e873d601 mx23: ssp: Fix ssp-regs.h for MX23
Disable SSP2 and SSP3 ports on MX23.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
06dc8160a0 mx23: Add POWER and CLKCTRL register definitions
Add register definitions for the i.MX23 power control block and
clock control block. These are essential for the basic bootstrap
of the i.MX23. Also, properly include them in imx-regs.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
180f47a8df mx23: Add iomux-mx23.h
This has been copied from Linux source at revision 786f02b719f.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
3fd7f365e1 mx23: Add register base addresses
This adds the base addresses of i.MX23 and easy the detection of wrong
order in board setup, in case no SoC has been set, an error is raised
during build.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Otavio Salvador
bf48fcb61b mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Marek Vasut
14e26bcfa7 mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:19 +01:00
Allen Martin
64e6ec1d4e tegra: fdt: add apbdma node
Add apbdma node for tegra20 and tegra30, copied directly from tegra
Linux dtsi files.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-17 09:07:51 -07:00
Allen Martin
b7723f3f30 tegra: fdt: sort dts files
Sort nodes in dts files according the the following rules:

1) Any nodes that already exist in any /include/d file, in the order
they appear in the /include/d file.

2) Any nodes with a reg property, in order of their address.

3) Any nodes without a reg property, alphabetically by node name.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-17 09:07:34 -07:00
Allen Martin
d3f8752ed6 tegra: fdt: remove clocks nodes
These nodes are unused.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-17 09:07:23 -07:00
Kim Phillips
a6187dccd8 Merge remote-tracking branch 'mpc83xx/next' 2013-01-16 18:34:09 -06:00
Allen Martin
d08b9e9c7e tegra: remove IRDA pinmux synonym
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this
synonym and replace with UARTB to disambiguate.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
083bbbbe77 Tegra30: fdt: Update DT files with I2C info for T30/Cardhu
Note that T30 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
DVC_I2C is still used to designate the controller intended for
power control (PWR_I2C in the schematics). On Cardhu, it's used
to access the PMU and EEPROM, as well as the audio codec, temp
sensor, and fuel gauge devices from the OS.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
619bd99e5c Tegra30: clocks: Fix clock tables for I2C and other periphs
Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
6d6c0baebe Tegra30: Add generic Tegra30 build support
This patch adds basic Tegra30 (T30) build support - no specific
board is targeted.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
79ce91bade Tegra30: Cardhu: Add DT files
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:08 -07:00
Tom Warren
b2871037d2 Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-01-16 13:40:07 -07:00
Tom Warren
5576aab517 Tegra30: Add CPU (armv7) files
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidai.com>
2013-01-16 13:40:07 -07:00
Tom Warren
1b245fee91 Tegra30: Add AVP (arm720t) files
This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.

Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-01-16 13:40:07 -07:00
Tom Warren
dc89ad1438 Tegra30: Add arch-tegra30 include files
Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-01-16 13:40:07 -07:00
Marc Dietrich
716d943983 tegra: display: add board pinmux
Boards may require a different pinmux setup for DISPALY than the default one.
Add a way to call into board specific code to set this up.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-16 13:40:07 -07:00
Gabor Juhos
9c170e2ef4 MIPS: bootm.c: add support for 'prep' and 'go' subcommands
The bootm command supports subcommands since long time
however those subcommands are not yet usable on MIPS.

The patch is based on the ARM implementation, and it adds
support for the 'prep' and 'go' subcommands only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 10:52:07 +01:00
Gabor Juhos
0ea7213f63 MIPS: bootm.c: separate environment initialization
Move the environment initialization code into a
separate function. This make the code reusable
for bootm subcommands.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 10:52:07 +01:00
Gabor Juhos
e08634c7bf MIPS: bootm.c: separate linux jump code
Move the actual jump code into a separate function.
This make the code reusable for bootm subcommands.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 10:52:07 +01:00
Gabor Juhos
75a279c8f2 MIPS: bootm.c: use debug macro to print debug message
The '## Transferring control ...' message is printed
only if DEBUG is enabled. Get rid of the 'ifdef DEBUG'
statement and use the debug macro instead.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-01-16 10:52:07 +01:00
Łukasz Dałek
df3ad6c81d pxa: Save lr register in relocate_code function
When u-boot is compiled for PXA25x processor, pxa/start.S is calling
cpu_init_crit by BL instruction. BL is overwriting lr register so
relocate_code is going into infinite loop. This patch preservs lr
register in r12 before calling cpu_init_crit and after function returns
restores it.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-14 16:22:00 -07:00
Albert ARIBAUD
a17617d655 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-01-14 17:00:02 +01:00
Albert ARIBAUD
1199c377cf Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-01-14 15:21:00 +01:00
Troy Kisky
abbab70363 mx31/mx35/mx51/mx53/mx6: add watchdog
Use a common watchdog driver for all these cpus.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-13 11:39:57 +01:00
angelo
fd70aa4146 m68k/lib: fix serial driver relocation
Fix coldfire serial driver bindings no more relocated to ram after last
changes to drivers/serial/serial.c (regression).
Serial initialization in ram has to be called after that gd->reloc_off is
calculated.

Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
2013-01-11 14:41:14 -07:00
Tom Rini
7a8e739cd5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-11 14:38:24 -07:00
Jaehoon Chung
5374d386f8 Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk
Mobile storage is used the CLK_DIV_FSYS3 value.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11 16:56:31 +09:00
Jaehoon Chung
c39e969e8e Exynos: clock: support get_mmc_clk for exynos
To get exactly clock value for mmc, support the get_mmc_clk() like
set_mmc_clk().

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11 16:56:31 +09:00
Taylor Hutt
80e409508b arm: Tabify code for MMC initialization
The two modified lines were indented with spaces.
They are now indented with tabs.

Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:28:36 +01:00
Simon Glass
2f8d8d6b3a arm: Move bootstage record for board_init_f() to after arch_cpu_init()
The timer may be inited in arch_cpu_init() so it is not safe to make a
bootstage mark before this is called. Arrange the code to fix this.

Note: The question was raised as to why we don't keep all archs in sync.
PowerPC doesn't have specific bootstage markers at present (although it
does use boot progress). I hope that the generic board series will solve
this problem in general, but in the meantime this is a real problem, and
only in ARM.

We now get a correct time for board_init_f:

Timer summary in microseconds:
       Mark    Elapsed  Stage
          0          0  reset
    100,000    100,000  spl_start
    848,530    748,530  board_init_f
    907,301     58,771  board_init_r
    910,478      3,177  board_init

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:27:41 +01:00
Tom Wai-Hong Tam
fe34f8dc8c arm: Make interrupts.o and reset.o in libarm also appear in SPL
SPL u-boot may call do_reset() which depends on interrupts.o and reset.o.
So make them also appear in SPL.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:22:15 +01:00
Simon Glass
e2e3e2b1be arm: Add CONFIG_DISPLAY_BOARDINFO_LATE to display board info on LCD
This option displays board info after stdio is running, so that it will
appear on the LCD. If it is displayed earlier, the board info will appear
on the serial console but not on the LCD.

Here follows a blow-by-blow description.

1a. Without CONFIG_DISPLAY_BOARDINFO_LATE, on serial:

U-Boot 2011.12-02550-g037e1c5-dirty (Nov 15 2012 - 14:29:42) for SMDK5250

CPU:   S5PC520 @ 1700MHz

Board: Google Snow, rev 0
I2C:   ready
DRAM:  2 GiB Elpida DDR3 @ 800MHz
MMC:   S5P MSHC0: 0, S5P MSHC1: 1
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

1b. Without CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info
is missing):

In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

2a. With CONFIG_DISPLAY_BOARDINFO_LATE, on serial:

U-Boot 2011.12-02550-g037e1c5 (Nov 15 2012 - 14:27:40) for SMDK5250

CPU:   S5PC520 @ 1700MHz
I2C:   ready
DRAM:  2 GiB Elpida DDR3 @ 800MHz
MMC:   S5P MSHC0: 0, S5P MSHC1: 1
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

Model: Google Snow
In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

2b. With CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is present):

Model: Google Snow
In:    mkbp-keyb
Out:   lcd
Err:   lcd
Net:   No ethernet found.
Hit any key to stop autoboot:  0
SMDK5250 #

Since the LCD is all that a typical user sees, it is useful to display
the model there.

We may be able to rearrange things some other way one day, but at
present this seems like a convenient way of getting the required
behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:22:01 +01:00
Simon Glass
06fd853890 arm: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

Any time you load untrusted data you expose yourself to a bug in the
code. The attacker gets to choose the data so can sometimes carefully
craft it to exploit a bug. We try to avoid touching user-controlled
data during a verified boot unless strictly necessary. Since the
default environment is good enough in this case (or you would just
change it), this gets around the problem by just not loading the
environment.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loading of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
2013-01-10 22:21:47 +01:00
Simon Glass
eae78c3406 arm: Move fdt check earlier so that board_early_init_f() can use it
We want to use the fdt inside board_early_init_f(), so check for its
presence earlier in the pre-reloc init sequence.

So far ARM and microblaze are the only only ones that use
CONFIG_OF_CONTROL. Microblaze does not have the same init loop, and in
particular does not have the board_early_init_f() call. So a patch for
microblaze would have no meaning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:21:44 +01:00
Gabe Black
724cdffca1 arm: Keep track of the tlb size as well as its location
It may be necessary to know where the TLB area ends as well as where it
starts. This allows board code to complete a secure memory erase without
destroying the page tables.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:21:32 +01:00
Arun Mankuzhi
44df5e8d30 arm: move flush_dcache_all() to just before disable cache
In Cortex-A15 architecture, when we run cache invalidate
the cache clean operation executes automatically.
So if there are any dirty cache lines before disabling the L2 cache
these will be synchronized with the main memory when
invalidate_dcache_all() runs in the last part of U-boot

The two functions after flush_dcache_all is using the stack. So this
data will be on the cache. After disable when invalidate is called the
data will be flushed from cache to memory. This corrupts the stack in
invalida_dcache_all. So this change is required to avoid the u-boot
hang.

So flush has to be done just before clearing CR_C bit

Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-10 22:21:27 +01:00
Ajay Kumar
7b4bd121b6 EXYNOS: Add dummy definition to fix compilation dependency on CONFIG_EXYNOS_MIPI_DSIM
When only DP is used, we need not enable CONFIG_EXYNOS_MIPI_DSIM.
But if we do not select CONFIG_EXYNOS_MIPI_DSIM, exynos_fb.c throws
error saying exynos_mipi_dsi_init() not defined. So, we add
dummy definition for exynos_mipi_dsi_init when CONFIG_EXYNOS_MIPI_DSIM
is not defined.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Ajay Kumar
1673f199d9 EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Ajay Kumar
9b572852c0 EXYNOS5: Add support for FIMD and DP
Add panel_info structure required by LCD driver
and DP panel platdata for SMDK5250.
Add GPIO configuration for LCD.
Enable FIMD and DP support on SMDK5250.
DP Panel size: 2560x1600.
We use 16BPP resolution to get LCD console.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chomium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10 10:19:47 +09:00
Albert ARIBAUD
612404c28a Merge 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-01-09 20:01:48 +01:00
Fabio Estevam
2b16e51c2f mx6: Add workaround for ARM errata
Add workaround for the following ARM errata: 743622 and 751472.

The motivation for this change is the following kernel commit 62e4d357a
(ARM: 7609/1: disable errata work-arounds which access
secure registers), which removes the errata from multiplatform kernel.

Since imx has been converted to multiplatform in the kernel, we need to apply
such workarounds into the bootloader.

Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel.

Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad"
document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-09 19:22:06 +01:00
Albert ARIBAUD
ea33fb1a32 Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master' 2013-01-09 16:57:03 +01:00
Tom Rini
642ef40bdc Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-09 08:13:22 -07:00
Luke Lowrey
3e75e69668 arch-kirkwood: Ethernet port macro returning incorrect address
Modified the arch-kirkwood header so KWGBE_PORT_SERIAL_CONTROL1_REG(x)
returns the correct address.

Originally calling KWGBE_PORT_SERIAL_CONTROL1_REG(1) returned the
address for port 0 and vice versa.

Doesn't have any knock on effects to the u-boot code as the only
time they're used is to do the same function to both addresses

Signed-off-by: Luke Lowrey <luke@chamsys.co.uk>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-01-09 04:12:11 +05:30
Albert ARIBAUD
9d86f0c30b kirkwood: make MPP arrays static const
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 04:12:10 +05:30
Tom Rini
91c038f087 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-08 14:26:42 -07:00
Albert ARIBAUD
61bdb91335 arm: remove useless code in start.S files
Remove code such as unneeded includes or labels.
These removals have no functional effect.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-08 22:14:54 +01:00
Albert ARIBAUD
e05e5de7fa arm: move C runtime setup code in crt0.S
Move all the C runtime setup code from every start.S
in arch/arm into arch/arm/lib/crt0.S. This covers
the code sequence from setting up the initial stack
to calling into board_init_r().

Also, rewrite the C runtime setup and make functions
board_init_*() and relocate_code() behave according to
normal C semantics (no jumping across the C stack any
more, etc).

Some SPL targets had to be touched because they use
start.S explicitly or for some reason; the relevant
maintainers and custodians are cc:ed.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-08 22:14:50 +01:00
Albert ARIBAUD
79f3877794 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
2013-01-08 13:15:45 +01:00
Rajeshwari Shinde
69c6f976a1 EXYNOS5: Add device node for USB.
This patch adds the device node required for USB

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 21:14:34 +09:00
Rajeshwari Shinde
cb9b23cda9 EXYNOS5: FDT: Add SPI device node data
Add SPI device node data for exynos.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:34 +09:00
Rajeshwari Shinde
f0b1619118 EXYNOS5: FDT: Add sound device node data
Add sound device node data for exynos

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:33 +09:00
Rajeshwari Shinde
d055911887 EXYNOS5: FDT : Decode peripheral id
Api is added to decode peripheral id based on the interrupt number
of the peripheral.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:32 +09:00
Rajeshwari Shinde
c2425b66c3 EXYNOS5: FDT: Add I2C device node data
Add I2C device node data for exynos

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:54:32 +09:00
Piotr Wilczek
7a84e1fa22 arm:exynos4:pinmux: Modify the gpio function for mmc
This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-08 10:47:45 +09:00
Chander Kashyap
a527757316 EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
Adds functions to extract clock frequency of Exynos4x12 IPs.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 21:12:43 +09:00
Hatim RV
3ea93948cf exynos5: Add DT based driver for SMC911X ethernet
Add device tree based ethernet driver for SMC911X controller on
SMDK5250 boards.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 19:26:25 +09:00
Hatim RV
1b652071d0 EXYNOS5: FDT: add initial dts file for EXYNOS5250, SMDK5250
This patch adds initial dts file for EXYNOS5250 SoC. This dts
file currently include only ethernet devices and properties. More
devices to be added in subsequent patches.
Also add the dts file for SMDK5250 board which uses the EXYNOS5250
dts file.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 19:26:25 +09:00
Chander Kashyap
fa442bbb3f EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
This patch adds gpio structure for Exynos4x12.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 16:16:02 +09:00
Chander Kashyap
07235ef8a3 EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
This patch adds clock structure for Exynos4x12.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 16:16:02 +09:00
Chander Kashyap
b189a83a08 EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
This patch populates base addresses of Exynos4x12 registers.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26 16:16:02 +09:00
Tom Rini
da77a0e593 Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-12-22 05:55:19 -07:00
Albert ARIBAUD
96764df1b4 Merge samsung, imx, tegra into u-boot-arm/master
This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes.
2012-12-22 11:59:14 +01:00
Yoshihiro Shimoda
1a2621bab8 sh: add support for sh7752evb board
The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch supports the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-12-20 13:20:17 +09:00
Scott Wood
06f60ae3e4 powerpc/mpc83xx: add support for new SPL
This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs
using the new infrastructure.

Existing nand_spl targets are updated to deal with the name change
from nand_init.c to spl_minimal.c (as in theory this isn't limited
to NAND anymore).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-12-19 17:45:44 -06:00
Allen Martin
a098cf41fd Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged
Conflicts:
	README
	arch/arm/cpu/armv7/exynos/clock.c
	board/samsung/universal_c210/universal.c
	drivers/misc/Makefile
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/seaboard.h
2012-12-19 13:02:36 -08:00
Joe Hershberger
ec8a252cd4 env: Use getenv_yesno() more generally
Move the getenv_yesno() to env_common.c and change most checks for
'y' or 'n' to use this helper.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-12-13 11:46:55 -07:00
Tom Rini
caddc17f30 Merge branch 'master' of git://git.denx.de/u-boot-mips 2012-12-12 06:51:02 -07:00
Joe Hershberger
f88e09de8d mips: serial: Fix busted manual relocation
serial_initialize() must be called after relocation to adjust the
pointers to putc(), getc(), etc.  This is busted ever since the
serial driver-model-ification series.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-12 13:20:24 +01:00
Daniel Schwierzeck
f0c27993e4 MIPS: constify mips_io_port_base
mips_io_port_base is exported as 'extern const unsigned long mips_io_port_base;'
in arch/mips/include/asm/io.h. Thus make the variable const too.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-12 13:14:16 +01:00
Simon Glass
b1f17bf5ff Add strcasecmp() and strncasecmp()
strncasecmp() is present as strnicmp() but disabled. Make it available
and define strcasecmp() also. There is a only a small performance penalty
to having strcasecmp() call strncasecmp(), so do this instead of a
standalone function, to save code space.

Update the prototype in arch-specific headers as needed to avoid warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-11 13:17:34 -07:00
Piotr Wilczek
89bd58a1e9 exynos:pinmux: Add pinmux support for i2c
This patch add pinmux for I2C for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Piotr Wilczek
847ab8f6e2 exynos:cpu: Add Exynos4 I2C spacing
This patch add the spacing for i2c for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Piotr Wilczek
83d745dd88 exynos:clock: Add i2c clock
This patch adds i2c clock for Exynos4

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2012-12-11 13:17:31 -07:00
Marek Vasut
fa5e2845a8 mxs: i2c: Implement algorithm to set up arbitrary i2c speed
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.

The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
2012-12-11 13:17:30 -07:00
Nikita Kiryanov
dcee1ab320 gpio: add gpio_is_valid() to omap_gpio API
Add gpio_is_valid() to omap_gpio API

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-12-10 12:45:35 -07:00
Davide Bonfanti
21f11c7b49 davinci: fixed cpu reset
The reset procedure works on watchdog timer while before it was modifying
TIMER_1 registers.
Tested on DM365.

Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
2012-12-10 08:56:38 -07:00
Lokesh Vutla
86021143a3 omap: emif: configure emif only when required
DMM_LISA_MAP registers program whether memory is mapped
on particular EMIF or not. Irrespective of these registers
EMIF is getting configured. Correcting the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
c7f1cf5f29 OMAP: Tweak omap-common/Makefile since reset.S -> reset.c
Git commit d417d1db5f replaced the
omap-common file reset.S with reset.c, but the Makefile was not
adjusted for that.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
f281f299df omap4: Add comments on some "#endif"s for readability.
No functional changes, simply for readability.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Robert P. J. Day
e3fe62574d omap3: Add a few comments to "#endif"s for readability.
No functional changes, just more comments for readability when a
preprocessor check spans more than a few lines, and for consistency.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2012-12-10 08:55:25 -07:00
Peter Barada
8c4445d266 Pass sdrc timing values through board_sdrc_timings structure
Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings.  This saves about
90 bytes of space in SPL.

Signed-off-by: Peter Barada <peter.barada@logicpd.com>
2012-12-10 08:54:02 -07:00
Mansoor Ahamed
04c3757829 am33xx: add ELM support
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.

Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:02 -07:00
Ilya Yanok
8eb16b7f73 am33xx: NAND support
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Ilya Yanok
1befaffbfb OMAP: include sys_proto.h from boot-common
Include asm/arch/sys_proto.h for gpmc_init prototype.
Without this we get a warning while building for AM335x.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-12-10 08:54:01 -07:00
Andreas Bießmann
4af9e675fa omap3/mem.c: remove unused defines
These GPMC_CS defines are a leftover from prior gpmc_init(). Commit 187af954
removed the need for these definitions but missed to remove them.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
2012-12-10 08:54:01 -07:00
Minkyu Kang
2c601c7208 Merge branch 'master' of git://git.denx.de/u-boot into resolve
Conflicts:
	README
	board/samsung/universal_c210/universal.c
	drivers/misc/Makefile
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/seaboard.h
2012-12-10 14:13:27 +09:00
Richard Genoud
bcfc8976e5 at91sam9x5: enable USB support for 9x5ek board.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-12-09 22:38:27 +01:00
Daniel Schwierzeck
ea40a05422 MIPS: constify address pointer in test_bit()
Fix several warnings when enabling UBIFS on MIPS:

In file included from ubifs.h:2137:0,
                 from ubifs.c:26:
misc.h: In function 'ubifs_zn_dirty':
misc.h:38:2: warning: passing argument 2 of 'test_bit' discards 'const' qualifier from pointer target type [enabled by default]
../include/asm/bitops.h:569:23: note: expected 'volatile void *' but argument is of type 'const long unsigned int *'

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-08 21:48:19 +01:00
Zhi-zhou Zhang
0d69d918ab MIPS: fix a latent bug on initialize $gp
If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned.
then the following ld insntrustion generates a Adel exception.
So here make _gp be always aligned in 8 bytes.

Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-12-08 21:33:07 +01:00
Stefano Babic
05a860c228 Merge branch 'master' of git://git.denx.de/u-boot into master
Conflicts:
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/woodburn_common.h
	board/woodburn/woodburn.c

These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.

Fix all conflicts and update woodburn to use Power Framework.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-12-08 12:02:45 +01:00
Otavio Salvador
393ff47ba3 mxs: SPL: Generalize memory initialization
Use a generic 'dram_vals[]' array that has the full initialization
sequence and rename the initialization method so it doesn't has a
frequency on its name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-12-07 14:50:02 +01:00
Simon Glass
058d59b08d x86: Build vga video code only if CONFIG_VIDEO_VGA is defined
When running from coreboot we don't want this code, so make it
optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
a94e9d70e3 x86: Remove video_init() prototype from u-boot-x86.h
This function is not intended to be exported from the video drivers, so
remove the prototype. This fixes an error:

cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
c94663170b x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
2b9d2252aa x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
1350f1cce1 x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.

This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.

Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
7c71034d3c x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.

Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
b83058cd23 x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
488b8b242b x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Stefan Reinauer
300081aa68 x86: Emit port 80 post codes in show_boot_progress()
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Simon Glass
2712f08898 x86: fdt: Create basic .dtsi file for coreboot
This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
ba74a0ffcb x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly
We will use coreboot.dtsi as our fdt include file.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
b208c7f1d0 x86: Add support for CONFIG_OF_CONTROL
Allow a device tree to be provided through the standard mechanisms.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Stefan Reinauer
05b71646a9 x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loadinlg of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
91d82a29e7 x86: Add back cold- and warm-boot flags
These were removed, but actually are useful.

Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.

We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
112a575e49 x86: Override calculate_relocation_address to use the e820 map
Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.

Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:42 -08:00
Gabe Black
d65297b64d x86: Make calculate_relocation_address an overridable function
Different systems may have different mechanisms for picking a suitable place
to relocate U-Boot to.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
842d33874f x86: Make the upper bound on relocated symbols closed instead of open
This seems to be a bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
32f98735f9 x86: Reorder x86's post relocation memory layout
This changes the layout in decreasing addresses from:

1. Stack
2. Sections in the image
3. Heap

to

1. Sections in the image
2. Heap
3. Stack

This allows the stack to grow significantly more since it isn't constrained by
the other u-boot areas. More importantly, the generic memory wipe code assumes
that the stack is the lowest addressed area used by the main part of u-boot.
In the original layout, that means that u-boot tramples all over itself. In
the new layout, it works.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
8313315b9a x86: Initialise SPI if enabled
If we have SPI support, make sure that we init it.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vic Yang <victoryang@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
ac31a7b81c x86: Implement arch_phys_memset so that it can wipe memory above 4GB
Implement arch_phys_memset so that it can set memory at physical addresses
above 4GB using PAE paging. Because there are only 5 page tables in PAE mode,
1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The
tables must be 4K page aligned and are declared that way, and because U-Boot
starts as 4K aligned and the relocation code relocates it to a 4K aligned
address, the tables work as intended.

While paging is turned on, all 4GB are identity mapped except for one 2MB
page which is used as the window into high memory. This way, U-Boot will
continue to work as expected when running code that expects to access memory
freely, but the code can still get at high memory through its window.

The window is put at 2MB so that it's 2MB page aligned, low in memory to be
out of the way of things U-Boot is likely to care about, and above the lowest
1MB where lots of random things live.

Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:41 -08:00
Gabe Black
ec516c4899 x86: Increase the size of the phys_size_t and phys_addr_t types
These types should be 64 bits long to reflect the fact that physical
addresses and the size of physical areas of memory are more than 32 bits
long.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Duncan Laurie
0c3929092d x86: Fix off-by-one error in do_elf_reloc_fixups()
The use of post-increment with a do-while loop results in
the loop going one step too far when handling relocation fixups.

In about 1/100 cases this would cause it to hang.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Duncan Laurie
984d8b09fb x86: Ignore memory >4GB when parsing Coreboot tables
U-boot is unable to actually use that memory and it can
cause problems with relocation if it tries to.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Simon Glass
1484311286 x86: Fix indirect jmp warning in zimage.c
This fixes the following warning:

zimage.c:312: Warning: indirect jmp without `*'

Also fixed these warnings to keep checkpatch quiet:

warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Stefan Reinauer
17de114f9f x86: Clean up MTRR 7 right before jumping to the kernel
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Graeme Russ
98568f0fa9 x86: Import MSR/MTRR code from Linux
Imported from Linux 3.1 with a few modifications to suit U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Stefan Reinauer
61e0ea900a x86: Provide a function to clean up just before booting a zimage
This function can be used by boards which want to do some clean-up
before booting a zImage.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Stefan Reinauer
095593c030 x86: Add basic cache operations
Add functions to enable/disable the data cache.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Gabe Black
9a7da182fa x86: Fill in the dram info using the e820 map on coreboot/x86
This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Vadim Bendebury
3cdc18a8de x86: Add a CBMEM timestamp generated right before the kernel startup.
To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Vadim Bendebury
6dbe0cce3f x86: Enable coreboot timestamp facility support in u-boot.
This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.

Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.

The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.

Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Vadim Bendebury
2f899e03a9 x86: Add function to read time stamp counter
Put this function in the u-boot-x86.h header file. We could instead create
timer.h perhaps.

We support setting a base time, and reading the time relative to this base.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Bill Richardson
55ae10f8db x86: gpio: Add GPIO driver for Intel ICH6 and later.
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Stefan Roese
083f2e08d2 mpc5200: Add SPL support
This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:51 +01:00
Stefan Roese
ea8256f072 SPL: Port SPL framework to powerpc
This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.

timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:30:22 +01:00
Stefan Roese
966b11c749 powerpc: Extract EPAPR_MAGIC constants into processor.h
By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05 17:27:02 +01:00
Marek Vasut
a918a53c36 mxs: Staticize SPL functions
The MXS SPL didn't mark local functions "static". Fix it. This also makes the
SPL smaller by roughly 300 bytes.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:29:11 +01:00
Marek Vasut
1230e7bc2d mxs: Properly setup VDDD in power supply setup code
The memory setup code adjusted the VDDD voltage. Remove this adjustment
and configure the VDDD voltage correctly in the power supply setup code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:27:21 +01:00
Marek Vasut
77cb33bd25 mxs: Implement common function to setup VDDx
Implement common function to setup the VDDIO, VDDD and VDDA voltage.
Right now, there are two almost identical functions to setup VDDIO
and VDDD, which is prone to breakage. Pull out the differences into
constant structure and pass them as an argument to the common function.

Moreover, the function has almost identical loops for setting higher
and lower VDDx voltage. Merge these two loops.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-04 09:26:54 +01:00
Marek Vasut
893aabbead mx28: Rename regs-power.h to regs-power-mx28.h
The i.MX23 has different register layout and bit placement in the
power supply. Thus, in order to be able to add support for MX23,
rename the MX28's regs-power.h to regs-power-mx28.h . Moreover,
add ifdef around inclusion of regs-*-mx28.h in imx-regs.h so the
MX23 boards will include proper set of registers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-12-04 09:01:04 +01:00
Marek Vasut
3642b1c147 mx28: Remove SET, CLR, TOG ops from PLLxCTRL1 registers
These registers don't have _SET, _CLR and _TOG at the respective offsets
available, these registers has to be toggled via R-M-W if needed. Thus do
not export these offsets anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-12-04 08:52:05 +01:00
Tom Rini
ce12a8c1a9 Merge branch 'master' of git://git.denx.de/u-boot-x86 2012-12-03 06:47:05 -07:00
Stefan Reinauer
339c511106 x86: Don't spam POST80 codes with slow IO functions
This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.

It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Stefan Reinauer
5b1be1bd01 x86: Fix typo in pcat_timer.c
Fix a small comment typo.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Gabe Black
687c108b10 x86: Include types.h explicitly in the i386 version of io.h
The i386 version of io.h depends on the phys_addr_t type which is defined in
types.h. It wasn't including that explicitly, and was working presumably
because the other files including it had already included types.h themselves
directly or indirectly. This change fixes that.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Gabe Black
452b80ef8c x86: Add a dummy implementation for timer_get_us
The microsecond timer is not currently implemented, but add a dummy
implementation for now.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Gabe Black
f30fc4de41 x86: Add a default implementation for cleanup_before_linux()
This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:04 -08:00
Gabe Black
028a56289a x86: Add an fdt pointer to the global data structure
This change adds a pointer to the global data structure in x86 to point to
the device tree. This mirrors an identical pointer in ARM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:04 -08:00
Gabe Black
5b5ece9ef4 x86: Allow compiling out realmode/bios code
We don't want this for coreboot, so provide a way of compiling it out.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:04 -08:00
Simon Glass
402ed0048a x86: coreboot: Decode additional coreboot sysinfo tags
Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Stefan Reinauer
93c1735f41 x86: coreboot: Drop sysinfo.c
sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Yoshihiro Shimoda
867da0d4fe sh: fix trigger_address_error()
The function should set BL bit, but it should not clear other flags.
So, the patch uses set_bl_bit() instead of a local asm code.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-11-30 15:06:04 +09:00
Tom Rini
e57d9d15ee Merge branch 'master' of git://www.denx.de/git/u-boot-x86 2012-11-28 13:44:40 -07:00
Gabe Black
82e73f0e3d x86: coreboot: Implement recursively scanning PCI busses
A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:05 -08:00
Gabe Black
452f50f7cf x86: coreboot: Tell u-boot about PCI bus 0 when initializing
U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2012-11-28 11:40:04 -08:00
Stefan Reinauer
badcb343d7 x86: coreboot: Move non-board specific files to coreboot arch directory
coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:04 -08:00
Gabe Black
c953fbee54 x86: Add some missing includes
I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.

Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:04 -08:00
Gabe Black
b16f521a5e x86: Allow excluding reset vector code from u-boot
When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Simon Glass
8a487a4417 x86: Add initial memory barrier macros
These are available on other architectures, so add them on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
8abebe3ead x86: Add ilog2 to bitops
ilog2 is required by AHCI driver

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
c73c6de60c x86: Remove duplicate PCI init
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
8d61625d6a x86: Put global data on the stack
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Graeme Russ
e4fb611649 x86: Forward declare gd_t
So it can be used as a type in struct global_data and remove an ugly typecast

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-11-28 11:40:03 -08:00
Tom Rini
a86fcff695 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2012-11-28 08:30:21 -07:00
Tom Rini
d41b3cc16f Merge branch 'master' of git://git.denx.de/u-boot-mips 2012-11-27 20:34:51 -07:00
York Sun
afbfdf5450 powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE
Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:08 -06:00
Timur Tabi
b25f6de7c0 powerpc/85xx: update the work-around for P4080 erratum SERDES-9
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Yuanquan Chen
c0a4e6b889 powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Zang Roy-R61911
9760b274df powerpc/corenet_ds: move SATA config to board configuration
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :

 #ifdef CONFIG_FSL_SATA_V2
 ...
 #endif

To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Timur Tabi
d607b9684b powerpc/85xx: implement check for erratum A-004580 work-around
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
Kim Phillips
345d6efdc7 powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list
by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]:		264

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:07 -06:00
York Sun
2a5fcb835f powerpc/mpc85xx: Temporary fix for spin table backward compatibility
Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
0118033b67 powerpc/85xx: implement check for erratum A-004849 work-around
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
1956e431f8 powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:05 -06:00
Andy Fleming
e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
Jaehoon Chung
d0ebbb8dfa EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Support DesignWare MMC Controller for Samsung Specific.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 17:26:47 -06:00
Tom Rini
dfe161032d Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2012-11-26 14:53:33 -07:00
Scott Wood
c97cd1ba48 spl/85xx: new SPL support
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:25 -06:00
Scott Wood
4b919725b6 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
a179eb0a4b powerpc/mpc85xx: consistently use COBJS-y
A subsequent patch will conditionalize some of the files that are
currently unconditional.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
b9735cbaeb spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
59629c2897 spl/mpc85xx: move udelay to cpu code
It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale.  Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:23 -06:00
Scott Wood
8bc50f0b6d powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
7f0a22ff25 powerpc/mpc85xx: fix TLB alignment
In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.

Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
6ec63f411e powerpc: change .fixup test to a GCC version test
This was introduced by commit 2446151974, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
--
v2: test gcc version instead of testing nothing
2012-11-26 15:41:22 -06:00
Scott Wood
9a511bd6a3 powerpc/mpc85xx: add comma before "already enabled"
Now outputs like this:

L2:    512 KB already enabled, moving to 0xf8f80000

rather than this:

L2:    512 KB already enabledmoving to 0xf8f80000

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
2012-11-26 15:41:20 -06:00
Scott Wood
f545d300b0 powerpc/mpc85xx: move debug tlb entry after TLB is in known state
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
2012-11-26 15:41:20 -06:00
Zhi-zhou Zhang
8ab36d2e54 MIPS: do not initialize timestamp variable before relocate_code
Because timestamp is declared as `static', we needn't initialize
it by writing it a zero. If we do it before relocate_code, we
will write into a flash address(0xffffffffbfc0xxxx).

Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-11-25 21:50:43 +01:00
Albert ARIBAUD
b8a7c46796 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2012-11-25 13:01:58 +01:00
Marek Vasut
1d4fd0dc3b mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSET
The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is
not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET.
Correct the name in the header file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-24 16:21:37 +01:00
Marek Vasut
90a21030e3 mx28: Fix typo in POWER_MINPWR_VBG_OFF
The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called
POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the
header file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-24 16:21:10 +01:00
Ilya Yanok
673a524b6a musb-new: omap2plus backend driver
Backend driver for MUSB OTG controllers found on TI OMAP2/3/4
(tested only on OMAP3 Beagle).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:08 +01:00
Ilya Yanok
08fc71711a OMAP3: am35x: add musb functions
AM35XX specific functions for integrated USB PHY/MUSB IP.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
272165f6a9 OMAP3: am35x_def.h: add USB defines
Add defines for MUSB IP block on AM35X SoCs.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
833a53c627 musb-new: am35x backend driver
Backend driver for MUSB OTG controllers found on TI AM35x.

It seems that on AM35X interrupt status registers can be updated
_before_ core registers. As we don't use true interrupts in U-Boot
and poll interrupt status registers instead this can result in
interrupt handler being called with non-updated core registers.
This confuses the code and result in hanged transfers.
Add a small delay in am35x_interrupt as a workaround.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
7df5cf35de am33xx: init OTG hardware and new musb gadget driver
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:07 +01:00
Ilya Yanok
37931f02c2 musb-new: dsps backend driver
Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:06 +01:00
Ilya Yanok
c60795f41d usb: use linux/usb/ch9.h instead of usbdescriptors.h
Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.

As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.

Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.

This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-11-20 00:16:06 +01:00
Tom Rini
178d0cc1a4 Merge branch 'master' of git://git.denx.de/u-boot-video 2012-11-19 09:28:04 -07:00
Tom Rini
bb367b95f9 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2012-11-19 09:27:18 -07:00
Simon Glass
0dde7f5379 arm: Add control over cachability of memory regions
Add support for adjusting the L1 cache behavior by updating the MMU
configuration. The mmu_set_region_dcache_behaviour() function allows
drivers to make these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:38 -07:00
Wei Ni
87540de3af tegra: Add SOC support for display/lcd
Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.

Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Mayuresh Kulkarni:
- changes to remove bitfields and clean up for submission

Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass:
- simplify code, move clock control into here, clean-up
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:37 -07:00
Simon Glass
e1ae0d1f71 tegra: Add support for PWM
The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:36 -07:00
Simon Glass
eefe3e598e tegra: fdt: Add LCD definitions for Tegra
Add LCD definitions and also a proposed binding for LCD displays.

The PWM is as per what will likely be committed to linux-next soon.

The displaymode binding comes from a proposal here:

http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html

The panel binding is new, and fills a need to specify the panel
timings and other tegra-specific information. Should a binding appear
that allows the pwm to handle this automatically, we can revisit
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:36 -07:00
Simon Glass
beca1fdeff tegra: fdt: Add pwm binding and node
This binding will apparently soon be in linux-next. Bring it in now
since we need to do something, and may as well try to target what
Linux will have.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Simon Glass
b344496110 tegra: Add display support to funcmux
Add support for a default pin mapping for display1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Simon Glass
95be58c988 tegra: Use const for pinmux_config_pingroup/table()
These two functions don't actually modify their arguments so add a const
keyword.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-11-19 08:15:35 -07:00
Benoît Thébaudeau
39e8576164 mx5: Mark lowlevel_init board-specific code
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-11-19 08:56:27 +01:00
Fabio Estevam
cc446726de mx6: clock: Only show CSPI clock if CSPI is enabled
If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.

Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
2012-11-19 08:49:00 +01:00
Fabio Estevam
081237c1f7 mx5: Print CSPI clock in 'clock' command
Print CSPI clock in 'clock' command.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2012-11-19 08:49:00 +01:00
Fabio Estevam
d84f56f48f mx5: Align SPI CS naming with i.MX53 reference manual
Align SPI chip select naming with i.MX53 reference manual.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-11-19 08:48:59 +01:00
Benoît Thébaudeau
71a5c55bfa ehci-mxc: Add support for i.MX35
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-16 09:16:45 +01:00
Benoît Thébaudeau
34d33b671a ehci-mxc: Define host offsets
Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-16 09:16:45 +01:00
Benoît Thébaudeau
8eeb19be75 mx31: Move EHCI definitions to ehci-fsl.h
The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
ehci-fsl.h so that all MXC SoCs can use them.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-16 09:16:43 +01:00
Rajeshwari Shinde
1bf43b829e SPI: Add SPI Driver for EXYNOS.
This patch adds SPI driver for EXYNOS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: jy0922.shim@samsung.com
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:21 +09:00
Hatim RV
383b5cc58c EXYNOS5: Add base address for SPI
Add base address definition for SPI device on Exynos.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Hatim RV
b56b304252 EXYNOS: Add clock for SPI
Add api to calculate and set the clock for SPI channels

Signed-off-by: James Miller <jamesmiller@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
fbb5743308 EXYNOS5: Add pinmux support for SPI
This patch adds pinmux support for SPI channels

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
2e206caaa6 EXYNOS: Add clock for I2S
This patch adds clock support for I2S

Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
87fa491aee EXYNOS: Add I2S base address
This patch adds base address for I2S

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
6b0884d73a EXYNOS: Add pinmux for I2S
This patch adds pinmux support for I2S1

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
75ddfb4ff4 EXYNOS: Add parameters required by I2S
This patch adds the audio parameters required by the I2S to play the
predefined audio data.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Rajeshwari Shinde
02cfce31a7 EXYNOS: Add I2S registers
This patch add I2S registers

Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:20 +09:00
Ashok Kumar Reddy
4debcc2c22 ARM: arm1176: Define arch_cpu_init() for s3c64xx
arch_cpu_init() is removed from cpu level to SOC level for arm1176
in commit 4ea6d6b,the same is done for s3c64xx

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:19 +09:00
Marek Vasut
2b5fdd07c5 dm: wdt: Move s5p watchdog timer to drivers/watchdog/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:19 +09:00
Minkyu Kang
bb6527bc73 EXYNOS: Clock: Add common function for pll rate calculation
Moved the common code to calculate pll clock rate to new function
exynos_get_pll_clk().

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
2012-11-15 21:08:19 +09:00
Minkyu Kang
6fcc059f81 ARCH: EXYNOS: add support to match product id
Based upon single SoC there can be multiple variants.
This patch add support to match the complete product ID.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
2012-11-15 21:08:19 +09:00
Piotr Wilczek
a3eab2ac41 arm:exynos4:pinmux: Modify the gpio function for mmc
This patch add pinmux settings for Exynos4 for mmc0 and mmc2

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:18 +09:00
Łukasz Majewski
822593f028 gpio:fix: Proper handling of GPIO subsystem parts at Samsung devices
Now proper GPIO parts numbering is handled at Samsung devices.
This fix is necessary for code using GPIO located at other banks
than first.

Test HW:
- Exynos4210 - Trats
- S5PC110 - goni

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15 21:08:18 +09:00
Vikram Narayanan
5d71bd210f mx51evk: Fix build error when CONFIG_VIDEO is disabled
The inclusion of LCD patch into mx51evk breaks the build when
CONFIG_VIDEO is disabled. Fix this by splitting the video related
stuff to a new file.

Also rename the function lcd_iomux to setup_iomux_lcd to make the
namings aligned with the other iomux functions.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-14 14:05:35 +01:00
Łukasz Majewski
2ffb4beb50 pmic: Introduce power_init_board() method at ./lib/board.c file
It is necessary to introduce a new system wide function- power_init_board()

It turns out, that power initialization must be done as early as possible.
In the case of PMIC framework redesign, which aims to support multiple
instances of PMIC devices the initialization shall be performed just
after malloc configuration.

The power_init_board function is a weak function with default implementation.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-11-14 11:21:09 +01:00
Thomas Chou
db71964235 nios2: remove asm/status_led.h
The file has a wrong inline keyword of __led_toggle(), which causes
compilation error. And its content is defined in common status_led.h.
So define CONFIG_BOARD_SPECIFIC_LED in board config files and remove
this header file.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2012-11-10 19:45:58 +08:00
Benoît Thébaudeau
ccfa398547 arm1136: Fix enable_caches()
enable_caches() did not enable icache if CONFIG_SYS_ICACHE_OFF was not defined
but CONFIG_SYS_DCACHE_OFF was.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2012-11-10 12:28:22 +01:00
Troy Kisky
34275d70fe arch-mx6: add mx6dl_pins.h
Only the values used in the sabrelite board are
added currently. Add more as other boards use them.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-11-10 08:15:40 +01:00
Troy Kisky
eb0344d974 imx-common: cpu: add imx_ddr_size
Read memory setup registers to determine size
of available ram. This routine works for mx53/mx6x

I need this because when mx6solo called get_ram_size
with a too large maximum size, the system hanged.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-11-10 08:15:40 +01:00
Troy Kisky
20332a066a mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
Previously, the same value was returned for both mx6dl and mx6solo.
Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev
stored at 0x280 instead of 0x260.
I don't have a sololite to verify.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-11-10 08:15:40 +01:00
Stefano Babic
3e4d27b06d Merge git://git.denx.de/u-boot 2012-11-10 08:05:54 +01:00
Michal Simek
b3e5cd17f6 microblaze: Fix compilation failure because of missing libdts
Microblaze platform can use CONFIG_OF_EMBED option
but also it is necessary to support boards
which don't want to use this option.
U-Boot doesn't compile dts/libdts.o for #undef CONFIG_OF_EMBED
case that's why it should be guarded by ifdef.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-11-08 10:33:19 +01:00
Michal Simek
f8c1ed092c microblaze: Remove asm/bitops.h from asm/posix_types.h
The patch
"include/linux/byteorder: import latest endian definitions from linux"
(sha1: eef1cf2d5c)

Introduced a lot of compilation failures with unknow types.
include/linux/byteorder/big_endian.h:45:1: error: unknown type name '__le64'
include/linux/byteorder/big_endian.h: In function '__cpu_to_le64p':
include/linux/byteorder/big_endian.h:47:18: error: '__le64' undeclared (first use in this function)
include/linux/byteorder/big_endian.h:47:18: note: each undeclared identifier is reported only once for each function it appears in
include/linux/byteorder/big_endian.h:47:25: error: expected ';' before '__swab64p'
include/linux/byteorder/big_endian.h: At top level:
include/linux/byteorder/big_endian.h:49:1: error: unknown type name '__le64'
include/linux/byteorder/big_endian.h:53:1: error: unknown type name '__le32'
include/linux/byteorder/big_endian.h: In function '__cpu_to_le32p':
include/linux/byteorder/big_endian.h:55:18: error: '__le32' undeclared (first use in this function)
include/linux/byteorder/big_endian.h:55:25: error: expected ';' before '__swab32p'
include/linux/byteorder/big_endian.h: At top level:
include/linux/byteorder/big_endian.h:57:1: error: unknown type name '__le32'
include/linux/byteorder/big_endian.h:61:1: error: unknown type name '__le16'
...

Removing asm/bitops.h solved this problem.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-11-07 17:11:14 +01:00
Michal Simek
5811830fae microblaze: Flush caches before enabling them
Flushing caches is necessary because of soft reset
which doesn't clear caches.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-11-07 17:11:14 +01:00
Michal Simek
ea0122816c microblaze: Fix byteorder for microblaze
Just remove ancient code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-11-07 17:11:14 +01:00
Michal Simek
548ce4bf76 microblaze: Fix compilation warning in ext2_find_next_zero_bit
ext2_find_next_zero_bit must be also static if __swab32 is also static.

Warning:
include/asm/bitops.h:369:22: warning: '__fswab32' is static but
used in inline function 'ext2_find_next_zero_bit'
which is not static [enabled by default]

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
2012-11-07 17:11:14 +01:00
Tom Rini
6acc7c3cbc Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-11-05 07:42:00 -07:00
Kim Phillips
a2873bde4c powerpc/mpc83xx: sparse fixes
fdt.c:91:78: warning: Using plain integer as NULL pointer
fdt.c:103:78: warning: Using plain integer as NULL pointer
speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static?
speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static?
mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:37 -07:00
Kim Phillips
e56143e54f powerpc/mpc85xx: sparse fixes
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
2ed2e9121f arch/powerpc/cpu/mpc8xxx/: sparse fixes
ctrl_regs.c:31:5: warning: symbol 'fsl_ddr_get_version' was not declared. Should it be static?
cpu.c:135:14: warning: non-ANSI function declaration of function 'cpu_mask'
cpu.c:154:18: warning: non-ANSI function declaration of function 'cpu_numcores'
cpu.c:37:17: warning: symbol 'cpu_type_list' was not declared. Should it be static?
cpu.c:117:17: warning: symbol 'cpu_type_unknown' was not declared. Should it be static?
fsl_lbc.c:14:6: warning: symbol '__lbc_sdram_init' was not declared. Should it be static?

and:

lc_common_dimm_params.c:15:1: warning: symbol 'compute_cas_latency_ddr3' was not declared. Should it be static?

making it static produces the following compiler warning:

lc_common_dimm_params.c:15:1: warning: 'compute_cas_latency_ddr3' defined but not used [-Wunused-function]

so we protect it with the preprocessor.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
20051f2ab2 arch/powerpc/lib/board.c, *traps.c: sparse fixes
traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static?
traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static?
board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static?
board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static?
board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static?
board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static?
board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static?
board.c:405:53: warning: Using plain integer as NULL pointer

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
fe44f452db arch/powerpc/lib/extable.c: sparse fix
extable.c:66:9: warning: symbol 'ex_tab_message' was not declared. Should it be static?

making it static can produce a new build warning on some boards:

extable.c:66:12: warning: 'ex_tab_message' defined but not used [-Wunused-variable]

but ex_tab_message doesn't do much even when used, so just remove it.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
cdfdb8d7f3 arch/powerpc/include/asm/io.h: fix warning: preprocessor token __iomem redefined
a fixup __iomem definition in arch code appears to be placed there as a cover
up from a code import from linux when u-boot didn't yet have a compiler.h,
introduced by commit 812711ce6b "Implement
__raw_{read,write}[bwl] on all architectures".

git show 812711ce6b3a386125dcf0d6a59588e461abbb87:include/linux/compiler.h
fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce6b3a386125dcf0d6a59588e461abbb87'.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:35 -07:00
Kim Phillips
eef1cf2d5c include/linux/byteorder: import latest endian definitions from linux
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
2012-11-04 11:00:34 -07:00
Vikram Narayanan
46d626d392 socfpga/spl: Remove malloc.h
Remove unused header

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
2012-11-04 16:23:23 +01:00
Vikram Narayanan
7ae534cef9 socfpga/spl: Remove timer_init from spl_board_init
Timer is initialized already in board_init_r function in
(common/spl/spl.c) No need to initialize it again

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
2012-11-04 16:19:58 +01:00
Albert ARIBAUD
a42c87f9d8 Merge remote-tracking branch 'u-boot-ti/master' 2012-11-03 10:05:22 +01:00
Tom Rini
57f588be60 omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFF
When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings
currently.  Re-order functions so that we don't have that anymore.

Signed-off-by: Tom Rini <trini@ti.com>
2012-10-30 22:23:28 -07:00
Pali Rohár
89e6f13849 arm bootm: Allow to pass board specified atags
Board can implement function setup_board_tags which is used for adding atags

Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
2012-10-30 15:28:05 -07:00
Allen Martin
d598e0fe73 arm720t: add back common.h include
Add back common.h header that was removed in previous patch so that
CONFIG_TEGRA can be evaluated correctly.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 14:04:26 -07:00
Allen Martin
ee2e185f62 tegra20: initialize variable to avoid compiler warning
Initialize this variable to avoid a compiler warning about possible
use of uninitialized variable with gcc 4.4.6.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 09:07:06 -07:00
Allen Martin
b2f9893826 tegra: move to common SPL framework
Change tegra SPL to use common SPL framework.  Any tegra specific
initialization is now done in spl_board_init() instead of
board_init_f()/board_init_r().  Only one SPL boot target is supported
on tegra, which is boot to RAM image.  jump_to_image_no_args() must be
overridden on tegra so the host CPU can be initialized.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 09:07:06 -07:00
Stephen Warren
2b7818d49f ARM: enhance u-boot.lds to detect over-sized SPL
Add an ASSERT() to u-boot.lds to detect an SPL that doesn't fit within
SPL_TEXT_BASE..SPL_MAX_SIZE.

Different .lds files implement this check in two possible ways:
1) An ASSERT() like this
2) Defining a MEMORY region of size SPL_MAX_SIZE, and re-directing all
   linker output into that region. Since u-boot.lds is used for both
   SPL and main U-Boot, this would entail only sometimes defining a
   MEMORY region, and only sometimes performing that redirection, and
   hence option (1) was deemed much simpler, and hence implemented.

Note that this causes build failures at least for NVIDIA Tegra Seaboard
and Ventana. However, these are legitimate; the SPL doesn't fit within
the required space, and this does cause runtime issues.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-29 09:07:05 -07:00
Wolfgang Denk
1b0757eced PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)
These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>
2012-10-28 20:17:25 +01:00
Albert ARIBAUD
f04821a8ca Merge remote-tracking branch 'u-boot-imx/master' 2012-10-27 11:43:17 +02:00
Stephen Warren
b68d6712c3 ARM: fix u-boot.lds for -ffunction-sections/-fdata-sections
When -ffunction-sections or -fdata-section are used, symbols are placed
into sections such as .data.eserial1_device and .bss.serial_current.
Update the linker script to explicitly include these. Without this
change (at least with my gcc-4.5.3 built using crosstool-ng), I see that
the sections do end up being included, but __bss_end__ gets set to the
same value as __bss_start.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2012-10-26 23:46:21 +02:00
Yann Vernier
bff679ddfb arm: ks8695: use defined constants for UART
CONFIG_BAUDRATE and KS8695_UART_LINEC_WLEN8 used for UART registers
2012-10-26 23:32:11 +02:00
Marek Vasut
82138f4fcd arm720: Remove CONFIG_ARM7_REVD
This is a dead code, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26 22:39:03 +02:00
Marek Vasut
a63dd62bb2 arm720: Further clean up the arm720t directory
Clean up away old macros and such, so the file doesn't start piling
up cruft.

Signed-off-by: Marek Vasut <marex@denx.de>

clean
2012-10-26 22:38:56 +02:00
Marek Vasut
f2e0801565 stdio: Remove the CLPS7111 serial driver
This driver is no longer used, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26 22:38:40 +02:00
Marek Vasut
b411eb30f5 arm: Remove support for NETARM
This stuff has been rotting in the tree for a while now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26 22:38:00 +02:00
Marek Vasut
afad40299e arm: Remove support for s3c4510
This stuff has been rotting in the tree for a year now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26 22:37:12 +02:00
Marek Vasut
6f62f42071 arm: Remove support for lpc2292
This stuff has been rotting in the tree for a year now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26 22:35:20 +02:00
Fabio Estevam
e100a3d52e mx25: Place common functions into sys_proto.h
imx-regs.h is meant to contain SoC register definitions.

Common SoC funtions should go to sys_proto.h instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-26 16:28:07 +02:00
Stefano Babic
d81b27a245 MX35: add support for woodburn board
The woodburn board is based on the MX35 SOC.
Support for both external (NOR) and internal
(SD Card) boot mode are added. It uses the
generic SPL framework to implement the internal boot
mode.

The following peripherals are supported:
- Ethernet (FEC)
- SD Card
- NAND (512 MB)
- NOR Flash

In the internal boot mode, a simple imximage header
is generated to set the address in internal RAM
where the SOC must copy the SPL code. The initial setup
is then demanded to the SPL itself.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:27:59 +02:00
Stefano Babic
a3cbc3969d ARM: Add SPL target to arm1136
The patch adds SPL for the arm1136 architecture and
inserts SPL (the produced binary) to clobber target
in the main Makefile.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:27:59 +02:00
Stefano Babic
d41924a2c1 MX35: Add soc_boot_mode and soc_boot_device to MX35
The functions are required to use the generic
SPL Framework.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:27:58 +02:00
Stefano Babic
e650030347 MX35: add LOW_LEVEL_SRAM_STACK to use SPL_FRAMEWORK
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:27:58 +02:00
Stefano Babic
b736e4b929 ARM: Fix start.S when used with SPL in arm1136
This patch modifies start.S for the arm1136 to make it
conform to start.S  in armv7 architecture, to make it
usable if the SPL framework is used.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:27:58 +02:00
Stefano Babic
01968b96a2 MX5: fix warning in clock.c
Patch fix warnings compiling with ELDK-4.2:

clock.c: In function 'get_standard_pll_sel_clk':
clock.c:341: warning: 'freq' may be used uninitialized in this function

Reported-by : Marek Vasut <marex@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:11:32 +02:00
Albert ARIBAUD
4c25761337 Merge remote-tracking branch 'u-boot-atmel/master' 2012-10-26 07:54:25 +02:00
Albert ARIBAUD
c68436fa42 Merge remote-tracking branch 'u-boot-ti/master' 2012-10-26 07:00:28 +02:00
Andrew Bradford
25164218b7 am33xx: Enable UART{1,2,3,4,5} clocks
If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232
cape or the am335x_evm daughterboard, enable the required clocks for
the UART in use.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
2012-10-25 14:44:24 -07:00
Peter Korsgaard
c7d35bef25 am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers
So other parts can be added.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:31:38 -07:00
Peter Korsgaard
c00f69dbcd am33xx: support board specific ddr settings
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:31:38 -07:00
Peter Korsgaard
7f26a5a26f am33xx: move generic parts of pinmux handling out from board/ti/am335x
So they are available for other boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:31:37 -07:00
Peter Korsgaard
75a23880a5 am33xx/board: use cpu_mmc_init() for default mmc initialization
So platforms can override it with board_mmc_init() if needed.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:31:37 -07:00
Peter Korsgaard
e363426e99 am33xx: move ti i2c baseboard header handling to board/ti/am335x/
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make re-apply with rtc32k_enable() applied]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:31:36 -07:00
Peter Korsgaard
c50cce2758 am33xx/board.c: make wdtimer/uart_base static
Only used here (and uart_base only for SPL).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25 11:30:50 -07:00
Tom Rini
69916bcf71 am33xx: Add SPI SPL as an option
Add the required config.mk logic for this SoC as well as the BOOT_DEVICE
define.  Finally, enable the options on the am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:30:50 -07:00
Stefano Babic
60c41d907e VIDEO: add macro to set LCD size for DSS driver
Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2012-10-25 11:30:49 -07:00
Vaibhav Hiremath
000820b583 am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume.  In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain.  Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.

So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25 11:30:22 -07:00
Alison Wang
45370e1836 ColdFire: Add MCF5441x CPU support
Add MCF5441x CPU support.

The MCF5441x devices are a family of highly-integrated 32-bit
microprocessors based on the Version 4m ColdFire microarchitecture,
comprising of the V4 integer core, memory management unit(MMU) and
enchanced multiply-accumulate unit(EMAC).

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-10-24 22:27:46 +08:00
Alison Wang
7adbd11e78 ColdFire: Fix unused variable in cpu_init.c
Fix the following build warnings in cpu_init.c:

cpu_init.c: In function 'cpu_init_f':
cpu_init.c:47:9: warning: unused variable 'pll'
cpu_init.c:46:10: warning: unused variable 'fbcs'
cpu_init.c:44:10: warning: unused variable 'scm1'

Signed-off-by: Alison Wang <b18965@freescale.com>
2012-10-24 22:27:46 +08:00
Gerlando Falauto
a88731a6c2 mpc83xx: add support for mpc8309
This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:26 -05:00
Gerlando Falauto
8afad91f15 cleanup: introduce CONFIG_MPC830x
Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Gerlando Falauto
4b5282de99 cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23 15:23:25 -05:00
Joel A Fernandes
391a741162 am33xx: Enable DDR3 for DDR3 version of beaglebone
DDR3 support is tested and working with beaglebone hardware. Include a check
for this board type and configure DDR3. The timings and other configuration
match EVM SK.

Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Acked-by: Jason Kridner <jdk@ti.com>
2012-10-23 08:33:17 -07:00
Tom Rini
c7656bab41 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2012-10-22 16:54:38 -07:00
Andy Fleming
23028d69e9 85xx: Protect timeout_save variable with ifdefs
The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 17:28:18 -05:00
Liu Gang
19e4a00965 powerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Haiying Wang
990e1a8ce1 poweprc/85xx: add QMan frequency info and fdt fixup.
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Haiying Wang
b0e8115741 mpc85xx/portals: Add qman and bman ip_cfg field into portal info
Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the
total portal number, buffer pool number etc, we can use this info to limit
those resources in kernel driver.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
York Sun
98ffa19053 powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:33 -05:00
York Sun
ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00
York Sun
3f0997b325 powerpc/mpc85xx: Remove R6 from spin table
R6 was in ePAPR draft version but was dropped in official spec.
Removing it to comply.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:31 -05:00
York Sun
82968a7ab5 powerpc/mpc8xxx: Fix DDR SPD failed message
Since empty DIMM slot is allowed on other than the first slot, remove the
error message if SPD is not found in this case.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:31 -05:00
York Sun
89b7809568 powerpc/mpc8xxx: Add auto select bank interleaving mode
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:30 -05:00
York Sun
a1d558a20f powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:29 -05:00
York Sun
eb53941206 powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:28 -05:00
York Sun
f31cfd1925 powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:27 -05:00
York Sun
123922b1e5 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
York Sun
57495e4e5e powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
	000 -> Termsel off
	001 -> 120 Ohm
	010 -> 180 Ohm
	011 -> 75 Ohm
	100 -> 110 Ohm
	101 -> 60 Ohm
	110 -> 70 Ohm
	111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
Roy Zang
111fd19e3b fm/mEMAC: add mEMAC frame work
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:25 -05:00
York Sun
d2404141f9 powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:24 -05:00
York Sun
9e75875849 powerpc/mpc85xx: Add T4240 SoC
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:23 -05:00
Andy Fleming
f311838ded powerpc/mpc85xx: Add T4 device definitions
The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:22 -05:00
York Sun
379c5145ef powerpc/corenet2: fix mismatch DDR sync bit from RCW
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:20 -05:00
York Sun
d1001e3f0c powerpc/corenet2: Add SerDes for corenet2
Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
	The Common Public Radio Interface (CPRI) is publicly available
	specification that standardizes the protocol interface between the
	radio equipment control (REC) and the radio equipment (RE) in wireless
	basestations. This allows interoperability of equipment from different
	vendors,and preserves the software investment made by wireless service
	providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:19 -05:00
York Sun
fd3cebd020 powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2
Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
92230d49da powerpc/e6500: Move QCSP registers for QMan v3
The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:18 -05:00
York Sun
f8f85b049c powerpc/mpc85xx: expand SERDES reference clock select bit
Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:17 -05:00
York Sun
9a653a9810 powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:16 -05:00
York Sun
2f1712b275 powerpc/mpc85xx: check number of cores
Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
f77329cfcf powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
6d2b9da19c powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
69c7826759 powerpc/mpc85xx: Introduce new macros to add and delete TLB entries
These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
Kumar Gala
800c73c410 powerpc/85xx: Add determining and report IFC frequency
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
York Sun
553ae6f8f2 powerpc/DPAA: Fix compiling error
FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined.
Remove the #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
Timur Tabi
4905443f1c powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
    Up to 2.4 GHz with 64-bit ISA support
    Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
    2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
        support Up to 1600MT/s
    Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
    Packet parsing, classification, and distribution (FMAN)
    Queue management for scheduling, packet sequencing and
    congestion management (QMAN)
    Hardware buffer management for buffer allocation and
    de-allocation (BMAN)
    Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
    20 lanes at up to 5 Gbps
    Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
    Two 10 Gbps Ethernet MACs
    Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
    Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
    Two serial ATA (SATA 2.0) controllers
    Two high-speed USB 2.0 controllers with integrated PHY
    Enhanced secure digital host controller (SD/MMC/eMMC)
    Enhanced serial peripheral interface (eSPI)
    Two I2C controllers
    Four UARTs
    Integrated flash controller supporting NAND and NOR flash
DMA
    Dual four channel
Support for hardware virtualization and partitioning enforcement
    Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
    Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
71cfcef649 powerpc/p5040ds: add per pci endpoint liodn offset list
Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
    pci0: 193 256 259 262 265 268 271 274 277
    pci1: 194 257 260 263 266 269 272 275 278
    pci2: 195 258 261 264 267 270 273 276 279

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Timur Tabi
fd946040f1 powerpc/85xx: define SRIO LIODN functions only if SRIO is defined
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:13 -05:00
Laurentiu Tudor
e389a377ee powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself.  Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Timur Tabi
0c7e65f3d6 powerpc/mpc85xx: fix Unicode characters in release.S
Commit 709389b6 unintentionally used the Unicode version of the
apostrophy.  Replace it with the normal ASCII version.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Liu Gang
d59c557049 powerpc/srio: Workaround for srio erratrm a004034
Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.

An SRIO port configured as a 4x port may see one of these scenarios:

1.	One or more lanes fails to achieve lane synchronization.
	Depending on which lanes fail, this may result in downtraining
	from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

2.	The link may fail to achieve lane alignment as a 4x, even
	though all 4 lanes achieve lane synchronization, and downtrain
	to a 1x. An SRIO port configured as a 1x port may fail to complete
	port initialization (PnESCSR[PU] never deasserts) because of
	scenario 1.

Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
ramneek mehresh
9c889ece32 powerpc/mpc8xxx: Fix USB device-tree fixup
Fix usb device-tree fixup:
	- wrong modification of dr_mode and phy_type when
	  "usb1" is not mentioned inside hwconfig string;
	   now allows hwconfig strings like:
		"usb2:dr_mode=host,phy_type=ulpi"
	- add warning message for using usb_dr_mode
	  and usb_phy_type env variables (if either is used)

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:12 -05:00
Ashok
bcf28c23f2 ARM : Remove unused CONFIG_DRIVER_SMC91111, CONFIG_DRIVER_LAN91C96
Remove unused CONFIG_DRIVER_SMC91111,CONFIG_DRIVER_LAN91C96,
if required implement smc_set_mac_addr() in board init.

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
2012-10-22 08:33:52 -07:00
Marek Vasut
8b493a5236 common: Discard the __u_boot_cmd section
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Marek Vasut
6c7c946cad common: Convert the U-Boot commands to LG-arrays
This patch converts the old method of creating a list of command
onto the new LG-arrays code. The old u_boot_cmd section is converted
to new u_boot_list_cmd subsection and LG-array macros used as needed.

Minor adjustments had to be made to the common code to work with the
LG-array macros, mostly the fixup_cmdtable() calls are now passed the
ll_entry_start and ll_entry_count instead of linker-generated symbols.

The command.c had to be adjusted as well so it would use the newly
introduced LG-array API instead of directly using linker-generated
symbols.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Marek Vasut
556751427b common: Add .u_boot_list into all linker files
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Zang Roy-R61911
4e0be34a85 P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional
P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:28 -05:00
Mark Marshall
320d53da60 powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.
We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:27 -05:00
Chris Packham
168e5bc409 mpc85xx: make gpio_direction_output respect value
Users of familiar with the Linux gpiolib API expect that value parameter
to gpio_direction_output reflects the initial state of the output pin.
gpio_direction_output was always driving the output low, now it drives
it high or low according to the value provided.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:03:16 -05:00
Tom Rini
99070db0dc Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	drivers/serial/serial_lh7a40x.c

Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 18:23:38 -07:00
Simon Glass
eeaec258b7 sandbox: Change global data baudrate to int
This doesn't need to be a long, so change it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:46 -07:00
Simon Glass
55f97c1bfb x86: Change global data baudrate to int
This doesn't need to be a long, so change it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:46 -07:00
Simon Glass
a25356d771 nds32: Change global data baudrate to int
This doesn't need to be a long, so change it.

Also adjust bi_baudrate to be unsigned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:46 -07:00
Simon Glass
8dc22b00ac mips: Change global data baudrate to int
This doesn't need to be a long, so change it.

Also adjust bi_baudrate to be unsigned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Simon Glass
5e84e5a7d4 blackfin: Change global data baudrate to int
This doesn't need to be a long, so change it.

Also adjust bi_baudrate to be unsigned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Simon Glass
e46e31a83a arm: Change global data baudrate to int
This does not need to be a long, so change it.

Also adjust bi_baudrate to be unsigned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Simon Glass
a8f1f1cd97 sparc: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Simon Glass
a7e5ee9ebb powerpc: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Simon Glass
7a68e330d0 openrisc: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:45 -07:00
Simon Glass
7fffe2fac8 nios2: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:44 -07:00
Simon Glass
74e8456bc1 microblaze: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:44 -07:00
Simon Glass
f5a5b3c5ee m68k: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:44 -07:00
Simon Glass
15dc95d48a avr32: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:44 -07:00
Simon Glass
ecd4551f14 sh: Change bi_baudrate and global data baudrate to int
These don't need to be longs, so change them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-19 15:25:44 -07:00
Simon Glass
39826f0997 arm: fdt: Relocate fdt along with other data
Rather than leave the fdt down next to the code/data, we really should
relocate it along with everything else. For CONFIG_OF_EMBED this happens
automatically, but for CONFIG_OF_SEPARATE it does not.

Add code to copy the fdt and point to the new copy after relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-19 21:38:27 +02:00
Marek Vasut
c59ac903f2 m68k: Fix unused variable in board.c
The following warning was produced, fix it:

board.c: In function 'board_init_r':
board.c:390:8: warning: unused variable 's' [-Wunused-variable]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
2012-10-19 23:47:41 +08:00
Marek Vasut
c1568ca545 m68k: Fix unused variable warning in speed.c
The following warning was produced, fix it:

speed.c: In function 'get_clocks':
speed.c:94:15: warning: variable 'bPci' set but not used [-Wunused-but-set-variable]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
2012-10-19 23:47:41 +08:00
Marek Vasut
2b05593da6 m68k: Fix unused variable warning
The fbcs variable was unused, producing the following warning:

cpu_init.c: In function 'cpu_init_f':
cpu_init.c:52:10: warning: unused variable 'fbcs' [-Wunused-variable]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
2012-10-19 23:47:41 +08:00
Marek Vasut
37d6cc3176 m68k: Fix wrong assembler instruction in start.S
The jmp _fault generated the following error message, thus change it
to bra _fault:

start.S: Assembler messages:
start.S:310: Error: Conversion of PC relative displacement to absolute

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
2012-10-19 23:47:41 +08:00
Philippe De Muyter
2ca7406c64 m68k: Fix relocation errors in start.S
When the environment sectors in the flash are big, one get those errors :

 mcf547x_8x/start.S:173: relocation truncated to fit: R_68K_PC16 against
  symbol `cpu_init_f' defined in .text section in libmcf547x_8x.a(cpu_init.o)
 mcf547x_8x/start.S:174: relocation truncated to fit: R_68K_PC16 against
  symbol `board_init_f' defined in .text section in libm68k.a(board.o)

Fix that.

Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
2012-10-19 23:47:41 +08:00
Marek Vasut
fb24ffc086 dm: Move s3c24xx USB driver to a proper place
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
2012-10-18 06:54:18 +02:00
Marek Vasut
d731282e7c dm: wdt: arm: Move tnetv107x into drivers/watchdog/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Oliver Brown <obrown@adventnetworks.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
2012-10-18 06:52:02 +02:00
Fabio Estevam
c4fe17f6d8 mx5: Add workaround for ARM erratum ID 468414
Add the software workaround for ARM erratum ID 468414.

According to mx53/mx51 errata document:

"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a
subsequent request

Description:

Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded
to a subsequent, unrelated memory request.
The conditions are as follows:
• Neon loads and stores must be in use
• Neon L1 caching must be disabled
• Trustzone must be configured and in use
• The secure memory address space and the non-secure memory address space both use the same
physical addresses, either as an alias or the same memory location or for separate memory
locations
The issue is reported by ARM, erratum ID 468414, Category 2"

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-17 18:25:12 +02:00
Fabio Estevam
782b028841 mx5: lowlevel_init.S: Fix PLL settings for mx53
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.

Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.

Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.

Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.

Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-17 18:09:34 +02:00
Fabio Estevam
758c344945 mx5: lowlevel_init.S: Split init_clock macro
init_clock is currently shared between mx51 and mx53 and it contains lots of
ifdef's which makes it really hard to follow the code.

Split the init_clock between mx51 and mx53 to allow easier readability.

No functional changes are made.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-17 18:09:34 +02:00
Tom Rini
d1ff690612 Merge branch 'master' of git://git.denx.de/u-boot-mips 2012-10-17 08:57:13 -07:00
Pavel Herrmann
4d1361d867 split AU1X00 specific code from cmd_ide.c
move special case of ide_swap_read() for AU1X00 SoC into SoC-specific directory.

Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
2012-10-17 07:59:09 -07:00
Pavel Herrmann
8d1165e11a split mpc8xx hooks from cmd_ide.c
move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created
ide_init_postreset() (invoked after calling ide_reset after ide_preinit),
some cleanup to make checkpatch happy, enable IDE init hooks in configs of
affected boards.
confusingly, these hooks are used by more than just mpc8xx-based boards, and
therefore are placed in arch/ppc/lib/

note: checkpatch still emits warnings about using volatile

Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
2012-10-17 07:59:08 -07:00
Marek Vasut
ec3fd68952 serial: Use default_serial_puts() in drivers
Replace the in-place ad-hoc implementation of serial_puts() within
the drivers with default_serial_puts() call. This cuts down on the
code duplication quite a bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
2012-10-17 07:55:50 -07:00
Stefan Roese
bfa5b71408 mpc82xx: Remove BMW board port
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: James F. Dougherty <jfd@broadcom.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-17 07:55:50 -07:00
Nobuhiro Iwamatsu
6abcf2d531 nds32: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
With almost all the architecture and board BOARD_LATE_INIT does not use.
CONFIG_BOARD_LATE_INIT is used instead.
This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Macpaul Lin <macpaul@andestech.com>
[trini: Fixup for context changes]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-17 07:55:50 -07:00
Wu, Josh
3a49cd7e1a ARM: at91sam9x5: enable MCI0 support for 9x5ek board.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-10-17 11:29:25 +02:00
Albert ARIBAUD
b9f4bc34ac Remove lh7a40x cpu and serial driver
Since commit 957731ed (ARM: remove broken "lpd7a40x" boards),
lh7a40x cpu and serial driver have become unused. Remove them.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-10-16 18:00:36 +02:00
Zhi-zhou Zhang
32afad783e MIPS: add board qemu-mips64 support
Both big-endian and little-endian are tested with below commands:
Rom version: (Default, Now we config it as rom version)
qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
Ram version:
qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic

Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-10-16 15:02:08 +02:00
Zhi-zhou Zhang
090854c826 MIPS: add support for 64 bit addressing
Prepare for upcoming mips64 support. This patch add mips64 address
support.

Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
[daniel.schwierzeck@gmail.com: prefer _MIPS_SZLONG in posix_types.h to fix some warnings]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-10-16 15:02:08 +02:00
Zhi-zhou Zhang
cb0a6a1ecc MIPS: don't use camel-case style
Replace camel-case style with upper-case style globally.

Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
2012-10-16 15:02:08 +02:00
Benoît Thébaudeau
5676f598e7 mx25: Clean up imx-regs.h
Clean up i.MX25 imx-regs.h:
 - Update mx31 imx-regs.h filename.
 - Test for __KERNEL_STRICT_NAMES just in case.
 - Define internal RAM size.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:12 +02:00
Eric Nelson
f95c960bcc i.MX6: add HDMI transmitter register declarations from kernel WIP.
Original source from Pengutronix HDMI driver work:

	http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commitdiff;h=72c31cd67ac880bd90785af86f8e46f8ea7b3bb0

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:11 +02:00
Eric Nelson
0fb1e57cb6 i.MX6: set drive strength for parallel RGB pads
Default drive strength is disabled and won't function.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:11 +02:00
Eric Nelson
5ae28d2db2 i.MX: iomux: input pad array can be const
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:11 +02:00
Fabio Estevam
dce67bd548 mx6qsabreauto: Pass the board revision to the kernel
The kernel from Freescale expects that the bootloader passes the board revision.

Read the board revision and pass it via get_board_rev().

Without passing the board revision the kernel does not operate properly as the
initialization of peripherals are different in revA versus revB boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-16 12:35:11 +02:00
Benoît Thébaudeau
6e3dc12754 mx35: Fix eSDHC clocks
Each eSDHC instance has a dedicated clock.

gd->sdhc_clk must also be set accordingly. This is good for the case only a
single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A
future patch will fix the multi-instance use case (initialization made directly
with fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2012-10-16 12:35:10 +02:00
Benoît Thébaudeau
151d63cb91 mx35: Clean up lowlevel_init
Clean up mx35 lowlevel_init:
 - Indent with tabs.
 - Fix comments.
 - Use defined values instead of literal constants.
 - Use defined macros instead of duplicating code.
 - Use macro parameters with default values instead of #define'd configs.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:10 +02:00
Tom Rini
bd23b22bad Merge branch 'agust@denx.de-next' of git://git.denx.de/u-boot-staging 2012-10-15 13:37:22 -07:00
Benoît Thébaudeau
85d993cef9 mx25: Clean up lowlevel_init
Clean up mx25 lowlevel_init:
 - Add comments.
 - Do not use write32 repeatedly with the same value in order not to increase
   code size.
 - Make register values configurable.
 - Use macro parameters with default values instead of literal constants.
 - Use defined macros instead of duplicating code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Matthias Weisser <weisserm@arcor.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
9e0081d573 mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
b809b3ac13 mx35: Define MAX and AIPS registers
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
df7e420bbd mx31: Add more CCM access macros
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
dd227b6ea0 mx5: Optimize lowlevel_init code size
Optimize mx5 lowlevel_init.S code size:
 - Compute values at compile time rather than at runtime where possible.
 - Assign r4 to hold the zero value rather than setting registers to 0 again and
   again.
 - Associate a function to setup_pll rather than expanding its large macro code
   multiple times.
 - Allocate constant values in section only if used.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
6be5800504 mx25: Fix eSDHC support
The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do
with mxcmmc.

Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set
accordingly. This is good for the case only a single SDHC instance is used
(initialization made with fsl_esdhc_mmc_init()). A future patch will fix the
multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
f7542638c7 mx25: Define cpu_eth_init() only if needed
The FEC is the only SoC Ethernet support available on i.MX25, so define
cpu_eth_init() only for it instead of returning a misleading success code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
9baefa465d mx25: Clean up clocks API
Use the standard mxc_get_clock() instead of exporting internal functions and
using literal constant values.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
17c7cf71b4 mx25 clocks: Fix MXC_FEC_CLK
mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock.

Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG
clock, so remove the duplicated code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:13 -07:00
Benoît Thébaudeau
c3b5189031 mx25: Define more standard clocks
Define AHB, IPG and CSPI clocks.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
fac7c817c3 mx25: Clean up clock calculations
Avoid possible overflow in clock calculations, and do not waste calls to lldiv()
to divide simple ulongs.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
3c76add262 mx25: Fix decode_pll
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
323846561a mx5/6 clocks: Fix SDHC clocks
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.

Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
be2f93b1ea mx51: Fix I2C clock ID check
There are only 2 I²C instances on i.MX51, but 3 on i.MX53.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
d5fe220df4 mx5 clocks: Fix MXC_FEC_CLK
The FEC clock does not come from PLL1, but from the IPG clock. The previous code
was even inconsistent with itself, returning the IPG clock as expected for
imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:12 -07:00
Benoît Thébaudeau
3cbd107b5f mx5 clocks: Simplify imx_get_cspiclk()
The code handling the dividers was duplicated for each possible input clock, and
this function can benefit from the newly introduced get_standard_pll_sel_clk()
function instead of duplicating this mux handling code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
08028b113e mx5 clocks: Fix get_uart_clk()
This function returned 66500000 instead of the correct lp_apm clock frequency if
the CCM.CSCMR1.uart_clk_sel mux is set to 3.

This patch fixes this issue by introducing the get_standard_pll_sel_clk()
function that will be used by future patches to handle identical muxes used by
many other clocks.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
f124e718f4 mx5 clocks: Fix get_ipg_per_clk()
This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue
was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case
CCM.CBCMR.perclk_lp_apm_sel is set.

It also fixes I²C support.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
55c8df0cb1 mx5 clocks: Fix get_periph_clk()
In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
b94792982f mx5 clocks: Fix get_lp_apm()
If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
 - on i.MX51, this clock comes from the output of the FPM,
 - on i.MX53, this clock comes from the output of PLL4.

This patch fixes the code accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
649dc8abd9 mx5 clocks: Add and use CCSR definitions
This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
414e1660c8 mx51: Fix USB PHY clocks
The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
2012-10-15 11:54:11 -07:00
Benoît Thébaudeau
248cdf0b52 mx5: Fix clock gate values
The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Benoît Thébaudeau
1f5e4ee0b9 mx5: Use explicit clock gate names
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Benoît Thébaudeau
846b38981f mx5 clocks: Cleanup
Clean up the i.MX5 clock driver:
 - Use readl() and writel() instead of their __raw_ counterparts.
 - Use the clr/setbits_le32() family of macros rather than expanding code.
 - Use accessor macros for bit-fields instead of _MASK and _OFFSET.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Benoît Thébaudeau
833b6435de mx5/6: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:10 -07:00
Matthias Weisser
e7bed5c2b3 imx: Use MXC_I2C_CLK in imx i2c driver
i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Eric Benard
8a57fdc640 mx25: add CPU revision 1.2
tested on a MCIMX257CJM4A which now reports :
CPU:   Freescale i.MX25 rev1.2 at 399 MHz

Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-10-15 11:54:10 -07:00
Eric Nelson
2af7e81015 i.MX6: get rid of redundant struct src_regs (dupe of struct src)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
de710a14b5 i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfields
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:09 -07:00
Eric Nelson
e66ad6e747 i.MX6: Add ANATOP_PFD_480 bitfield constants
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:09 -07:00
Eric Nelson
a83e1b7b8c i.MX6: define IOMUX_GPR3 register bitfields
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
344da71a20 i.MX6: define bitfields for CHSCCDR register
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:09 -07:00
Eric Nelson
da6df2d1c8 i.MX6: change register name for CCM_CHSCCDR to match ref. manual
Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in
reference manual, but was named chscdr in struct mxc_ccm_reg.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:08 -07:00
Eric Nelson
0bb7e316f0 i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:08 -07:00
Lukasz Dalek
539e9ffd92 pxa: Add code to examine cpu model and revision
Add function which return CPU model and revision which can be used for
cpu detection.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
c0720afbb5 tegra: nand: add board pinmux
Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
516f00b324 tegra: clean up board include hell
The prototypes used in board files were all scattered out, which lead to
code duplication between SPL and normal U-Boot and some prototypes not actually
being used. Consolidate this in a common board header.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
ac56d959a3 tegra: add funcmux entry for NAND attached to KBC
Secondary config for the Flash attachment.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
0cd10c7abf tegra20: rework UART GPIO handling
Rename board provided gpio_config_uart() to
gpio_early_init_uart() as it does the same thing as the equally
called function provided by the uart-switch code. This allows
to simply call this function in early board init whether or not
we are building with CONFIG_UART_SWITCH defined.

Also provide a weak symbol for this function, to avoid the
need to provide this function for boards that don't need any
fixup.

This patch supersedes the earlier posted
"tegra: convert gpio_config_uart to weak symbol".
Build tested with MAKEALL -s tegra20

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
65530a842e tegra20: add clock_set_pllout function
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.

This function adds a clean way to do so.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:07 -07:00
Lucas Stach
3f44e44f33 tegra20: complete periph_id enum
Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:06 -07:00
Tom Warren
150c24936b Tegra20: Move some include files to arch-tegra for sharing with Tegra30
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:06 -07:00
Tom Warren
3064f32278 Tegra20: Move some code files to common directories for upcoming Tegra30 patches.
Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any
files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs
and modified for that SoC. The 'common' files should need only minor changes.

Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a
follow-on patch.

Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-15 11:54:06 -07:00
Lucas Stach
6d365ea0ac tegra20: add USB ULPI init code
This adds the required code to set up a ULPI USB port. It is
mostly a port of the Linux ULPI setup code with some tweaks
added for more correctness, discovered along the way of
debugging this.

To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-10-15 11:54:01 -07:00
Lucas Stach
a896211ff1 tegra20: port to new ehci interface
EHCI interface now supports more than one controller. Wire up our usb functions
to use this new interface.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
2012-10-15 11:54:00 -07:00
Lucas Stach
676ae068d9 usb: ehci: rework to take advantage of new lowlevel interface
Kill off ehci-core.h
It was used to specify some static controller data. To support more than
one controller being active at any time we have to carry the controller
data ourselfes. Change the ehci interface accordingly.

NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed
to do the same thing as other platforms. But the change for now is at least
compile clean.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15 11:54:00 -07:00
Lucas Stach
c7e3b2b586 usb: lowlevel interface change to support multiple controllers
Carry an index in the lowlevel usb functions to make specify the
respective usb controller.

Also pass through an controller struct from lowlevel_init to the
creation of the root usb device of this controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2012-10-15 11:54:00 -07:00
Stefan Roese
a821d08dca ppc4xx: Remove AP1000 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: James MacAulay <james.macaulay@amirix.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
dee9c534db ppc4xx: Remove ML2 board support
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter De Schrijver <p2@mind.be>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Stefan Roese
99bcad1809 ppc4xx: Remove IOP480 support
Since the IOP480 (PPC401/3 variant from PLX) is only used on 2
boards that are not actively maintained, lets remove support
for it completely. This way the ppc4xx code will get a bit cleaner.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-15 11:53:59 -07:00
Marek Vasut
036036d79c serial: Remove CONFIG_SERIAL_MULTI from remaining sources
Remove the parts depending either on disabled CONFIG_SERIAL_MULTI
or ifdefs around CONFIG_SERIAL_MULTI parts since CONFIG_SERIAL_MULTI
is now enabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:59 -07:00
Marek Vasut
a382725060 serial: Remove CONFIG_SERIAL_MULTI from serial drivers
Remove the support for not-CONFIG_SERIAL_MULTI part from serial
port drivers and some board files. Since CONFIG_SERIAL_MULTI is
now enabled by default, that part is a dead code. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:58 -07:00
Marek Vasut
320de1354f serial: mxs: spl: Remove empty serial_* functions from SPL code
Remove the empty bodies from serial_* functions from MXS SPL code.
These empty implementations are now in common/serial.c instead so
declaring them also in the SPL code would cause a colision once
serial multi is enabled unconditionally.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:53:57 -07:00
Marek Vasut
29b5ff7f8e serial: sparc: Implement CONFIG_SERIAL_MULTI into leon3 serial driver
Implement support for CONFIG_SERIAL_MULTI into leon3 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the leon3 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
2012-10-15 11:53:52 -07:00
Marek Vasut
af7be3b6a9 serial: sparc: Implement CONFIG_SERIAL_MULTI into leon2 serial driver
Implement support for CONFIG_SERIAL_MULTI into leon2 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the leon2 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
2012-10-15 11:53:52 -07:00
Marek Vasut
fcc2074d57 serial: powerpc: Implement CONFIG_SERIAL_MULTI into iop480 serial driver
Implement support for CONFIG_SERIAL_MULTI into iop480 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the iop480 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:52 -07:00
Marek Vasut
7a31154627 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc85xx serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc85xx serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc85xx driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:52 -07:00
Marek Vasut
d68f4da2fa serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8260 serial drivers
Implement support for CONFIG_SERIAL_MULTI into both SCC and SMC mpc8260
serial drivers. These drivers were so far only usable directly, but this
patch also adds support for the multi method. This allows using more than
one serial driver alongside the mpc8260 drivers. Also, add a weak
implementation of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
2063a54e14 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8220 serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc8220 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc8220 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
b57c652802 serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc5xx serial driver
Implement support for CONFIG_SERIAL_MULTI into mpc5xx serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the mpc5xx driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:51 -07:00
Marek Vasut
6cb3273d11 serial: mips: Implement CONFIG_SERIAL_MULTI into JZ serial driver
Implement support for CONFIG_SERIAL_MULTI into JZ serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the JZ driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-10-15 11:53:51 -07:00
Marek Vasut
0191142283 serial: mips: Implement CONFIG_SERIAL_MULTI into asc serial driver
Implement support for CONFIG_SERIAL_MULTI into asc serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the asc driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-10-15 11:53:51 -07:00
Marek Vasut
7b953c5165 serial: mips: Implement CONFIG_SERIAL_MULTI into au1x00 serial driver
Implement support for CONFIG_SERIAL_MULTI into au1x00 serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the au1x00 driver. Also, add a weak implementation
of default_serial_console() returning this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-10-15 11:53:51 -07:00
Marek Vasut
41651cab97 serial: bfin: Flip the jtag serial console to CONFIG_SERIAL_MULTI
Rework the emulation of serial console via JTAG from simple ad-hoc
implementation of serial port routines to CONFIG_SERIAL_MULTI and
enable CONFIG_SERIAL_MULTI unconditionally for blackfin.

In order for the JTAG serial console to take precedence over all
other serial ports available in system, implement override for
default_serial_console call returning this JTAG serial console.

This brings in a bit of a growth of size, but eventually will allow
us to unconditionally enable CONFIG_SERIAL_MULTI throughout the whole
U-Boot and maintain only one serial subsystem.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-15 11:53:51 -07:00
Marek Vasut
5ae1de0d49 serial: bfin: Adjust serial_register_bfin_uart()
Rename the serial_register_bfin_uart() to bfin_initialize_serial()
to be consistent with the rest of the naming. Next, remove it's
prototype from serial.h and properly insert it into serial.c as
the rest of the serial initialization functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-15 11:53:50 -07:00
Marek Vasut
918327c8f0 serial: mpc512x: Move serial registration from serial_initialize()
Move the registration of serialN_device ports from default
serial_initialize() into driver specific function called from
serial_initialize(). This slims down the serial_initialize() call
to a bare tracker of all possible serial port registration routines
in U-Boot.

The newly implemented mpc512x_serial_initialize() function, which is
implemented inside of the mpc512x serial driver allows encapsulation
of serialN_device within the mpc512x serial driver itself.

Also, remove the exports of serialN_device from include/serial.h
as they are no longer needed. This is simply because the implementation of
default_serial_console() is wrapped into the mpx512x serial driver and
the default console is picked by CONFIG_SERIAL<N> macro in config file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
2012-10-15 11:53:50 -07:00
Marek Vasut
f0eb1f61b0 serial: mpc8xx: Move serial registration from serial_initialize()
Move the registration of serial_smc and serial_scc ports from
default serial_initialize() into CPU specific function called from
serial_initialize(). This slims down the serial_initialize() call
to a bare tracker of all possible serial port registration routines
in U-Boot.

The exports of both serial_scc_device and serial_smc_device can
not yet be removed as they are still used in default_serial_console()
calls.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-15 11:53:49 -07:00
Marek Vasut
90bad891e1 serial: Properly spell out the structure member names of serial_driver
Properly spell out the whole structure member names when an initialized
varible is instantiated from the struct serial_driver. In case the
structure definition for struct serial_driver undergoes reordering,
there will be no impact on variables defined based on this structure.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: C Nauman <cnauman@diagraph.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michal Simek <monstr@monstr.eu>
2012-10-15 11:53:48 -07:00
Marek Vasut
89143fb3b0 serial: Rename .init() and .uninit() in serial_device
Rename .init() to .start() and .uninit() to .stop() in struct
serial_device. This allows aligning struct serial_device with
closer to struct stdio_dev. The real goal here is to allow
these two structures to converge together and eventually make
one to be a superset of the other.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:48 -07:00
Marek Vasut
5368c55d4c COMMON: Use __stringify() instead of MK_STR()
Kill multiple occurances and redeclaration of MK_STR
in favor of __stringify().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:47 -07:00
Albert ARIBAUD
b823fd9ba5 ARM: prevent misaligned array inits
Under option -munaligned-access, gcc can perform local char
or 16-bit array initializations using misaligned native
accesses which will throw a data abort exception. Fix files
where these array initializations were unneeded, and for
files known to contain such initializations, enforce gcc
option -mno-unaligned-access.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Switch to usign call cc-option for -mno-unaligned-access as
Albert had done previously as that's really correct]
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:07 -07:00
Albert ARIBAUD
dec96689ca arm: armv7: omap3: Fix restore sequence in lowlevel_init
The restore sequence in lowlevel_init was in the wrong order,
causing lr to lose its original value and be set equal to ip
instead. Also, its use of the stack clashes with that of
s_init, so move the s_init call after the restore and turn
it  into a tail-optimized branch.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2012-10-08 11:15:04 -07:00
Tetsuyuki Kobayashi
03eecab9a1 arm: rmobile: bugfix: wrong register saving in lowlevel_init
lowlevel_init() of rmobile badly assumed that ip register holds return address.
The commit "63ee53a7 armv7 cpu_init_crit: Simplify code" breaks this assumption.
This patch removes this bad assumption and simplify code.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2012-10-08 11:15:04 -07:00
Tom Rini
89e76b5f86 Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-10-05 13:56:45 -07:00
Albert ARIBAUD
28e5ac2d97 arm: armv7: temporarily set -mno-unaligned-access
This patch aims at ensuring that the 2012.10 release works
out-of-the-box on as many targets as possible, by reinstating
commit 5347560f5427bcdd48a563b62180481606ac8044, which adds
option -mno-unaligned-access to armv7 builds.

This patch will be overriden immediately after release of 2012.10.
2012-10-05 21:24:22 +02:00
Tom Rini
1981668777 Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-10-04 10:00:42 -07:00
Dinh Nguyen
777544085d ARM: Add Altera SOCFPGA Cyclone5
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Tom Trini <trini@ti.com>
Cc: Wolfgang Denx <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
----
v8: Remove no_return attribute for reset_cpu

Based on v2012.10-rc2
2012-10-04 18:11:52 +02:00
Michal Simek
38b343dd05 arm: Support new Xilinx Zynq platform
Add timer driver.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-10-04 16:46:29 +02:00
Zhong Hongbo
76abfa5781 arm: Fixed the offset for the no relocation.
When the u-boot address of destination equal to  __start,
no relocation. relocation offset(r9) = 0.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Tested-by: Stefano Babic <sbabic@denx.de>
2012-10-04 16:41:15 +02:00
Joe Hershberger
c6734261ec arm: Add CONFIG_OF_BOARD_SETUP support to bootm
ARM boards need to change device tree settings as well

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-10-04 16:11:18 +02:00
Michal Simek
4e7067f332 arm: Remove additional config flags
These options are just duplicated from arch/arm/cpu/armv7/config.mk

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-10-04 14:51:50 +02:00
Benoît Thébaudeau
63ee53a7e9 armv7 cpu_init_crit: Simplify code
We don't need to return to cpu_init_crit after calling lowlevel_init, so
lowlevel_init can directly return to the caller of cpu_init_crit.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2012-10-04 14:19:07 +02:00
Allen Martin
0f20bb601f arm: work around assembler bug
Disable sibling call optimization based on binutils version.  This is
to work around a bug in the assember in binutils versions < 2.22.
Branches to weak symbols can be incorrectly optimized in thumb mode to
a short branch (b.n instruction) that won't reach when the symbol gets
preempted.

http://sourceware.org/bugzilla/show_bug.cgi?id=12532

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
2012-10-04 14:19:04 +02:00
Rob Herring
fcfa696b3a ARM: increase lmb stack space reservation to 4KB
The bootm initrd image copy to ram can collide with the stack in cases
where the print buffer size is large (i.e. 1K). The result is intermittent
initrd decompression errors depending on the initrd size MOD 4KB since
the initrd start address is 4KB aligned.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-10-04 10:25:40 +02:00
Albert ARIBAUD
386c6cb10d Merge remote-tracking branch 'u-boot-marvell/master' 2012-10-03 16:44:29 +02:00
Dinh Nguyen
7029394d82 ARM: kirkwood/orion5x: Use reset_cpu definition in include/common.h
include/common.h has the reset_cpu defined already. No need to
re-define here.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03 16:43:13 +05:30
Gerlando Falauto
b3168f4be8 kirkwood: implement kw_sdram_size_adjust
Size of the SDRAM chips might differ between any two (otherwise
identical) instances of the same board.

So add a function kw_sdram_size_adjust() which reads out the current
ram size for a given bank, and adjusts the Kirkwood's SDRAM window size
register accordingly.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2012-10-03 16:43:13 +05:30
Gerlando Falauto
4551516525 kirkwood: implement kw_sdram_bs_set()
Some boards might be equipped with different SDRAM configurations.
When that is the case, CPU CS Window Size Register (CS[0]n Size)
should be set to the biggest value through board.cfg file; then its
value can be fixed at runtime according to the detected SDRAM size.

Therefore, implement kw_sdram_bs_set().

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Marek Vasut <marex@denx.de>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03 16:43:13 +05:30
Holger Brunck
cf37c5d98b kirkwood: use c-struct for access to SDRAM addr decode registers
Remove the defines and do this with a C-struct.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Marek Vasut <marex@denx.de>
Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
2012-10-03 16:43:13 +05:30
Luka Perkov
6d4ebd159e kirkwood: fix mpp.h coding style
Signed-off-by: Luka Perkov <uboot@lukaperkov.net>
2012-10-03 16:43:13 +05:30
Gabriel Huau
5d889ae79e ARM : Add GPIO Driver and IOMUX definition for S3C2440
It's now possible to use the gpio driver interface
for s3c2440. This patch add iomux definitions too.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
2012-10-03 10:50:20 +02:00
Nobuhiro Iwamatsu
35729c6cb3 rmobile: Fix build timer driver with BUILD_DIR
Rmobile common timer driver  diverts the same driver as SH architecture.
When it builds at the same place with source, it is no problem, but when
it builds out of source, it cannot build.
This patch revises this problem.

Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2012-10-03 08:47:29 +02:00
Nobuhiro Iwamatsu
2d61084be9 arm: rmobile: Add cpu_eth_init function
This supports ethernet driver of RMOBILE R8A7740.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Hideyuki Sano
1a31ca4a78 arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA board
The Armadillo-800EVA board has Renesas R-Mobile R8A7740, 512MB DDR3-SDRAM,
Ethernet, and more.

This patch supports the following functions:
 - 512MB DDR3-SDRAM
 - Serial console (SCIF)
 - Ethernet MAC(MII) & PHY(SMSC)

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Nobuhiro Iwamatsu
62d0b6bab1 arm: rmobile: Add support PFC of Renesas R8A7740
Renesas R8A7740 has GPIO based PFC. This privode framework of PFC.
The code included in this base from linux kernel.

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Nobuhiro Iwamatsu
cfa291b7b8 arm: rmobile: Add support Renesas R8A7740
Renesas R8A7740 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.

Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:25 +02:00
Nobuhiro Iwamatsu
2c541df901 arm: rmobile: Add support TMU base timer function
Some rmobile SoC has TMU base timer function. This supports TMU.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:24 +02:00
Nobuhiro Iwamatsu
2f7ea5b047 arm: rmobile: Change initializing ICCICR register
There is rmobile without ICCICR.
ICCICR is initialized only when ICCICR is defined.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:24 +02:00
Tetsuyuki Kobayashi
4f007b8334 arm: rmobile: kzm9g: separate cpu_rev to integer and fraction
According to SoC document, revision info is separated to integer part and
fracton part.
So I separete rmobile_get_cpu_rev() to rmobile_get_cpu_rev_integer() and
rmobile_get_cpu_rev_fraction().

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:24 +02:00
Tetsuyuki Kobayashi
170cc96f6c arm: rmobile: kzm9g: fix CPU info
CPU info register was read wrongly by mistake. And function rmobile_get_cpu_rev() was not called properly.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:24 +02:00
Tetsuyuki Kobayashi
2c1157df46 arm: rmobile: kzm9g: Add dummy member to struct sh73a0_rwdt
Add dummy member to struct sh73a0_rwdt in sh73a0.h.
Without this, initializing watch dog timer goes wrong.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:23 +02:00
Nobuhiro Iwamatsu
c7ee8a508b arm: rmobile: Support build with gcc-4.6 or later
Latest rmobile code was tested by using old gcc (gcc-4.4).
When we use gcc-4.6 (or later), the build is made, but does not work.
This solves a problem not to work by add -march=armv5 to compiple option
when we built in gcc-4.6 (or later).
I tested by linaro's compiler version 2012.04-20120426.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:23 +02:00
Tetsuyuki Kobayashi
4306abda00 arm: rmobile: kzm9g: enable reset command
Do soft power on reset in U-Boot reset command.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:23 +02:00
Tetsuyuki Kobayashi
a12633122c arm: rmobile: kzm9g: Adjust low level hardware setting
Adjust low level hardware setting in s_init.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
8d811ca36a arm: rmobile: Add supoprt for KMC KZM-A9-GT board
The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM,
USB, Ethernet, and more.

This patch supports the following functions:
	- 512MB DDR2-SDRAM
	- 16MB NOR Flash memory
	- Serial console (SCIF)
	- Ethernet (SMSC)
	- I2C

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
b045a23773 arm: rmobile: Add support PFC of Renesas SH73A0
Renesas SH73A0 has GPIO based PFC. This privode framework of PFC.
The code included in this base from linux kernel.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
1cdf2482d1 arm: rmobile: Add support Renesas SH73A0
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
4fb44e22ec arm: rmobile: Add basic support for Renesas R-Mobile
This patch adds minimum support for R-Mobile. Only minimal support with timer.
This CPU can uses the peripheral of Renesas SuperH.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Nobuhiro Iwamatsu
a6cd85aad2 ARMv7: Add register definition of global timer
ARMv7 has global timer. This provides the register definition of this timer.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-10-03 02:04:22 +02:00
Simon Glass
94fd1316b7 bootstage: Store boot timings in device tree
Add an option, CONFIG_BOOTSTAGE_FDT to pass boot timings to the kernel
in the device tree, if available. To use this, you must have
CONFIG_OF_LIBFDT defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-02 22:39:33 +02:00
Stefan Kristiansson
f9882246a0 openrisc/bitops: add hweightX defines
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2012-10-02 11:55:45 -07:00
Stefan Kristiansson
2bcffa6faa openrisc: implement get_ticks and get_tbclk
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2012-10-02 11:55:45 -07:00
Joel A Fernandes
90207b6268 am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XX
U-boot should not ignore getting the bootmode passed on from the bootrom.
With this, U-boot SPL knows it was loaded from MMC1 and use this info to
read full U-boot from MMC1 as well.

Cc: pprakash@ti.com
Cc: trini@ti.com
Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-01 10:02:15 -07:00
Ilya Yanok
7ac2fe2da2 OMAP: networking support for SPL
This patch adds support for networking in SPL. Some devices are
capable of loading SPL via network so it makes sense to load the
main U-Boot binary via network too. This patch tries to use
existing network code as much as possible. Unfortunately, it depends
on environment which in turn depends on other code so SPL size
is increased significantly. No effort was done to decouple network
code and environment so far.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-01 10:02:14 -07:00
Albert ARIBAUD
1c27059a2f Merge remote-tracking branch 'u-boot/master' 2012-09-30 23:49:17 +02:00
Simon Glass
4668a086bb sandbox: Add asm/errno.h
This file is required for all archs. Fixes a sandbox build break on ext4.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-09-29 10:00:29 -07:00
Albert ARIBAUD
8f0732ac3d Merge remote-tracking branch 'u-boot-imx/master' 2012-09-29 11:12:34 +02:00
Tom Rini
cec2655c3b Merge branch 'master' of git://git.denx.de/u-boot-net 2012-09-27 12:06:07 -07:00
Tom Rini
3f7f2414ef ARM: SPL: Convert davinci to CONFIG_SPL_FRAMEWORK
- Convert the non-relocation part of board_init_f to spl_board_init, turn on CONFIG_SPL_BOARD_INIT in the configs.
- Remove duplicated code.
- Add spl_boot_device() that returns the statically chosen boot device.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 11:20:10 -07:00
Tom Rini
d97b4ce805 SPL: NAND: Move arch/arm/cpu/armv7/omap-common/spl_nand.c to common/spl
We move the spl_nand_load_image function to common/spl.  This will allow
for easier integration of SPL-boots-Linux code on other arches.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:50:00 -07:00
Tom Rini
6507f133f3 SPL: Create arch/arm/lib/spl.c for board_init_f and jump_to_image_linux
In SPL (CONFIG_SPL_FRAMEWORK) board_init_f must setup the stack pointer,
clear the BSS and call board_init_r.  We mark this as weak as some
platforms may need to perform additional initalization at this point.
We provide a gd that we know will be in a usable location, once the BSS
has been cleared to help with this as well.  Finally, we no longer call
relocate_code so remove that from the armv7 version.

Next, both board_init_f and jump_to_image_linux are going to be
inherently arch-specific, so move these versions to arch/arm/lib/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
47f7bcae8c SPL: Move the omap SPL framework to common/spl
Add a new flag, CONFIG_SPL_FRAMEWORK to opt into the common/spl SPL
framework, enable on all of the previously using boards.  We move the
spl_ymodem.c portion to common/ and spl_mmc.c to drivers/mmc/.  We leave
the NAND one in-place as we plan to replace it later in this series.

We use common/spl to avoid linker problems with respect to merging
constant strings in objects.   Otherwise all strings in common/ will be
linked in and kept which grows SPL in size too much.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
d7cb93b28a ARM: SPL: Move gpmc_init() to spl_board_init()
This is an OMAP/related-specific function, move calling it to
spl_board_init() and turn on CONFIG_SPL_BOARD_INIT on the boards that
enabled NAND and didn't enable this already.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:59 -07:00
Tom Rini
d4c4e0e117 ARM: SPL: Start hooking in the current SPI SPL support
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:58 -07:00
Tom Rini
026b2fe32c ARM: SPL: Clean up spl.c / spl_nand.c slightly
- Remove includes we don't need
- Switch some printf statements to puts
- Convert some printf statements to debug, introduce new puts statements
  - In most cases saying just "No mkimage signature, assuming
    u-boot.bin" or similar is sufficient.  This also means the non-DEBUG
    case doesn't need printf, in the core of SPL.
  - The other case here is that PLAIN_VERSION provided what we wanted
    already, so just use it.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:58 -07:00
Tom Rini
f0881250f9 ARM: SPL: Make spl_mmc.c more generic
Move the default omap/related-centric board_mmc_init to
arch/arm/cpu/armv7/omap-common/boot-common.c and move the type defines
to <asm/spl.h>.  Also use mmc->read_bl_len rather than MMCSD_SECTOR_SIZE

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:58 -07:00
Tom Rini
55cdbb8d4e ARM: SPL: Add <asm/spl.h> and <asm/arch/spl.h>
Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and
add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:49:57 -07:00
Tom Rini
24dafad5c4 ARM: SPL: Only call mem_malloc_init if configured
We can only attempt to setup a malloc pool if
CONFIG_SYS_SPL_MALLOC_START is defined, and not all boards require it.
Make the call depend on the define.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:39 -07:00
Tom Rini
8082fda9fc ARM: SPL: Remove NAND_MODE_HW_ECC from spl_nand.c
This detection code doesn't (and can't) do anything currently, so
remove.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:39 -07:00
Tom Rini
37189a1958 ARM: SPL: Rename omap_boot_mode to spl_boot_mode()
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:39 -07:00
Tom Rini
8e1b836ec5 ARM: SPL: Rename omap_boot_device to spl_boot_device
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:38 -07:00
Pavel Machek
9f8a6e7ae7 omap-common: SPL: Fix whitespace in omap-common/u-boot-spl.lds.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:38 -07:00
Tom Rini
6abbe744d2 omap-common: Fix typo in save_boot_params() in lowlevel_init.S
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:38 -07:00
Tom Rini
861a86f460 omap-common: SPL: Add CONFIG_SPL_DISPLAY_PRINT / spl_display_print()
Only omap4/5 currently have a meaningful set of display text and overo
had been adding a function to display nothing.  Change how this works to
be opt-in and only turned on for omap4/5 now.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:38 -07:00
Tom Rini
0da113e9fd spl_mmc: Make FAT checks / calls guarded with CONFIG_SPL_FAT_SUPPORT
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-27 09:48:37 -07:00
Daniel Schwierzeck
00d0d2ad4e malloc: remove extern declarations of malloc_bin_reloc() in board.c files
Declare malloc_bin_reloc() in malloc.h and remove all extern declarations
in various board.c files to get rid of one checkpatch.pl warning.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andreas Bießmann <andreas.devel@gmail.com>
Cc: Jason Jin <Jason.jin@freescale.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
2012-09-26 11:08:32 -07:00
Stephen Warren
59d63f7d2c ARM: arm1176: Define arch_cpu_init() at the SoC level
Commit 86c6326 "ARM: arm1176: enable instruction cache in
arch_cpu_init()" defined arch_cpu_init() in a file that is shared across
all arm1176 SoCs. tnetv107x already implemented this function, which
caused linking to break. Move the new conflicting arch_cpu_init() into
arm1176/bcm2835/init.c so that it doesn't conflict; grep indicates this
function is usually defined at the SoC-level, not the CPU-level, at least
for ARM.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-25 13:27:58 -07:00
Tom Rini
5675b50916 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2012-09-25 12:23:55 -07:00
Marek Vasut
61e129885a dm: net: Move IXP NPE to drivers/net/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2012-09-24 13:17:24 -05:00
Eric Nelson
e1eb75b535 i.MX: shut down video before launch of O/S
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-09-24 10:48:58 +02:00
Benoît Thébaudeau
362635bd50 mx51evk: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG
information.

If this data is not present, the kernel misconfigures the TZIC, which results in
the timer interrupt handler never being called, so the kernel deadlocks while
calibrating its delay.

Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-23 19:55:06 +02:00
Tom Rini
495dbd72dd Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-09-21 14:53:13 -07:00
Albert ARIBAUD
d193c1b6eb Merge remote-tracking branch 'u-boot-imx/master' 2012-09-21 00:26:19 +02:00
Jason Jin
30a3f3881e Flex bus definition update for Coldfire 5253.
originally work by Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com>
----
The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with
the 5235 processor. The registers in struct fbcs are different sizes from
those in the 5235. Also, the defines are a little different.

This is what I have so far. Comments?
----

Reformat the patch manually by Jason Jin

Signed-off-by: Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2012-09-20 20:39:41 +08:00
Richard Retanubun
59d0612252 ColdFire: Queued SPI driver
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
2012-09-20 20:39:27 +08:00
Alison Wang
198cafbf2c ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
a4110eecf2 ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
c6d8863015 ColdFire: Clean up checkpatch warnings for MCF523x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
aa0d99fc28 ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
32dbaafa5a ColdFire: Clean up checkpatch warnings for MCF52x2
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Alison Wang
849fc42471 ColdFire: Clean up checkpatch warnings for MCF5227x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Alison Wang
33d4411931 ColdFire: Add clear and set bits macros for ColdFire platform
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Alison Wang
f7799a1175 ColdFire: Update the bitops for ColdFire platform
This patch uses the general ffs definition to replace the
platform ffs definition.

This patch also fixes the build error by adding hweightN
definition for m5329evb and m5373evb.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:37:40 +08:00
Marek Vasut
535c74f80c ARM: Remove apollon board
This board is the only board that still sticks to OneNAND IPL.
Remove this board, since we have SPL around for a while and
OneNAND is well supported in the SPL framework. The board can
be revived if necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Tom Rini <trini@ti.com>
2012-09-18 12:01:51 -07:00
Marek Vasut
b2f2760006 dm: sparc: Fixup the compile warnings in sparc code
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: u-boot-dm@lists.denx.de
2012-09-18 12:01:50 -07:00
Tom Rini
037e9d33db Merge branch 'master' of git://git.denx.de/u-boot-i2c 2012-09-17 11:39:03 -07:00
Stefano Babic
19f59ea6db MX6: drop binary constants from iomux header
Constants set with binary value (0b...) are not compiled
from old toolchain when used by the clrsetbits_le32 macro.
Replaces them with the corresponding hex value.

The error reported (for example with the mx6qsabrelite board)
is something like:

mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-17 13:17:06 +02:00
Tom Rini
8f082d78fa Merge branch 'master' of git://git.denx.de/u-boot-mips 2012-09-14 07:15:48 -07:00
Tom Rini
a9ae14fce3 Merge branch 'master' of git://www.denx.de/git/u-boot-mmc 2012-09-12 10:26:06 -07:00
Michal Simek
c60a57912a microblaze: board: Use bi_flashstart instead of CONFIG_SYS_FLASH_BASE
Prepare for device-tree driven configuration.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
2012-09-11 09:24:58 +02:00
Michal Simek
2380b8f529 microblaze: Clean microblaze initialization
Move board specific function to board_init function in board/ folder
Remove externs from generic board.c
Use board_init_f function in board.c file.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
2012-09-11 09:24:58 +02:00
Michal Simek
bcbb046bd5 microblaze: timer: Prepare for device-tree initialization
Fix CONFIG_SYS_HZ usage in board config.

Do not use hardcoded value. Use CONFIG_SYS_HZ instead.
Separate static configuration to single block.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-09-11 09:24:58 +02:00
Michal Simek
26e6da854e microblaze: intc: Coding style cleanup
Just coding style cleanup.
Remove unneeded externs.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephan Linz <linz@li-pro.net>
2012-09-11 09:24:57 +02:00
Michal Simek
8706908a25 microblaze: intc: Registering interrupt should return value
Return value to find out if un/registration was succesful.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-09-11 09:24:57 +02:00
Michal Simek
e35c05baa1 microblaze: board: Remove compilation warning
Variable is used when CONFIG_SYS_FLASH_CHECKSUM is used.

Warning log:
board.c: In function 'board_init':
board.c:101: warning: unused variable 's'

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
2012-09-11 09:24:57 +02:00
Michal Simek
b710d9d6c2 microblaze: Add support for device tree driven board configuration
This is minimum code required to be able to use device-tree
for u-boot initialization.
Currently only for device driver initialization.

Linker script change ensures DTB to be aligned
for both options CONFIG_OF_EMBED and CONFIG_OF_SEPARATE.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
CC: Simon Glass <sjg@chromium.org>
2012-09-11 09:24:56 +02:00
Tom Warren
29f3e3f248 Tegra: Change Tegra20 to Tegra in common code, prep for T30
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2012-09-10 13:01:24 -07:00
Lucas Stach
22e7394021 tegra20: usb: rework set_host_mode
This allows for two things:
- VBus GPIO may be used on other ports than the OTG one
- VBus GPIO may be low active if specified by DT

Signed-off-by: Lucas Stach <dev@lynxeye.de>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <TWarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-10 13:01:21 -07:00
Stefano Babic
ea00e59be0 MX: set a common place to share code for Freescale i.MX
Up now only MX5 and MX6 can share code, because they have
a common source directory in cpu/armv7. Other not armv7
i.MX can profit of the same shared code. Move these files
into a directory accessible for all, similar to plat-mxc
in linux.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-10 14:24:29 +02:00
Jim Lin
312693c3dd tegra: nand: Add Tegra NAND driver
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.

If this node is not present or is disabled, then NAND will not
be initialized.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:31 -07:00
Simon Glass
c6af2e7d87 tegra: fdt: Add NAND controller binding and definitions
Add a NAND controller along with a bindings file for review.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:30 -07:00
Simon Glass
35e1132c88 tegra: Add NAND support to funcmux
Add selection of NAND flash pins to the funcmux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-07 13:54:30 -07:00
Benoît Thébaudeau
0dc7b82e4e mx31: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX31 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Helmut Raiger <helmut.raiger@hale.at>
2012-09-06 14:23:30 +02:00
Benoît Thébaudeau
697191d57f Fix mx31_decode_pll
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 11:07:52 +02:00
Benoît Thébaudeau
543d247935 mx35 timer: Switch to 32-kHz source
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-06 11:05:24 +02:00
Benoît Thébaudeau
9c6c5c0676 mx35: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX35 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-06 11:05:17 +02:00
Benoît Thébaudeau
1b2080f338 mx25: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX25 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Matthias Weisser <weisserm@arcor.de>
2012-09-06 11:05:09 +02:00
Benoît Thébaudeau
82e1b543b5 mx35: Fix clock dividers
The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 11:05:01 +02:00
Benoît Thébaudeau
9ba81baabb mx35: Add definitions for clock gate values
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 11:04:53 +02:00
Benoît Thébaudeau
e761955417 mx35: Fix decode_pll
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-06 11:04:41 +02:00
Koen Kooi
a532278074 omap4 i2c: add support for i2c bus 4
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
2012-09-06 06:01:09 +02:00
Jaehoon Chung
8458e0283f mmc: s5p_sdhci: fixed wrong function argument
Useless code is removed, and get buswidth value.
buswidth value will be used to choice the 4bit or 8bit.
(Now used 4bit mode in sdhci.c by default)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-09-05 17:33:26 -05:00
Albert ARIBAUD
057df193b4 Merge remote-tracking branch 'u-boot-ti/master' into m 2012-09-05 20:20:04 +02:00
Tom Rini
14dace7058 am33xx: Remove redundant timer config
We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that
has been configuring and enabling the timer, so remove our code that
does the same thing by different methods.

Tested on EVM GP, SK-EVM and Beaglebone.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-04 17:05:39 -07:00
Stefano Babic
fb380bfa8c OMAP3: video: add macros to set display parameters
Add a common macros to set the registers for horizontal
and vertical timing.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-04 17:05:39 -07:00
Stefano Babic
baee780013 video: drop duplicate set of DISPC_CONFIG register
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-04 17:05:39 -07:00
Arnout Vandecappelle (Essensium/Mind)
4aaf06415f OMAP3: add definition of CTRL_WKUP_CTRL register
AM/DM37x SoCs add the CTRL_WKUP_CTRL register.  It contains the
GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads
of gpio_126, gpio_127 and gpio_129.

Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Cc: Tom Rini <trini@ti.com>
2012-09-04 17:05:38 -07:00
Markus Hubig
e23e5eeeb8 arm: Adds board_postclk_init to the init_sequence.
The board_postclk_init() function can be used to perform operations
that requires a working timer early within the U-Boot init_sequence.

Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-04 22:05:55 +02:00
Marek Vasut
d82f05fcad MX28: Fixup the ad-hoc use of DIGCTL_MICROSECONDS
Use proper struct-based access for this register in the SPL code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-04 11:57:57 +02:00
Wolfgang Denk
a6f0c4faa4 Merge branch 'master' of git://git.denx.de/u-boot-avr32
* 'master' of git://git.denx.de/u-boot-avr32:
  net:macb: add line break
  avr32:portmux: fix setup for macb1
  avr32: Remove redundant LDSCRIPT definition

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-09-04 09:17:27 +02:00
Andreas Bießmann
6314c84df1 avr32:portmux: fix setup for macb1
Use portd_mask instead of portc_mask to setup the pins for port D.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-03 23:37:16 +02:00
Valentin Longchamp
8203b201ea kw_spi: fix clock prescaler computation
The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.

This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2012-09-03 17:28:51 +05:30
Albert ARIBAUD
491f6c2f29 edminiv2: orion5x: fix GPIO inits and values
Orion5x did not actually write GPIO output values
or input polarities, and ED Mini V2 had bad or
missing values for GPIO settings.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
2012-09-03 17:04:29 +05:30
Anatolij Gustschin
e5ab702a6c powerpc: re-add bi_ip_addr to bd_t struct
Since commit 50a47d0523
(net: punt bd->bi_ip_addr) booting old 2.4.x ppc kernels
is broken due to changed offsets of the fields in struct bd_t.
Offsets of the fields after removed bi_ip_addr are wrong,
causing wrong bus clocks and console baudrate configurations
and various other issues. Re-add the bi_ip_addr field to preserve
backward compatibility with older ppc kernels. Setting bi_ip_addr
in board.c is not really needed, grepping in the 2.4 linux tree
shows that bi_ip_addr is not accessed there. Adding bi_ip_addr
to struct bd_t for other arches isn't needed it seems. bd_t is
not used by other arches in the 2.4 linux tree.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-09-02 22:55:59 +02:00
Joakim Tjernlund
83f83d1935 ppc: Create a stack frame for wait_ticks()
wait_ticks() calls get_ticks() without building a back chain which
makes gdb unhappy when doing back trace. This can also cause
improper memory accesses.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2012-09-02 17:10:21 +02:00
Wolfgang Denk
7cdcaef0b2 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  MUSB driver: Timeout is never detected as the while loop does not end
  usb: fix ulpi_set_vbus prototype
  pxa25x: Add UDC registers definitions
  USB: Fix strict aliasing in ohci-hcd
  usb: Optimize USB storage read/write
  ehci: Optimize qTD allocations
  usb_stor_BBB_transport: Do not delay when not required
  usb_storage: Remove EHCI constraints
  usb_storage: Restore non-EHCI support
  ehci-hcd: Boost transfer speed
  ehci: cosmetic: Define used constants
  ehci: Fail for multi-transaction interrupt transfers
  arm:trats: Enable g_dnl composite USB gadget with embedded DFU function on TRATS
  arm:trats: Support for USB UDC driver at TRATS board.
  dfu:cmd: Support for DFU u-boot command
  dfu: MMC specific routines for DFU operation
  dfu: DFU backend implementation
  dfu:usb: DFU USB function (f_dfu) support for g_dnl composite gadget
  dfu:usb: Support for g_dnl composite download gadget.
  ehci: cosmetic: Define the number of qt_buffers

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-09-02 16:38:48 +02:00
Benoît Thébaudeau
ef55e84a89 avr32: Remove redundant LDSCRIPT definition
AVR32's LD script uses a standard location that is now automatically detected by
the main Makefile, so its definition in AVR32's config.mk is now obsolete and
redundant.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-02 00:37:02 +02:00
Bo Shen
9bfc236872 atmel: at91sam9x5: fix name error for spi
Fix the name error

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 17:06:14 +02:00
Łukasz Dałek
a6a78be025 pxa25x: Add UDC registers definitions
Signed-off-by: Łukasz Dałek <luk0104@gmail.com>
2012-09-01 16:21:53 +02:00
Benoît Thébaudeau
8e99ecd74b mxc: Define architecture identifier
Define ARCH_MXC for i.MX devices. This is useful to identify features or
behaviors common to all i.MX SoCs.

The i.MX28 is omitted because its architecture is a bit different (like imx/mxc
vs. mxs in Linux).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
2012-09-01 14:58:30 +02:00
fabio.estevam@freescale.com
a123312f4d mxs: Convert timeout parameter to 'unsigned int'
For representing a timeout value, it makes more sense to pass it as
'unsigned int'.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:30 +02:00
Marek Vasut
615a4ad0f6 MX28: DMA: Align the struct mxs_dma_desc
Align this structure to DMA alignment size.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
trem
e71c39def6 gpio: add gpio api support to mx27 (v4)
The gpio api has been tested on an armadeus apf27.

Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Matt Sealey
af369d9831 mx5: add iomux-mx51.h include
Allow usage of the imx-common/iomux-v3.h framework by including pad settings
for the i.MX51. The content of the file is taken from Linux kernel at
commit 5d23b39 plus the required changes to make it work in U-Boot.

The contained pad settings are the minimum required to make an Efika MX boot
and get all the currently-implemented peripherals working in U-Boot.

It is recommended that this file not be just a dumping ground for pins but
only contain the settings required for all the boards using it.

Changes for v2:
 * reference commit id from Linux kernel
 * additionally roll in the USB pads
 * removed GPIO_NUMBER define

Signed-off-by: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Otavio Salvador
72f8ebf17e mxs: Rename 'mx28_dram_init' to 'mxs_dram_init'
The DRAM initialization, after SPL has complete, is exactly the same
for all mxs SoCs so we should name it accordinly.

The following boards has been changed:

 * apx4devkit
 * m28evk
 * mx28evk
 * sc_sps_1

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
2012-09-01 14:58:28 +02:00
Otavio Salvador
89ce53ffcd mxs: Only build internal Ethernet controller for i.MX28
The internal Ethernet controller is only available on i.MX28
processors so it needs to use CONFIG_MX28 guardian to avoid having
this code called in others.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-01 14:58:28 +02:00
Otavio Salvador
6e829b672e mxs: Replace i.MX233 by i.MX23 on copyright header
All other header are going to use i.MX23 so we change this for
consistency.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
483920f273 mx35: Remove declaration of non-existing function
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
7c80326d34 mx35: Move clock enums to clock.h
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
d365e2d7c3 mx35: Remove declaration of non-existing function
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
fe24d6143d mx35: Fix broken pin definitions
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:28 +02:00
Benoît Thébaudeau
e23ee5674a mx35 iomux: Remove unused macro
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Benoît Thébaudeau
4311c1ab6a mx5: Undeclare imx_decode_pll()
The imx_decode_pll() function does not exist for mx5, so remove its declaration.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Stefano Babic
5fecb36ca0 MX: Set a common gpio.h for all i.MX
Each i.MX has its own gpio.h, defining the same structure.
The internal GPIO controller has the same layout
(at least for the register used by u-boot) and can be shared.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Matt Sealey <matt@genesi-usa.com>
2012-09-01 14:58:27 +02:00
Fabio Estevam
c55068e5b8 mxs: Use correct function name to initialize dram
commit d92591a (mxs: Convert sys_proto.h prefixes to 'mxs') introduced
a mxs_dram_init() function, which is not used anywhere.

Fix it, so that the following warning goes away:

mx28evk.c: In function ‘dram_init’:
mx28evk.c:67:2: warning: implicit declaration of function ‘mx28_dram_init’ [-Wimplicit-function-declaration]

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:27 +02:00
Otavio Salvador
a54535551d MX28: config: Allow different target generation in elftosb call
The elftosb call needs to use a target param specific for i.MX28. This
patch allow for later addition of i.MX233.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-01 14:58:27 +02:00
Benoît Thébaudeau
09bc3d04d9 mx35: Add cpu_mmc_init()
Add cpu_mmc_init() function to make it easy to init a single eSDHC instance.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Benoît Thébaudeau
ecb0f31755 mx5/6: Fix cpu_mmc_init() return value
Do not pretend to have initialized mmc successfully if CONFIG_FSL_ESDHC is not
defined. Instead, only implement a custom cpu_mmc_init() when it does something.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:27 +02:00
Troy Kisky
124a06d7fb imx-common/cmd_bmode.c: add imx bmode (bootmode) command
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.

Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Note: MX53 support untested.
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Troy Kisky
d1c679a46d iomux: move IOMUX_GPR13_xxx defines
Move mx6 specific defines to arch-mx6 directory.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
83209cb785 mx35: Remove duplicate GPIO3_BASE_ADDR
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
18c63990ec mx5: cosmetic: Clean up lowlevel_init
Coding style cleanup:
 - Remove useless parentheses.
 - Use tabs for indentations and alignments.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
68d919d420 mx5/6 timer: Round up tick_to_time() value
Round up tick_to_time() value instead of truncating it. This avoids stopping
waits instantly for low usec values, and this generally guarantees that the code
always waits for at least the requested duration.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
f2d3ae0739 mx3: Fix typo on IPU_CONF_CSI_EN
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
34a31bf52b mx35: Fix typo on EDIO
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
78ff1a6cac mx5: Enable dcache
Now that the main i.MX features work fine with dcache enabled, enabled it by
default if CONFIG_SYS_DCACHE_OFF is not defined.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
e107c7e9e4 mx25: Enable dcache
Now that the main i.MX features work fine with dcache enabled, enabled it by
default if CONFIG_SYS_DCACHE_OFF is not defined.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
trem
78befb695d rtc: add support of mx27 rtc
This driver has been tested on board armadeus apf27.

Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:25 +02:00
Marek Vasut
fdb00b8127 MX28: Shuffle around the power management code
Move some function calls to a more appropriate place, so they're
called only when needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:25 +02:00
Marek Vasut
1b0f5597fb MX28: Drop the cp15 reconfiguration from SPL
The SPL doesn't need the CP15 reconfiguration, as that's what the
BootROM does for us already. Moreover, when the CP15 is reconfigured
and the code returns control to BootROM, the USB boot works no more.

Remove the code and allow [1] to work properly as well.

[1] http://git.bfuser.eu/?p=marex/mxsldr.git;a=summary

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:25 +02:00
Otavio Salvador
fa7a51cb82 mxs: Convert sys_proto.h prefixes to 'mxs'
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:25 +02:00
Otavio Salvador
af963ba8f4 mxs: rename regs-clkctrl.h to regs-clkctrl-mx28.h
The CLKCTRL registers are SoC specific so we ought to have it clear on
filename.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:25 +02:00
Otavio Salvador
d7d8a3a150 mxs: Remove not required include of iomux-mx28.h
The iomux-mx28.h include is not required on spl_mem_init.c so it has
been droped.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:25 +02:00
Otavio Salvador
f348199606 mxs: Remove not required explicit iomux-mx28.h include
The iomux header is included on sys_proto.h so to avoid SoC specific
header inclusion.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-01 14:58:25 +02:00
Łukasz Majewski
d7957d1d43 arm:exynos: Enable data cache at exynos based processors.
This patch enables the L1 data cache for systems based on Samsung
Exynos processor.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
6fff52b93a video: support exynos pwm backlight driver
This patch support exynos pwm backlight driver. It can control backlight
power and brightness by using pwm.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
a29c832263 video: exynos fb driver supports display port feature
If dp_enabled was set, exynos fb driver support display port feature.
This patch depends on [PATCH] video: support exynos fimd driver
for various exynos series.

http://marc.info/?l=u-boot&m=134119605104467&w=2

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
d2a6982f9b video: support exynos display port drivers
This patch set supports exynos display port drivers.

DisplayPort is an industry standard device to accommodate the increasing board
adoption of digital display technology within the PC and consumer electronics.
The interface supports internal chip-to-chip and external box-to-box digital
display connections.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
c401505000 EXYNOS5: add display port base address
This patch add display port base address for EXYNOS5. In case of EXYNOS4,
use DEVICE_NOT_AVAILABLE macro because DP is not supported.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
b6516677c0 EXYNOS5: support display port phy control function
This patch support display port phy control function.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
46524beb4a EXYNOS5: support display system register control
This patch supports display block system regisger control.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
2c5cd25cf9 EXYNOS5: support exynos5 lcd clock control
This patch support exynos5 lcd clock control.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Donghwa Lee
ee93dcfa2e video: support exynos fimd driver for various exynos series
This patch supports exynos fimd driver for various exynos series different from
existing it supports only exynos4 chip.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:24 +02:00
Jaehoon Chung
f8c5cfad7b ARM: EXYNOS: fixed compiler warning message
Removed [-Wuninitialized] warning message.
The fout_sel is assigned to "-1" by default.
And start, gpio_func is initialized to 0.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Zhong Hongbo
3936b4f057 arm/s5pxx: Fix get_timer_masked to get the time.
In general, The get_timer_masked function get the system time,
no the number of ticks. Such as the nand_wait_ready will use
get_timer_masked to delay the operations. And change the system
time to adopt to the CONFIG_SYS_HZ.

Signed-off-by: Hongbo Zhong <bocui107@gmail.com>
Tested-by: Jaehoon Chung<jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
fd8ef01452 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
10bc1a7f49 EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
6071bcaec1 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
87f2e079db Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
526b570699 EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Define additional registers for clock control in Exynos5250 Rev 1.0

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:23 +02:00
Rajeshwari Shinde
589c397169 ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01 14:58:22 +02:00
Tetsuyuki Kobayashi
6f0dba85a9 arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
This patch removes save_boot_params_default() and put the equivalent in start.S

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:22 +02:00
Allen Martin
cca60769fc tegra20: Remove armv4t build flags
These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9.  Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:22 +02:00
Allen Martin
c497be78b3 arm: enable libgcc build for SPL
Enable the building of private libgcc for SPL

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:22 +02:00
Allen Martin
12b7b70cb0 tegra20: enable SPL for tegra20 boards
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards.  Also remove redundant code from u-boot that is not
contained in SPL.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:22 +02:00
Allen Martin
a49716aa7c tegra20: move SDRAM param save to later in boot
Move warmboot_save_sdram_params() to later in the boot sequence.  This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:22 +02:00
Allen Martin
c037c93bf9 ARM: add tegra20 support to arm720t
Add support for tegra20 arm7 boot processor.  This processor is used
to power on the Cortex A9 and transfer control to it.  In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:22 +02:00
Allen Martin
c7da6c6757 ARM: Fix arm720t SPL build
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:21 +02:00
Allen Martin
d9e73a87a9 tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common.  This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:21 +02:00
Allen Martin
00a2749d7b tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01 14:58:21 +02:00
Stephen Warren
efad6cf881 ARM: add basic support for the Broadcom BCM2835 SoC
This SoC is used in the Raspberry Pi, for example.

For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.

Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.

GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2012-09-01 14:58:21 +02:00
Stephen Warren
86c632651d ARM: arm1176: enable instruction cache in arch_cpu_init()
Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.

Cc: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
f418597369 snowball: Adding board specific cache cleanup routine
Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
53e6f6a634 armv7: Adding cpu specific cache managmenent
Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
75dfe964cb u8500: Enabling power to MMC device on AB8500 V2
Register mapping has changed on power control chip between
the first and second revision.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
1e37322e5a u8500: Moving processor-specific functions to cpu area.
Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
b95f9ec7d8 snowball: applying power to LAN and GBF controllers
LAN and GBF need to be powered explicitely, doing so with
interface to AB8500 companion chip.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
101a769d75 snowball: Moving to ux500.v2 addess scheme for PRCMU access
Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
81637e26b3 snowball: Adding CPU clock initialisation
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:20 +02:00
Mathieu J. Poirier
9652de7c48 snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:19 +02:00
Mathieu J. Poirier
42cb8fb6cb u8500: Moving prcmu to cpu directory
This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01 14:58:19 +02:00
Mathieu J. Poirier
84dee301c3 snowball: Add support for ux500 based snowball board
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:

	drivers/gpio/Makefile
2012-09-01 14:58:19 +02:00
Tom Rini
77bfa6b436 davinci, c6x: Always use C version of reset code
We can safely use the same reset code written in C for both Davinci and
C6X platforms.  In addition the C version of the code is marginally
smaller on Davinci.

Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:19 +02:00
Satyanarayana, Sandhya
6995a28937 am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2012-09-01 14:58:19 +02:00
Sughosh Ganu
25f8bf6eff da8xx/hawkboard: Add support for ohci host controller
Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

Move the usb header for da8xx platforms under arch-davinci.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2012-09-01 14:58:19 +02:00
Tom Rini
975b71bc10 armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack
Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.

Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:19 +02:00
Tom Rini
41aebf8106 omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms
Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms.  As part of this we change some of the macros that are used
to be more clear.  Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END.  On am335x evm we
should have been doing this initially and do now.

Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:19 +02:00
Tom Rini
4c0620bf42 am33xx: Add support, update omap3 McSPI driver
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:18 +02:00
Tom Rini
0689a2ef19 am33xx: Correct MMC1, remove MMC2 support
- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:18 +02:00
Stathis Voukelatos
8b165a5394 i.MX28: bug fixes in PMU configuration code
Signed-off-by: Stathis Voukelatos <stathis.voukelatos@linn.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
2012-09-01 14:58:18 +02:00
Marek Vasut
7fb1ed0eab MX28: Move the u-boot.bd info CPUDIR/SOCDIR
This gets us rid of duplication of the same file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:18 +02:00
Otavio Salvador
41e5497225 mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCs
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
05c823bd32 mxs: Clarify why we poweroff in case of brownout in 5v conflict
If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable
but this wasn't clear on code so a comment has been added to clarify
it.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
1e0cf5c34b mxs: Reowork SPL to use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
9c471142bc mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
ddcf13b152 mxs: prefix register acessor macros with 'mxs' prefix
As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
3a0398d7b9 mxs: reorganize source directory for easy sharing of code in i.MXS SoCs
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:17 +02:00
Otavio Salvador
ab90b2c7fe MX28: use a clear name for DDR2 initialization
The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-01 14:58:16 +02:00
Otavio Salvador
b0261b1212 MX28: extend print_cpuinfo() to use chip information
The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:16 +02:00
Otavio Salvador
e972d72bd7 imx: Use a clear identification of an unidentified CPU type
In case an unidentified CPU type is detected it now returns
i.MX??, in a const char.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:16 +02:00
Markus Hubig
a3dab5d1d9 Enable the EMAC clock in at91_macb_hw_init().
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 14:58:15 +02:00
Bo Shen
f7fa2f3740 arm : Atmel : add at91sam9x5ek board support
Add at91sam9x5ek board support, this board support the following SoCs
  AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01 14:58:14 +02:00
Laurence Withers
be7d257895 DaVinci DA8xx: fix set_cpu_clk_info()
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:

  [...snip...]
  ARM frequency = 300 MHz
  DSP frequency = -536870913 MHz
  DDR frequency = 300 MHz

This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Hadli, Manjunath <manjunath.hadli@ti.com>
Cc: Heiko Schocher <hs@denx.de>
2012-09-01 14:58:14 +02:00
Laurence Withers
de9d2e3d60 DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
2012-09-01 14:58:14 +02:00
Laurence Withers
88ac6b9d14 DaVinci DA850: UART2 clock ID comes from ASYNC3
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
2012-09-01 14:58:14 +02:00
Laurence Withers
8a54aa0da7 DaVinci DA8xx: tidy up clock ID definition
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Marek Vasut
308252adaf dm: Move OMAP GPIO driver to drivers/gpio/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
db7dd8109c am33xx: Rework pinmux functions
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
  - Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
726c05d2cf am33xx evm: Add CONFIG_CMD_EEPROM and related
am33xx boards have at least one eeprom and in the case of beaglebones
with capes, more.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
65d750be59 am33xx: Add support for TI AM335x StarterKit EVM
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
  config_ddr with.
- Both of the above require filling in the header structure early, move
  it into the data section.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
973b663820 am33xx: Remove board/ti/am335x/evm.c
The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards.  As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
d4898ea896 am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
318f27c98f am33xx: Rework config_ddr to make DDR3 support easier.
In order to support DDR3 as well as DDR2, we need to perform the same
init sequence, but with different values.  So change config_ddr() to
toggle setting pointers/etc for what DDR2 wants, and then calling.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
942d3f0174 am33xx: Move some variables in emif4.c, mark them static.
We need vtpreg and ddrctrl but no longer need a second ddrregs.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
a74f0c7cb5 am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported).  Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove.  Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there.  Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:13 +02:00
Tom Rini
82afcc9efd am33xx: Do not touch 'ratio1' fields
The various ratio1 fields are not documented in any of the documentation
I can find.  Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
5ac3b7ada1 am33xx: Rework config_io_ctrl slightly
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation).  Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
ff7ec0f945 am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
87a1acbb69 am33xx: Turn a number of 'int' functions to 'void'
A number of memory initalization functions were int and always returned
0.  Further it's not feasible to be doing error checking here, so simply
turn them into void functions.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
c48c895433 am33xx: Document what we're doing with ddrctrl->ddrckectrl
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
  we're operating in the normal mode where EMIF/PHY clock is controlled
  by the PHY.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Vaibhav Bedia
7d8a961d31 am335x: ddr_defs: Update EMIF parameters
EMIF parameters are calculated based on the AC timing
parameters from the SDRAM datasheet and the DDR frequency.

Current values for these paramters in AM335x U-Boot code,
though reliable, are not fully optimal. The most optimal
settings can be derived based on the guidelines published
at [1]. A pre-computed set of values with the most optimum
settings for AM335x EVM and BeagleBone can be found at [2].

[1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
[2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
c8da4a587c am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
b971dfad6a am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value.  This call can be delayed
slightly to the point where we know which type of memory we have.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
fda35eb982 am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()).  For now, pass in
the value of DDR2.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
bce58fece5 am33xx: Make config_cmd_ctrl / config_ddr_data take const structs
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const.  This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
10e7e36daf am33xx: Rework DDR2 EMIF initalization slightly
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
372f11f58d am33xx: Bugfix to config_sdram()
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
13f1c44bc5 am33xx: Remove extra check in enable_ddr_clocks
We do not need to check for EMIF_GCLK and L3_GCLK being active.  This
was a hold-over from bringup and no longer required.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:12 +02:00
Tom Rini
7d5eb34908 am33xx: Convert to using <asm/emif.h> to describe the EMIF
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Tom Rini
79b3e6b75b am33xx: Remove DMM_BASE define
The am33xx does not have a DMM, so don't define the base.

Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Tom Rini
a438c756b6 am33xx: Enable gpio0 clock
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01 14:58:11 +02:00
Javier Martinez Canillas
41708a5db4 OMAP3: mem: Add Numonyx OneNAND 200MHz timing information
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
2012-09-01 14:58:11 +02:00
Chandan Nath
89017e150e am33xx: pin mux defintions for CPSW switch
This patch adds pin mux settings for CPSW switch found on
TI AM335X based boards (MII and RGMII modes).

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split pinmux into separate patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-09-01 14:58:11 +02:00
Chandan Nath
e79cd8eb9b am33xx: CPSW init and definitions
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-09-01 14:58:11 +02:00
Mikhail Kshevetskiy
680866a502 arm/davinci/da850: add uart0 pinmux
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>
2012-09-01 14:58:10 +02:00
Mikhail Kshevetskiy
89473d233f arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
2012-09-01 14:58:10 +02:00
Albert ARIBAUD
c50afc1dab Revert "arm: armv7: add compile option -mno-unaligned-access if available"
This reverts commit 5347560f5427bcdd48a563b62180481606ac8044,
which was applied only to get release 2012.07 functional on as
many ARM targets as possible despite mis-aligned accesses.
2012-09-01 14:58:10 +02:00
Steve Sakoman
d3decdebde omap: am335x_evm: enable i2c1 channel
This patch sets up pinmux, enables fclk, and
defines CONFIG_I2C_MULTI_BUS

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-09-01 14:58:10 +02:00
Lad, Prabhakar
0d986e61e2 da850/omap-l138: Add support to read u-boot image from MMC/SD
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.

Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.

Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
2012-09-01 14:58:09 +02:00
Lad, Prabhakar
560e69bf6a arm, davinci: perform check for initializing global data and serial init
initialize baudrate, flags, data and serial initialization,
only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined.

Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
2012-09-01 14:58:09 +02:00
Lad, Prabhakar
ecc98ec18c da850/omap-l138: Add MMC support for DA850/OMAP-L138
This patch adds support for MMC/SD on DA850/OMAP-L138.

Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
2012-09-01 14:58:09 +02:00
Steve Sakoman
3b97152b63 omap: am33xx: enable gpio support
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.

It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-09-01 14:58:09 +02:00
Stefan Roese
0044c42e94 Consolidate bootcount code into drivers/bootcount
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-09-01 14:26:02 +02:00
Anatolij Gustschin
d7903ae159 mpc5xxx: add GPIO port configuration
Add posibility for board specifig GPIO configurations using
various CONFIG_SYS_ macros.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2012-09-01 14:19:52 +02:00
Daniel Schwierzeck
0efcdb15f9 MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefiles
Prepare for upcoming MIPS64 CPU support.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-08-24 00:34:47 +02:00
Daniel Schwierzeck
2c0e3de384 MIPS: factor out endianess flag handling to arch config.mk
This is CPU independent and should be configured architecture-wide.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-08-24 00:34:43 +02:00
Andy Fleming
98ae9ac434 Revert "powerpc: Fix declaration type for I/O functions"
This reverts commit 20959471b5.
2012-08-23 12:16:57 -05:00
Scott Wood
3ea21536d7 powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:57 -05:00
York Sun
7ac3cc20e0 powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.h
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
1d083ff2c4 powerpc/mpc8xxx DDR: Fix interactive DDR debugging
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
62f739fe46 powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
7e4db27ffd powerpc/mpc8xxx DDR: Fix CAS latency calculation
Empty slot should be skipped when calculating CAS latency.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:56 -05:00
York Sun
45064adcae powerpc/mpc8xxx: Fix bug for extended DDR timing
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
a4c66509f1 powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
fcea30688f powerpc/mpc8xxx: Add support for cas latency 12 and above
Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
73b5396b25 powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
744713a6a3 powerpc/mpc85xx: Skip zero values for DDR debug registers
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.

Also add debug messages for workarounds and debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
York Sun
709389b654 powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
ffdf8890ae Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
50d96e95b4 Add IFC offset for DPAA/Corenet platforms
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:55 -05:00
Kumar Gala
5b6b85ae63 Add e6500 processor detection
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
123bd96d53 powerpc/mpc8xxx: use topology registers to calculate number of cores
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
York Sun
1ca8690d27 powerpc/mpc8xxx: Add immap for topology and rcpm registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
3854173aa8 powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.

So add IFC LAW target ID support for High-End SoC or corenet SoC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Prabhakar Kushwaha
e4879afba3 powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
33eee330cc powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.

To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.

The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.

We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline.  It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.

Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that.  We make it guarded so that we should never
see a speculative load, and we never do an explicit load.  Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward.  Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.

NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum.  This is the responsibility
of the OS that sets up PAMU.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Scott Wood
3e978f5dc8 powerpc/fsl-corenet: remove dead variant symbols
These are not supported as individual build targets, but instead
are supported by another target.

The dead p4040 defines in particular had bitrotted significantly.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
Timur Tabi
99abf7ded3 powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Matthew McClintock
9c6b47d53e p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
York Sun
be7bebeac2 powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Liu Gang
b5f7c8732a powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:15 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Liu Gang
ff65f12699 powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
York Sun
57125f222e powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.

Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:

fsl_cpu_a011:disable

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:13 -05:00
Joakim Tjernlund
7de8a7169e powerpc: Stack Pointer not properly aligned
The code first aligns the SP to 16 then subtract 8, making it
8 bytes aligned. Furthermore the initial stack frame not
quite correct either.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Joakim Tjernlund
89f4289958 mpc85xx: Initial SP alignment is wrong.
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Nobuhiro Iwamatsu
31d4fe8d40 sh: tmu: Removed arch/sh/include/asm/clk.h
asm/clk.h was included get_peripheral_clk_rate function. But this
is not used from anywhere.
This removed asm/clk.h, and deleted include line from arch/sh/lib/time.c

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-08-21 15:00:34 +09:00
Nobuhiro Iwamatsu
d4430426b6 sh: tmu: Changed switch statement to shift operation
Calculation of the bit position using switch statement can substitute
shift operation using ffs.
And removed unsed macro and variable.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-08-21 15:00:34 +09:00
Nobuhiro Iwamatsu
73f35e0b15 sh: tmu: Changed TMU driver using array of structures
This changed into access using array of structure from access to the register
using the definition of the register by macro.
And removed white space.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-08-21 15:00:33 +09:00
Marek Vasut
d2aa5dca74 dm: mips: Import libgcc components from Linux
Import ashldr3, ashrdi3 and lshrdi3 to squash possible libgcc fp mismatch,
resulting in the following warning:

mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_lshrdi3.o) uses hard float, u-boot uses soft float
mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_ashldi3.o) uses hard float, u-boot uses soft float

Imported from Linux (linux-next 20120723) as of commit:

commit 72fbfb260197a52c2bc2583f3e8f15d261d0f924
Author: Ralf Baechle <ralf@linux-mips.org>
Date:   Wed Jun 7 13:25:37 2006 +0100

    [MIPS] Fix optimization for size build.

    It took a while longer than on other architectures but gcc has finally
    started to strike us as well ...

    This also fixes the damage by 6edfba1b33c701108717f4e036320fc39abe1912.

    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
[<daniel.schwierzeck@gmail.com>: removed USE_PRIVATE_LIBGCC = yes]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2012-08-17 20:13:48 +02:00
Marek Vasut
8b82cefbfc dm: mips: Fix lb60 timer code
The timer code contains more halfword writes which trigger gcc errors.
The registers are again 32bit, yet written by 16bit writes, fix this:

timer.c: In function ‘reset_timer_masked’:
timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c: In function ‘get_timer_masked’:
timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c: In function ‘timer_init’:
timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2012-08-17 20:13:48 +02:00
Marek Vasut
36d0a42b68 dm: mips: Fix lb60 WDT control
Write the TSCR register via 32bit write instead of 16bit one.
The register is 32bit wide and bit 16 is being set, triggering
gcc overflow error and making the code broken.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2012-08-17 20:13:48 +02:00
Mike Frysinger
11a05fbde7 nds32: fix unused pmu_init warning
Fixes the build-time warning:
	board.c: At top level:
	board.c:106: warning: 'pmu_init' defined but not used

This makes the ifdef logic at the call site match the logic at the
function definition.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-11 00:43:28 +08:00
Mike Frysinger
782ff0cd87 nds32: delete unused local variable
Fixes the build-time warning:
	board.c: In function 'board_init_r':
	board.c:304: warning: unused variable 's'

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-11 00:43:28 +08:00
Mike Frysinger
38230ee7bb nds32: drop bi_enetaddr from global data
Nothing is using this, so punt it from the gd.  Seems to just be a copy
& paste wart from the initial port.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-11 00:43:28 +08:00
Julius Baxter
3874a37745 openrisc: Work around potential relocation issues
When reset code is in flash, the jump instructions emitted by the
compiler are relative instead of absolute jumps.

A fix to the reset code to make correct jumps to the beginning of
code relocated to RAM have also been added.

Signed-off-by: Julius Baxter <juliusbaxter@gmail.com>
2012-08-09 23:37:45 +02:00
Prabhakar Kushwaha
20959471b5 powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.

Chage protoype declaration as static.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:24:31 +02:00
Prabhakar Kushwaha
a16a5cccfb powerpc:Fix return type & parameter passed for I/O functions
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32

Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-08-09 22:23:14 +02:00
Mike Frysinger
47fde91f0c global_data: unify global flag defines
All the global flag defines are the same across all arches.  So unify them
in one place, and add a simple way for arches to extend for their needs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-08-09 21:46:32 +02:00
Wolfgang Denk
1d56f63dab Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
  powerpc/mpc85xx: Ignore E bit for BSC9130/1
  powerpc/sgmii: To support PHY link state auto detect in SGMII mode
  powerpc/85xx: improve definition of BR_PHYS_ADDR macro
  powerpc/p2041: configure the CPLD lane_mux according to RCW
  powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
  powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
  powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
  powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
  powerpc/p1022ds: add support for SPI and SD boot

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-08-09 21:04:05 +02:00
Timur Tabi
5c5befda58 powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for.  The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
York Sun
718f2b3187 powerpc/mpc85xx: Ignore E bit for BSC9130/1
Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply
timing. Remove them now.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
Timur Tabi
7ee411071f powerpc/85xx: improve definition of BR_PHYS_ADDR macro
The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:15 -05:00
Shaohui Xie
98de369b1c powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:38 -05:00
York Sun
535a159ab6 powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:38 -05:00
Yoshihiro Shimoda
d185857267 sh: modify checkcpu() for SH-4A
Even if using CPU is SH-4A, the previous code always put "SH4".
This patch fixes it.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-08-08 09:50:41 +09:00
Wolfgang Denk
948fa1713c Merge branch 'master' of git://git.denx.de/u-boot-i2c
* 'master' of git://git.denx.de/u-boot-i2c:
  km/common: remove printfs for i2c deblocking code
  CONFIG: SMDK5250: I2C: Enable I2C
  I2C: Add support for Multi channel
  I2C: Modify the I2C driver for EXYNOS5
  I2C: Move struct s3c24x0_i2c to a common place.
  EXYNOS: PINMUX: Add pinmux support for I2C
  EXYNOS5: define EXYNOS5_I2C_SPACING
  EXYNOS: Add I2C base address.
  EXYNOS: CLK: Add i2c clock
  mx6qsabrelite: add i2c multi-bus support
  imx-common: add i2c.c for bus recovery support
  i.mx53: add definition for I2C3_BASE_ADDR
  i.mx: iomux-v3.c: move to imx-common directory
  i.mx: iomux-v3.h: move to imx-common include directory
  iomux-v3: remove include of mx6x_pins.h
  mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support
  mxc_i2c: add bus recovery support
  mxc_i2c: prep work for multiple busses support
  mxc_i2c: add i2c_regs argument to i2c_imx_stop
  mxc_i2c: add retries
  mxc_i2c: check for arbitration lost
  mxc_i2c: change slave addr if conflicts with destination.
  mxc_i2c: don't disable controller after every transaction
  mxc_i2c: place i2c_reset code inline
  mxc_i2c: place imx_start code inline
  mxc_i2c: remove redundant read
  mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state
  mxc_i2c.c: code i2c_probe as a 0 length i2c_write
  mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write
  mxc_i2c: create i2c_init_transfer
  mxc_i2c: clear i2sr before waiting for bit
  mxc_i2c: create tx_byte function
  mxc_i2c: remove ifdef of CONFIG_HARD_I2C
  mxc_i2c: fix i2c_imx_stop
  i2c: deblock i2c bus also if accessed before realocation

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-31 22:07:42 +02:00
Wolfgang Denk
d978780b2e Merge branch 'master' of git://git.denx.de/u-boot-microblaze
* 'master' of git://git.denx.de/u-boot-microblaze:
  microblaze: Wire up SPI driver
  spi: microblaze: Adds driver for Xilinx SPI controller
  microblaze: intc: Clear interrupt code
  microblaze: Call serial multi initialization
  microblaze: Move __udelay implementation
  microblaze: Remove extern from board.c
  microblaze: Wire up dts configuration
  fdt: Add board specific dts inclusion
  microblaze: Move individual board linker scripts to common script in cpu tree.
  microblaze: Add gpio.h
  microblaze: Add missing undefs for UBI and UBIFS
  microblaze: Expand and correct configuration comments
  microblaze: Enable ubi support
  microblaze: Avoid compile error on systems without cfi flash
  microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION

Conflicts:
	drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-31 22:01:08 +02:00
Rajeshwari Shinde
91dffb16ff I2C: Move struct s3c24x0_i2c to a common place.
struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:02:41 +02:00
Rajeshwari Shinde
c65c05f57f EXYNOS: PINMUX: Add pinmux support for I2C
This patch adds pinmux code for I2C.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:02:28 +02:00
Rajeshwari Shinde
8da3eb1b22 EXYNOS5: define EXYNOS5_I2C_SPACING
This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel
base address.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:02:07 +02:00
Rajeshwari Shinde
1a758aec3d EXYNOS: Add I2C base address.
This patch adds the base address for I2C.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:01:56 +02:00
Rajeshwari Shinde
989feb8c52 EXYNOS: CLK: Add i2c clock
This adds i2c clock information for EXYNOS5.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-31 08:01:32 +02:00
Troy Kisky
cc54a0f7cc imx-common: add i2c.c for bus recovery support
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:57 +02:00
Troy Kisky
df369dcdb0 i.mx53: add definition for I2C3_BASE_ADDR
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:44 +02:00
Troy Kisky
18c0ad27c1 i.mx: iomux-v3.c: move to imx-common directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:32 +02:00
Troy Kisky
af2a35fb1f i.mx: iomux-v3.h: move to imx-common include directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:19 +02:00
Troy Kisky
d3394ec198 iomux-v3: remove include of mx6x_pins.h
This include is not needed.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31 07:59:56 +02:00
Wolfgang Denk
b98b611502 Merge branch 'next' of git://git.denx.de/u-boot
* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-30 20:39:52 +02:00
Marek Vasut
15ae8a31ca MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Subject slightly changed.
Signed-off-by: Wolfgang Denk <wd@denx.de>

Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and
TQM860LDB0A3-T50.202 (MPC860T at 50MHz).

Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2012-07-30 09:58:02 +02:00
Wolfgang Denk
00d8f4cd82 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM1136: Fix cache range checks
  mx6: Make pad name macro consistent with the datasheet
  mx28: Fix elftosb source link in README.mx28_common
  doc: README.mx28_common: Add missing entry into Contents

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-22 00:10:39 +02:00
Stefano Babic
569fadcd74 MPC83xx, MPC85xx: compile stub cache function
An empty flush_dcache_range() was added into MPC83xx and MPC85xx to
work with drivers shared with other architecture.  However, it is
compiled only if USB is set, but it is required for other drivers
(FSL_ESDHC), too.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Andy Fleming <afleming@gmail.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Marek Vasut <marex@denx.de>
CC: Wolfgang Denk <wd@denx.de>

Added MPC83xx version.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-21 23:37:48 +02:00
Benoît Thébaudeau
f8f09dd404 ARM1136: Fix cache range checks
bad_cache_range actually returned true if the range was OK, but it was used
according to its name, which resulted in all valid dcache range invalidate/flush
operations being dropped. Hence, most DMA transfers resulted in garbage data.

This patch renames this function according to what it does, and it fixes the
interpretation of its return value by other functions. The chosen naming is the
same as for ARM926EJ-S in order to be consistent.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-21 23:24:25 +02:00
Ashok
6b8ac524e7 mx6: Make pad name macro consistent with the datasheet
Use the same name as defined in the datasheet.
DSP_CLK -> DISP_CLK

Signed-off-by: Ashok Kumar Reddy Kourla <ashokkourla2000@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-20 23:03:28 +02:00
Wolfgang Denk
c2b3dcc24d Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependency
  ARM: OMAP4: PANDA: Add rest of the USB module pads to essentials
  arm: armv7: add compile option -mno-unaligned-access if available
  arm: Fix to mistake clean the memory space

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-20 22:38:32 +02:00
Macpaul Lin
8d732840ba nds32: split common cache access from cpu into lib
This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
 - dcache_flush_rang -> flush_dcache_rang
 - icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range

Signed-off-by: Macpaul Lin <macpaul@gmail.com>
2012-07-20 23:55:52 +08:00
Fabio Estevam
a21c65115b ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependency
Create a weak-aliased arch_cpu_init, so that we can get rid of CONFIG_ARCH_CPU_INIT
and always call arch_cpu_init.

This way we do not need to define CONFIG_ARCH_CPU_INIT in every board file, since
arch_cpu_init() is supposed to handle common CPU level code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-20 14:24:08 +02:00
Tetsuyuki Kobayashi
5eb497429e arm: armv7: add compile option -mno-unaligned-access if available
Recent compiler generates unaligned memory access in armv7 default.
But current U-Boot does not allow unaligned memory access, so it causes
data abort exception.
This patch add compile option "-mno-unaligned-access" if it is available.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Gary Thomas <gary@mlbassoc.com>
2012-07-20 14:24:08 +02:00
Zhong Hongbo
448217d4b2 arm: Fix to mistake clean the memory space
In currently, when __bss_start is equal to __bss_end__,
The bss loop will clear all the things in memory space.

But just only when __bss_end__ greater than __bss_start__,
we do the clear bss section operation.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-07-20 14:24:08 +02:00
Troy Kisky
de6f604de2 mxc_i2c: specify i2c base address in config file
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11 10:54:29 +02:00
Michal Simek
575a3d21f6 microblaze: intc: Clear interrupt code
Clear and prepare for device-tree driven configuration.
Remove CONFIG_SYS_INTC_0 definition
Use dynamic allocation instead of static.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-10 11:54:06 +02:00
Michal Simek
e0bb305df8 microblaze: Call serial multi initialization
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-10 11:54:06 +02:00
Michal Simek
779bf42c2a microblaze: Move __udelay implementation
Move __udelay to the timer code because of unification.
And clean coding style because of checkpatch.pl.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-10 11:54:06 +02:00
Michal Simek
36c7e6efb3 microblaze: Remove extern from board.c
eth_init() is defined at include/net.h.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Simon Glass <sjg@chromium.org>
2012-07-10 11:54:06 +02:00
Wolfgang Denk
895f3e0542 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  tegra: define fdt_load/fdt_high variables
  tegra: enable bootz command
  tegra: usb: Fix device enumeration problem of USB1
  tegra: trimslice: set up serial flash pinmux
  tegra: add pin_mux_spi() board initialization function
  tegra: add GMC/GMD funcmux entry for SFLASH
  tegra: bootcmd: start USB only when needed
  tegra: bootcmd enhancements
  tegra: add enterrcm command
  tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG
  Add env vars describing U-Boot target board
  tegra: usb: fix wrong error check
  tegra: add ULPI on USB2 funcmux entry
  tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches
  tegra: Add Tamonten Evaluation Carrier support
  tegra: Use SD write-protect GPIO on Tamonten
  tegra: Implement gpio_early_init() on Tamonten
  tegra: Allow boards to perform early GPIO setup
  tegra: plutux: Add device tree support
  tegra: medcom: Add device tree support
  tegra: Rework Tamonten support
  beagle: add eeprom expansion board info for bct brettl4

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-10 08:54:41 +02:00
Rajeshwari Shinde
30704dae46 EXYNOS: Fix USB compiler warning
Fixed the compiler warning message.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-10 08:50:05 +02:00
Wolfgang Denk
ba662f8998 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250
  EXYNOS5: USB: Fix incorrect USB base addresses
  EXYNOS: Add power Enable/Disable for USB-EHCI
  USB: EXYNOS: Set USB 2.0 HOST Link mode
  EXYNOS5: Add structure for PMU registers
  EXYNOS5: Fix system register structure
  USB: EXYNOS: Incorporate EHCI review comments

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-09 23:59:00 +02:00
Jim Lin
8b3f7bf7ec tegra: usb: Fix device enumeration problem of USB1
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.

Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:34 +02:00
Stephen Warren
a016e144ed tegra: add GMC/GMD funcmux entry for SFLASH
This is used on TrimSlice.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Stephen Warren
9cd3f3adf0 tegra: add enterrcm command
Tegra's boot ROM supports a mode whereby code may be downloaded and flash
programmed over a USB connection. On dev boards, this is typically entered
by holding down a "force recovery" button and resetting the CPU. However,
not all boards have such a button (one example is the Compulab Trimslice),
so a method to enter RCM from software is useful.

This change implements the command "enterrcm" to do this, and enables it
for all Tegra boards by default. Even on boards other than Trimslice,
controlling this over a UART may be useful, e.g. to allow simple remote
control without the need for mechanical button actuators, or hooking up
relays/... to the button.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Lucas Stach
f857fff606 tegra: usb: fix wrong error check
loop_count runs down from 10000, so the correct condition to error out
is ==0.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren.nvidia@gmail.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Lucas Stach
f97daaa231 tegra: add ULPI on USB2 funcmux entry
This is needed as a prerequisite for Tegra USB ULPI support
within U-Boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-09 22:44:33 +02:00
Rajeshwari Shinde
86d74d0339 EXYNOS5: USB: Fix incorrect USB base addresses
This patch corrects the base addresses for USB_PHY and USB_OTG.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2012-07-09 18:27:55 +02:00
Rajeshwari Shinde
c48ac11322 EXYNOS: Add power Enable/Disable for USB-EHCI
This patch adds functions to enable/disable the power of USB
host controller for EXYNOS5.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2012-07-09 18:27:55 +02:00
Rajeshwari Shinde
71045da812 USB: EXYNOS: Set USB 2.0 HOST Link mode
This patch adds a function to set usb host mode to USB 2.0 HOST Link
for EXYNOS5

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2012-07-09 18:27:55 +02:00
Rajeshwari Shinde
f9c4e04be7 EXYNOS5: Add structure for PMU registers
This patch adds power mananagement registers structure for exynos5 SoC.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2012-07-09 18:27:55 +02:00
Rajeshwari Shinde
775b6f728d EXYNOS5: Fix system register structure
This patch corrects the SYSREG structure.
We have removed the sysreg.h added in the previous patchset
version as the sysreg structure is already defined in system.h.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2012-07-09 18:27:54 +02:00
Rajeshwari Shinde
7590d3cece USB: EXYNOS: Incorporate EHCI review comments
This patch incorates the review comments given by Minkyu Kang for
EHCI support on EXYNOS

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2012-07-09 18:27:54 +02:00
Michal Simek
2e65b44c0f microblaze: Move individual board linker scripts to common script in cpu tree.
Unification for all microblaze boards.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-07-09 10:44:27 +02:00
Michal Simek
d6afd6867c microblaze: Add gpio.h
Gpio support is not implemented yet. Adding it because of fdtdec.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2012-07-09 10:44:26 +02:00
Wolfgang Denk
18277f7057 Revert "arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0"
This reverts commit fa042186b9.
It causes build warnings like this:
cpu.c:48:1: warning: -fstack-usage not supported for this target
[enabled by default]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-09 09:19:00 +02:00
Wolfgang Denk
50cd93b250 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-08 19:26:33 +02:00
Wolfgang Denk
8246ff864d Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-08 19:16:14 +02:00
SRICHARAN R
d702b0811d ARM: cache: Move the cp15 CR register read before flushing the cache.
The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c

int cleanup_before_linux(void)
{
 ...
 ...
 dcache_disable();
 v7_outer_cache_disable();
 invalidate_dcache_all();
}

 1) invalidate_dcache_all call expects that all the caches has been
 flushed, invalidated and there are no dirty entries prior to its
 execution.  In the above sequence dcache_disable() flushes, invalidates
 the caches and turns off the  mmu. But after it cleanups the cache
 and before the mmu is disabled  there is a cp_delay() function which
 has STR instruction. On certain cores like the cortex-a15, cache hit
 and a write can happen to a cache line even when the dcache is
 disabled. So the above mentioned STR instruction creates a dirty entry
 after cleaning. The mmu gets disabled after this.

 2) invalidate_dcache_all invalidates the cache lines. Again on
 cores like cortex-a15, invalidate instruction flushes the dirty
 line as well. So some times the dirty line from sequence 1
 can corrupt the memory resulting in a crash.

 Fixing this by moving the get_cr() and cp_delay() calls before
 cleaning up the cache, thus avoiding the dirty entry.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:44 +02:00
Fabio Estevam
d519b4bc0a ARM: introduce arch_early_init_r()
Introduce arch_early_init_r() function, which can be useful for doing
early initialization after relocation has happened.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:44 +02:00
Fabio Estevam
c27c07b86b ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
No need to define CONFIG_ARCH_CPU_INIT.

All mx28 based boards should use arch_cpu_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:44 +02:00
Fabio Estevam
5427d29c26 No need to define CONFIG_ARCH_CPU_INIT.
All mx6 based boards should use arch_cpu_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:44 +02:00
Stefan Roese
4ae8bc4392 SPL: ARM: spear: Add SPL support for SPEAr600 platform
This patch adds SPL support for SPEAr600. Currently only SNOR
(Serial NOR) flash support is included. Other boot devices
(NAND, MMC, USB ...) may be added with later patches.

Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
2012-07-07 14:07:43 +02:00
Simon Glass
fe901f2d9b arm: Don't use printf() in SPL builds
raise() likes to call printf() if it is available, but in SPL builds it
either is not available, or adds a large chunk to the resulting image
size.

So don't call it even if it is available.

This change reduces SPL size from 10KB to 6.3KB on hawkboard, for
example, using generic relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:43 +02:00
Stefan Roese
2cb06a4fda GPIO: Add SPEAr GPIO driver
Tested on x600 (SPEAr600).

Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:42 +02:00
Amit Virdi
bc0bdf4c22 cleanup/SPEAr: Remove unnecessary parenthesis
In SPEAr configuration files, unnecessary paranthesis are used in some
\#defines. Remove them as they serve no purpose

Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:42 +02:00
Shiraz Hashim
f28e5c946d SPEAr: Correct SoC ID offset in misc configuration space
SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:42 +02:00
Shiraz Hashim
7c885a0e55 SPEAr: explicitly select clk src for UART
UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:42 +02:00
Vipin KUMAR
962d026b6a SPEAr: Add basic arch related support for SPEAr SoCs
Earlier, architecture specific init code was mixed with board initialization
code in board/spear/... This patch updates architecture support for SPEAr in
latest u-boot and prints the SoC information.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:40 +02:00
Vipin KUMAR
8eb0ee6a64 SPEAr: Add macb driver support for spear310 and spear320
SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The
driver for this device is already supported by u-boot, so configuring
board configuration file and defining base addresses etc to make use
of the common driver

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:40 +02:00
Vipin KUMAR
deb0056227 SPEAr: Configure network support for spear SoCs
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:40 +02:00
Amit Virdi
70fdbefc6c SPEAr: Eliminate dependency on Xloader table
Xloader table was used primarily to inform u-boot about the DDR size. However,
now the ddr size is calculated at runtime which eliminates any need for the
Xloader table. So removing this unnecessary code.

Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:40 +02:00
Vipin KUMAR
f3fcf92d59 st_smi: Add support for SPEAr SMI driver
SMI is the serial memory interface controller provided by ST.

Earlier, a driver exists in the u-boot source code for the SMI IP. However, it
was specific to spear platforms. This commit converts the same driver to a more
generic driver. As a result, the driver files are renamed to st_smi.c and
st_smi.h and moved into drivers/mtd folder for reusability by other platforms
using smi controller peripheral.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:38 +02:00
Vipin KUMAR
0def98e7be mtd/NAND: Remove obsolete SPEAr specific NAND drivers
Since, SPEAr platform uses generic FSMC driver now, so spear specific files
drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are
removed

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2012-07-07 14:07:38 +02:00
Vipin KUMAR
1fa943b99d SPEAr: Configure FSMC driver for NAND interface
Since FSMC is a standard IP and it supports different memory interfaces, it
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2012-07-07 14:07:38 +02:00
Tetsuyuki Kobayashi
fa042186b9 arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:36 +02:00
SRICHARAN R
5e9cd44ca0 ARM: OMAP4/5: Move USB clocks to essential group.
USB clocks will be required for fastboot, tftp
related functionalities. Move these clocks to
essential group inorder to have the functionality
working when non-essential clocks are not enabled.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:36 +02:00
SRICHARAN R
dbf8fb6ad1 ARM: OMAP4/5: Move gpmc clocks to essential group.
GPMC clocks are currently getting enabled as a part
non-essential clocks. This will be required during
NOR boot. Move this to essential group to keep the
functionality, when non-essential clocks are not
enabled.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:36 +02:00
SRICHARAN R
254763822e ARM: OMAP4+: Move external phy initialisations to arch specific place.
The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:35 +02:00
Sebastien Jan
cc009defa4 omap4: Use a smaller M,N couple for IVA DPLL
This reduced M,N couple corresponds to the advised value from
TI HW team.

Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.

Signed-off-by: Sebastien Jan <s-jan@ti.com>
2012-07-07 14:07:35 +02:00
Steve Sakoman
f2b37a6533 omap: am33xx: accomodate input clocks other than 24 Mhz
The PLL setup values currently assume a 24 Mhz input clock.

This patch uses V_OSCK from the board config file to support boards
with different input clock rates.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-07-07 14:07:35 +02:00
Steve Sakoman
ad0878a749 omap: emif: fix bug in manufacturer code test
Code currently tests for <= 0xff.  Micron manufacturer code is 0xff, so
Micron memory will not be detected!

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-07-07 14:07:35 +02:00
Steve Sakoman
55c1284942 omap: emif: deal with rams that return duplicate mr data on all byte lanes
Some rams (Micron for example) return duplicate mr data on all byte lanes.

Users of the get_mr function currently don't deal with this duplicated
data gracefully.  This patch detects the duplicated data and returns only
the expected 8 bit mr data.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
2012-07-07 14:07:35 +02:00
Lokesh Vutla
38f25b125e OMAP4+: Force DDR in self-refresh after warm reset
Errata ID:i727

Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.

Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.

This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
2012-07-07 14:07:35 +02:00
Lokesh Vutla
784229cc25 OMAP4+: Handle sdram init after warm reset
EMIF and DDR device state are preserved in warmreset.  Redoing the full
initialisation would cause unexpected behaviour.  Do only partial
initialisation to account for frequency change.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
2012-07-07 14:07:34 +02:00
Lokesh Vutla
702395073f ARM: OMAP3+: Detect reset type
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.

This will be used to skip the module configurations
that are retained across a warm reset.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:34 +02:00
Tetsuyuki Kobayashi
f8b9d1d30e arm: bugfix: Move vector table before jumping relocated code
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:33 +02:00
Valentin Longchamp
dacc8c6f79 arm/kirkwood: protect the ENV_SPI #defines
So that they can be redefined by some boards specific values.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2012-07-07 14:07:33 +02:00
Valentin Longchamp
ac486e3ba1 kw_spi: support spi_claim/release_bus functions
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.

Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2012-07-07 14:07:32 +02:00
Valentin Longchamp
8f5d7a0398 kirkwood: add save functionality kirkwood_mpp_conf function
If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save  must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.

A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2012-07-07 14:07:31 +02:00
Bo Shen
2b3b1c668b ATMEL/PIO: Enable new feature of PIO on Atmel device
Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-07-07 14:07:30 +02:00
Michael Langer
5c23712dbd i.MX6 USDHC: Use the ESDHC clock
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.

MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).

Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-07 14:07:29 +02:00
Marek Vasut
e3ddc64603 i.MX28: Add function to adjust memory parameters
This function can be overridden at run-time and allows implementors
of new boards based on the i.MX28 chip to fine-tune the memory params.
It is possible to write into the dram_vals array because when the SPL
runs, it is located SRAM. Therefore the location is writable. There is
no possibility of these data to be read-only.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
2012-07-07 14:07:29 +02:00
Otavio Salvador
8b8d81047d MX28: Fix a typo in mx28_reg_8 macro
The macro mistakenly referred to 32bit struct instead of 8bit one.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:27 +02:00
Fabio Estevam
3f5f200bbe mx53: Fix mask for SATA reference clock
SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c.

Fix the mask for these bits.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:25 +02:00
Jason Liu
0d952e5d2e i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly
If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct

Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-07 14:07:25 +02:00
Rajeshwari Shinde
c5e3710a18 EXYNOS5: PINMUX: Added default pinumx settings
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-07-07 14:07:25 +02:00
Minkyu Kang
7775831dd3 Exynos: fix cpuinfo and cpu detecting
Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
2012-07-07 14:07:25 +02:00
SRICHARAN R
e423a8f76d ARM: OMAP4: Correct the lpddr2 io settings register value.
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.

Correcting the above settings here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
7fd5b9bfe4 OMAP5: Change voltages for omap5432
Change voltages for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
753bae8c5d OMAP5: DPLL core lock for OMAP5432
No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
784ab7c545 OMAP5: EMIF: Add support for DDR3 device
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
43037d7631 OMAP5: ADD precalculated timings for ddr3
Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Lokesh Vutla
eb4e18e89e OMAP5: Configure the io settings for omap5432 uevm board
This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Lokesh Vutla
0a0bf7b217 OMAP5: ADD chip detection for OMAP5432 SOC
This patch adds chip detection for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Lokesh Vutla
851bebd68c OMAP5: Adding correct Control id code for OMAP5430
Control id code for omap5430 ES1.0 is hard coded with a wrong value.
This patch corrects the value

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Tom Rini
65c206b688 am33xx: Fix i2c sampling rate typo
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2012-07-07 14:07:22 +02:00
Tom Rini
d88bc0425b am33xx: Fill in more cm_wkuppll / cm_perpll
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2012-07-07 14:07:22 +02:00
Tom Rini
fe4f97b98f am335x: Correct i2c sysc offset
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2012-07-07 14:07:22 +02:00
Troy Kisky
d5b069ecb4 DaVinci: fix ddr2 vtp i/o calibration
Previously, only the low 5 bits (NCH) were being transfered
from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed.

VTP_RECAL should be bit 15, not 18.

The only mainline board affected by this change is davinci_sonata.
The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT.

However, if the program that loads u-boot on these boards
copied the code from u-boot, they will need fixed as well.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Please get tested by acks before applying, where tested by
means an overnight memory test.

Thanks
Troy
2012-07-07 14:07:22 +02:00
SRICHARAN R
e843d0f7ee ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.
OMAP5 evm board has 2GB of memory. So correct the
macro to take in to account of the full dram size.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:22 +02:00
SRICHARAN R
41321fd4d6 ARM: OMAP5: Align memory used for testing to the power of 2
get_ram_size checks the given memory range for valid ram,
but expects the size of memory to be aligned to the power
of 2. In case of OMAP5 evm board the memory available is
2GB - 16MB(used for TRAP section) = 2032MB.

So always ensure that the size of memory used for testing is
aligned to the power of 2.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:22 +02:00
SRICHARAN R
77efdeb758 ARM: OMAP5: dmm: Create a tiler trap section.
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.

This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.

Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:22 +02:00
SRICHARAN R
e06e914d87 ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.
The DMM sections can be overlapping with each other, with
sections 3 to 0 having the highest to lowest priority in that
order. There could also be a section that is used trap the
unmapped Tiler entries and this trap section could be
overlapping with the actual sdram area.

So take care of the above scenarios while calculating the
size of the actual ram.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-07-07 14:07:21 +02:00
Tom Rini
2ab2810375 am33xx: Do not call init_timer twice
We do not need to call init_timer both in SPL and U-Boot itself, just
SPL needs to initialize the timer.

Signed-off-by: Tom Rini <trini@ti.com>
2012-07-07 14:07:21 +02:00
Tom Warren
76e350b7a3 arm: Tegra: Use ODMDATA from BCT in IRAM
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.

Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2012-07-07 14:07:21 +02:00
Tom Warren
52a8b82074 gpio: tegra2: rename tegra2_gpio.* to tegra_gpio.*
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:20 +02:00
Tom Warren
edffa63d3d spi: tegra2: rename tegra2_spi.* to tegra_spi.*
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:20 +02:00
amartin@nvidia.com
f3717ac584 tegra: override compiler flags for low level init code
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.

The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9.  While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:19 +02:00
Simon Glass
27c4a3318f tegra: Correct PLL access in ap20.c and clock.c
Correct this warning seen by Albert:

ap20.c:44:18: warning: array subscript is above array bounds

There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:19 +02:00
Stephen Warren
d1e4607901 tegra: add SDMMC1 on SDIO1 funcmux entry
This will be used on TrimSlice.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Lucas Stach
a2cfe63eeb tegra: add SDIO1 funcmux entry for UARTA
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry

v2: remove enum change

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Lucas Stach
ffec1eb9c7 tegra: sync SDIO1 pingroup enum name with TRM
Signed-off-by: Lucas Stach <dev@lynxeye.de>
CC: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Stephen Warren
e21649be56 tegra: add UART1 on GPU funcmux entry
TrimSlice uses UART1 on the GPU pingroup.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:18 +02:00
Stephen Warren
b9607e7061 tegra: add alternate UART1 funcmux entry
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-07-07 14:07:17 +02:00
Tom Warren
078078cfa9 spi: Tegra2: Seaboard: fix UART corruption during SPI transactions
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
2012-07-07 14:07:17 +02:00
York Sun
feae34243f powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
Fix SVR checking for commit acf3f8da.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
5e23ab0a31 powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
York Sun
1e9ea85f7d powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Timur Tabi
7b6e80538b lib/powerpc: addrmap_phys_to_virt() should return a pointer
addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.

The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-06 17:30:32 -05:00
Prabhakar Kushwaha
e87dc41fc1 powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.

Avoid updating these register.They will be programmed during NAND RAMBOOT.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:31 -05:00
Prabhakar Kushwaha
ad75d44239 powerpc/mpc85xx:Add debugger support for e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).

So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Please refer doc/README.mpc85xx for more information

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:31 -05:00
Prabhakar Kushwaha
d16a37b864 powerpc/85xx:Fix NAND code base to support debugger
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
689f00fc7e powerpc/85xx:Make debug exception vector accessible
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.

1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.

2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
5344f7a258 powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register

Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00
Prabhakar Kushwaha
19a8dbdc45 powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:03:25 -05:00
Timur Tabi
a6cdaa0cd1 powerpc/mpc83xx: fix copyright string in serdes.c
The misspelling of "semiconductor" causes some internal copyright analysis
tools to complain.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-07-03 11:07:21 -05:00
Tom Rini
26750c8aee CONFIG_SYS_BAUDRATE_TABLE: Add <config_fallbacks.h>, place there
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in <config_fallbacks.h> which mkconfig places after <configs/...h> in
the generated config file.  This is used when a board has not set its
own table.

Signed-off-by: Tom Rini <trini@ti.com>
2012-06-20 20:26:16 +02:00
Wolfgang Denk
fedab338f3 Merge branch 'master' of git://git.denx.de/u-boot-video
* 'master' of git://git.denx.de/u-boot-video:
  video: atmel/lcd: add LCD driver for new Atmel SoC
  video: cfb_console: flush dcache for frame buffer in DRAM
  cfb_console: Ignore bell character
  cfb_console: Add console_clear_line function
  cfb_console: Fix function console_back
  omap3_dss: cosmetic changes
  omap3_dss: add optional framebuffer
  mx53loco: Add LCD support
  mx5: Rename mx51_fb_init()
  mx53: Allow IPUv3 driver to also work on mx53
  mx51evk: Add LCD support
  EXYNOS: display 32bpp bitmap TIZEN logo
  create lib/tizen directory
  LCD: display 32bpp decompressed bitmap image
  common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
  common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
  common/lcd.c: use ARRAY_SIZE
  cmd_bmp.c: make bmp_display() usable by drivers or board code
  LCD: support another s6e8ax0 panel type
  LCD: change s6e8ax0 panel gamma value
  include/video.h: drop unused video_printf()

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-06-07 23:42:17 +02:00
Wolfgang Denk
74b5b5dbc3 Merge branch 'master' of git://git.denx.de/u-boot-avr32
* 'master' of git://git.denx.de/u-boot-avr32:
  avr32:board.c: fix compile warning
  avr32:grasshopper: fix PHY initialisation

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-06-07 23:41:03 +02:00
Wolfgang Denk
d1c6e9e44a Merge branch 'master' of git://git.denx.de/u-boot-mips
* 'master' of git://git.denx.de/u-boot-mips:
  MIPS: board.c: move extern declarations to u-boot-mips.h
  MIPS: bootm_qemu_mips.c: make checkpatch.pl clean
  MIPS: bootm.c: make checkpatch.pl clean

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-06-07 23:38:54 +02:00
Wolfgang Denk
76aef69e49 Merge branch 'master' of git://git.denx.de/u-boot-sh
* 'master' of git://git.denx.de/u-boot-sh:
  sh/ap_sh4a_4a: Fix typo of operator in ET0_ETXD4
  sh: Add SH7269 device and RSK2+SH7269 board
  sh: Set CONFIG_SH_ETHER_PHY_MODE and CONFIG_SH_ETHER_SH7734_MII to boards with sh_eth
  sh: Add support for AP-SH4A-4A board
  sh: Add register definition of PFC for SH7734
  sh: r0p7734: Add support I2C controller
  sh: Add bit control functions
  sh: Add support for r0p7734 board
  sh: Add support Renesas SH7734

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-06-07 23:34:11 +02:00
Marek Vasut
25315683fd MPC8xxx: Define cache ops for USB
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:

$ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
Configuring for MPC8572DS board...
make: *** [u-boot] Error 1
powerpc-linux-gnu-size: './u-boot': No such file
e1000.c: In function ‘e1000_initialize’:
e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
tsec.c: In function ‘tsec_initialize’:
tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1

--------------------- SUMMARY ----------------------------
Boards compiled: 1
Boards with errors: 1 ( MPC8572DS )
----------------------------------------------------------

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
2012-06-07 23:29:19 +02:00
Andreas Bießmann
d3a105a26f avr32:board.c: fix compile warning
This patch fixes following warning:

---8<---
board.c: In function 'board_init_r':
board.c:257: warning: unused variable 's'
--->8---

Patch de30122bb5 missed to remove this variable
too.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-06-04 09:21:34 +02:00
Daniel Schwierzeck
e034ea3b77 MIPS: board.c: move extern declarations to u-boot-mips.h
This fixes some remaining checkpatch.pl warnings.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-06-03 23:46:04 +02:00
Daniel Schwierzeck
ed53010441 MIPS: bootm_qemu_mips.c: make checkpatch.pl clean
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-06-03 23:46:04 +02:00
Daniel Schwierzeck
e51a6b7a6c MIPS: bootm.c: make checkpatch.pl clean
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-06-03 23:46:04 +02:00
Phil Edworthy
99744b7e34 sh: Add SH7269 device and RSK2+SH7269 board
This is an sh2a device (max 266MHz) with FPU, video display
controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports,
SD and on-chip USB.

The RSK2+SH7269 board uses the SH7269 processor. It is often
referred to as just rsk7269.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-05-28 09:12:54 +09:00
Nobuhiro Iwamatsu
4eb0b78e76 sh: Add register definition of PFC for SH7734
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-05-28 09:12:53 +09:00
Nobuhiro Iwamatsu
1379c51ea5 sh: Add bit control functions
This provide bit control functions as clrbits_*, setbits_* and
clrsetbits_*.

V2: Fix comment style and error of whitespace.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-05-28 09:12:53 +09:00
Nobuhiro Iwamatsu
2a57e7ec96 sh: Add support Renesas SH7734
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-05-28 09:12:53 +09:00
Jeroen Hofstee
8da2efb661 omap3_dss: cosmetic changes
Remove unnecessary brackets.
Unwrap lines which are below 80 chars.
Single line comment as single line (as the rest).
Moved init values to the source code.

cc: s-paulraj@ti.com
cc: khasim@ti.com
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
2012-05-25 15:35:25 +02:00
Jeroen Hofstee
d9c13aac14 omap3_dss: add optional framebuffer
The beagle board uses the background color to show an orange screen during
startup. This patch adds the ability to add a frame buffer, with the
intention not to break the beagle board use case (I don't have one).
videomodes.c is not used. Scrolling depends on this patch:

http://patchwork.ozlabs.org/patch/155662/

cc: trini@ti.com
cc: s-paulraj@ti.com
cc: khasim@ti.com
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
2012-05-25 15:34:18 +02:00
Fabio Estevam
fff6ef72b3 mx53: Allow IPUv3 driver to also work on mx53
Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and
mx53 SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-25 10:36:29 +02:00
Donghwa Lee
3d02408665 LCD: support another s6e8ax0 panel type
s6e8ax0 panel has many panel of types. This patch support another panel
on TIZEN lunchbox board(HWREVISION 2). This panel has reversed panel
display type. So, I had added necessary command.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2012-05-25 09:15:09 +02:00
Joe Hershberger
cb487f5664 net: cosmetic: Un-typedef Ethernet_t
Separate the Ethernet header from the 802 header.
Base the size constants on the structs.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 17:46:14 -05:00
Joe Hershberger
1735188329 net: Encapsulate CDP packet identification
Checking for CDP packets should be encapsulated, not copied code.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 14:19:23 -05:00
Joe Hershberger
10cbe3b6a4 net: Fix remaining API interface breakage
These are all the files which use the API incorrectly but did not get
built using MAKEALL -a powerpc|arm.  I have no compiler for them, but
the remaining issues should be far less than without this patch.

Any outstanding issues are left to the maintainers of boards that use
these drivers.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 14:19:21 -05:00
Joe Hershberger
7a10692a9c arch/powerpc/cpu/mpc8260/ether_scc.c: Fix compile warning
Fix this:
ether_scc.c: In function 'mpc82xx_scc_enet_initialize':
ether_scc.c:377:14: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 23:17:52 -05:00
Joe Hershberger
412411cb2e arch/powerpc/cpu/mpc85xx/ether_fcc.c: Fix compile warning
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:453:15: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Joe Hershberger
888fc6158e arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warning
Fix this:
ether_fcc.c: In function 'fec_initialize':
ether_fcc.c:390:15: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Joe Hershberger
3573c327a6 arch/powerpc/cpu/mpc8220/fec.c: Fix compile warning
Fix this:
fec.c: In function 'mpc8220_fec_recv':
fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
fec.c: In function 'mpc8220_fec_initialize':
fec.c:839:12: warning: assignment from incompatible pointer type

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 13:41:46 -05:00
Wolfgang Denk
1b10d0717a MPC8xx: fix "Remove volatile from net API" aftermath
Commit db288a9 "net: Remove volatile from net API" caused a number of
build warnings:
fec.c: In function 'fec_initialize':
fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default]
fec.c: In function 'fec_recv':
fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default]
/home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *'
scc.c: In function 'scc_initialize':
scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default]

Fix these.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2012-05-22 10:18:14 -05:00
Anatolij Gustschin
287e3ad488 arch/arm/cpu/ixp/npe/npe.c: Fix build warning
Fix:
npe.c: In function 'npe_initialize':
npe.c:630:13: warning: assignment from incompatible pointer type

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2012-05-22 10:18:13 -05:00
Wolfgang Denk
2ab5be7af0 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  USB: S5P: Add ehci support
  usb:udc:samsung Add functions for storing private gadget data in UDC driver
  usb:gadget:composite: Support for composite at gadget.h
  usb:gadget:composite USB composite gadget support
  usb:udc:samsung:cleanup Replace DEBUG_* macros with debug_cond() calls
  usb:udc: Remove duplicated USB definitions from include/linux/usb/ch9.h file
  USB: Document the QH and qTD antics in EHCI-HCD
  USB: Drop cache flush bloat in EHCI-HCD
  USB: Drop ehci_alloc/ehci_free in ehci-hcd
  USB: Align buffers at cacheline
  usb: use noinline define
2012-05-20 22:51:41 +02:00
Wolfgang Denk
8fa3d2b816 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash:
  NAND: Remove ONFI detection message to from bootup log
  driver/mtd:IFC: Fix possible memory leak
  driver/mtd: IFC NAND: Add support of ONFI NAND flash
  mtd, nand: move some printfs to debug output.
  nand_util: correct YAFFS image write function
  powerpc/85xx: fix NAND boot linker scripts for -fpic
  nand: extend .raw accesses to work on multiple pages
2012-05-20 22:47:40 +02:00
Wolfgang Denk
8bd07c9aaf Merge branch 'master' of git://git.denx.de/u-boot-net
* 'master' of git://git.denx.de/u-boot-net:
  net: move bootfile init into eth_initialize
  net: punt bd->bi_ip_addr
  net: cosmetic: netconsole.c checkpatch compliance
  net: cosmetic: tftp.* checkpatch compliance
  net: cosmetic: sntp.* checkpatch compliance
  net: cosmetic: rarp.* checkpatch compliance
  net: cosmetic: nfs.* checkpatch compliance
  net: cosmetic: net.c checkpatch compliance
  net: cosmetic: eth.c checkpatch compliance
  net: cosmetic: bootp.* checkpatch compliance
  net: cosmetic: net.h checkpatch compliance
  net: Remove volatile from net API
2012-05-20 22:33:44 +02:00
Wolfgang Denk
ee3a55fdf0 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
  OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
  ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
  ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
  arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
  OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
  omap4: do not enable auxiliary cores
  omap4: do not enable fs-usb module
  omap4: panda: disable uart2 pads during boot
  igep00x0: change mpurate from 500 to auto
  igep00x0: enable the use of a plain text file
  tegra2: trivially enable 13 mhz crystal frequency
  tegra: Enable keyboard for Seaboard
  tegra: Switch on console mux and use environment for console
  tegra: Add tegra keyboard driver
  tegra: fdt: Add keyboard definitions for Seaboard
  tegra: fdt: Add keyboard controller definition
  tegra: Add keyboard support to funcmux
  input: Add support for keyboard matrix decoding from an fdt
  input: Add generic keyboard input handler
  input: Add linux/input.h for key code support
  fdt: Add fdtdec functions to read byte array
  tegra: Enable LP0 on Seaboard
  tegra: fdt: Add EMC data for Tegra2 Seaboard
  tegra: i2c: Add function to find DVC bus
  fdt: tegra: Add EMC node to device tree
  tegra: Add EMC settings for Seaboard
  tegra: Turn off power detect in board init
  tegra: Set up warmboot code on Nvidia boards
  tegra: Setup PMC scratch info from ap20 setup
  tegra: Add warmboot implementation
  tegra: Set up PMU for Nvidia boards
  tegra: Add PMU to manage power supplies
  tegra: Add EMC support for optimal memory timings
  tegra: Add header file for APB_MISC register
  tegra: Add tegra_get_chip_type() to detect SKU
  tegra: Add flow, gp_padctl, fuse, sdram headers
  tegra: Add crypto library for warmboot code
  tegra: Add functions to access low-level Osc/PLL details
  tegra: Move ap20.h header into arch location
  Add AES crypto library
  i2c: Add TPS6586X driver
  Add abs() macro to return absolute value
  fdt: Add function to return next compatible subnode
  fdt: Add function to locate an array in the device tree
  i.MX28: Avoid redefining serial_put[cs]()
  i.MX28: Check if WP detection is implemented at all
  i.MX28: Add battery boot components to SPL
  i.MX28: Reorder battery status functions in SPL
  i.MX28: Add LRADC init to i.MX28 SPL
  i.MX28: Add LRADC register definitions
  i.MX28: Shut down the LCD controller before reset
  i.MX28: Add LCDIF register definitions
  i.MX28: Implement boot pads sampling and reporting
  i.MX28: Improve passing of data from SPL to U-Boot
  M28EVK: Add SD update command
  M28EVK: Implement support for new board V2.0
  FEC: Abstract out register setup
  MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
  i.MX28: Add delay after CPU bypass is cleared
  spi: mxs: Allow other chip selects to work
  spi: mxs: Introduce spi_cs_is_valid()
  mx53loco: Remove unneeded gpio_set_value()
  mx53loco: Add CONFIG_REVISION_TAG
  mx53loco: Turn on VUSB regulator
  mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
  pmic: dialog: Avoid name conflicts
  imx: Add u-boot.imx as target for ARM9 i.MX SOCs
  i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
  imx: usb: There is no such register
  i.MX25: usb: Set PORTSCx register
  imx: nand: Support flash based BBT
  i.MX25: This architecture has a GPIO4 too
  i.MX25: esdhc: Add mxc_get_clock infrastructure
  i.MX6: mx6q_sabrelite: add SATA bindings
  i.MX6: add enable_sata_clock()
  i.MX6: Add ANATOP regulator init
  mx28evk: add NAND support
  USB: ehci-mx6: Fix broken IO access
  M28: Scan only first 512 MB of DRAM to avoid memory wraparound
  Revert "i.MX28: Enable additional DRAM address bits"
  M28: Enable FDT support
  mx53loco: Add support for 1GHz operation for DA9053-based boards
  mx53loco: Allow to print CPU information at a later stage
  mx5: Add clock config interface
  imx-common: Factor out get_ahb_clk()
  i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
  mx31pdk: Allow booting a zImage kernel
  mx6qarm2: Allow booting a zImage kernel
  mx6qsabrelite: Allow booting a zImage kernel
  mx28evk: Allow booting a zImage kernel
  m28evk: Allow to booting a dt kernel
  mx28evk: Allow to booting a dt kernel
  mx6qsabrelite: No need to set the direction for GPIO3_23 again
  pmic: Add support for the Dialog DA9053 PMIC
  MX53: mx53loco: Add SATA support
  MX53: Add support to ESG ima3 board
  SATA: add driver for MX5 / MX6 SOCs
  MX53: add function to set SATA clock to internal
  SATA: check for return value from sata functions
  MX5: Add definitions for SATA controller
  NET: fec_mxc.c: Add a way to disable auto negotiation
  Define UART4 and UART5 base addresses
  EXYNOS: Change bits per pixel value proper for u-boot.
  EXYNOS: support TRATS board display function
  LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
  EXYNOS: support EXYNOS MIPI DSI interface driver.
  EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
  LCD: add data structure for EXYNOS display driver
  EXYNOS: add LCD and MIPI DSI clock interface.
  EXYNOS: definitions of system resgister and power management registers.
  SMDK5250: fix compiler warning
  misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
  misc:pmic:max8997 MAX8997 support for PMIC driver
  TRATS: modify the trats's configuration
  ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
  EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
  arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  cm-t35: add I2C multi-bus support
  include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
  include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
  omap3: Introduce weak misc_init_r
  omap730p2: Remove empty misc_init_r
  omap5912osk: Remove empty misc_init_r
  omap4+: Remove CONFIG_ARCH_CPU_INIT
  omap4: Remove CONFIG_SYS_MMC_SET_DEV
  OMAP3: pandora: drop console kernel argument
  OMAP3: pandora: revise GPIO configuration
  ...
2012-05-20 21:31:26 +02:00
Rajeshwari Shinde
5f0ffea455 USB: S5P: Add ehci support
This patch adds ehci driver support for s5p.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2012-05-20 08:32:33 +02:00
Scott Wood
d2a97daf62 powerpc/85xx: fix NAND boot linker scripts for -fpic
GOT is now handled the way the main u-boot.lds does it.  Without this,
the boot hangs when built with newer GCC (since 4.6).  Older toolchains
hid the issue by converting -fpic to -fPIC.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-05-18 17:34:39 -05:00
Mike Frysinger
de30122bb5 net: move bootfile init into eth_initialize
All arches init this the same way, so move the logic into the core
net code to avoid duplicating it everywhere else.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-15 17:32:33 -05:00
Mike Frysinger
50a47d0523 net: punt bd->bi_ip_addr
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr").  After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-15 17:32:05 -05:00
Matt Porter
a3c3fabb0f arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.

This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.

Signed-off-by: Matt Porter <mporter@ti.com>
2012-05-15 08:31:41 +02:00
Tero Kristo
2d622b03f8 omap4: do not enable auxiliary cores
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:41 +02:00
Tero Kristo
71ee921de0 omap4: do not enable fs-usb module
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2012-05-15 08:31:41 +02:00
Lucas Stach
b8cb5194f0 tegra2: trivially enable 13 mhz crystal frequency
This is needed for upcoming Toradex Colibri T20 upstream support.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:40 +02:00
Anton Staff
8436fbc392 tegra: fdt: Add keyboard controller definition
The Tegra keyboard controller provides a simple interface to a matrix
keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:40 +02:00
Simon Glass
7e91f40dd5 tegra: Add keyboard support to funcmux
Add funcmux support for the default keyboard mapping.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:39 +02:00
Simon Glass
e31c1e50ac tegra: i2c: Add function to find DVC bus
Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus.
This allows us to talk to the PMU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:39 +02:00
Simon Glass
1f47efa87a fdt: tegra: Add EMC node to device tree
Add a definition of the memory controller node according to the bindings
here:

http://patchwork.ozlabs.org/patch/132928/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:39 +02:00
Yen Lin
c5179da9f3 tegra: Setup PMC scratch info from ap20 setup
Save SDRAM parameters into the warmboot scratch registers

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Yen Lin
6570438a70 tegra: Add warmboot implementation
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.

Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Jimmy Zhang
6860b4a1cc tegra: Add PMU to manage power supplies
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.

- Split PMU code into separate TPS6586X driver

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Jimmy Zhang
0e35ad053f tegra: Add EMC support for optimal memory timings
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:38 +02:00
Simon Glass
1d5dba604c tegra: Add header file for APB_MISC register
Add a basic header file for this register, to be filled in as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
d515362d4d tegra: Add tegra_get_chip_type() to detect SKU
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Yen Lin
f6f767a404 tegra: Add flow, gp_padctl, fuse, sdram headers
These headers provide access to additional Tegra features.

flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Yen Lin
2a6f036a9a tegra: Add crypto library for warmboot code
Provides an interface to aes.c for the warmboot code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
ffc76482c2 tegra: Add functions to access low-level Osc/PLL details
Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass()
to find out if the Oscillator is bypassed. These are needed by warmboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
f9f3e1b8df tegra: Move ap20.h header into arch location
We want to include this from board code, so move the header into
an easily-accessible location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-05-15 08:31:37 +02:00
Simon Glass
a35925b8c1 Add abs() macro to return absolute value
This macro is generally useful to make it available in common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:37 +02:00
Marek Vasut
39007ec8cd i.MX28: Avoid redefining serial_put[cs]()
Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
7dec1bd11f i.MX28: Add battery boot components to SPL
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
399d9dab3d i.MX28: Reorder battery status functions in SPL
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
3f3255c3d7 i.MX28: Add LRADC init to i.MX28 SPL
This code is part of battery boot support for i.MX28.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
ec4836be6e i.MX28: Add LRADC register definitions
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
8d4c759f2c i.MX28: Shut down the LCD controller before reset
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
data pins interferes with the BootROM's boot mode sampling. So shut the
controller down.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
cfe96f7820 i.MX28: Add LCDIF register definitions
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:36 +02:00
Marek Vasut
f8c4a86b5e i.MX28: Implement boot pads sampling and reporting
This patch implements code that samples i.MX28 boot pads and reports boot mode
accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:35 +02:00
Marek Vasut
0239c2fb4a i.MX28: Improve passing of data from SPL to U-Boot
Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2012-05-15 08:31:35 +02:00
Stefano Babic
c4559daa91 MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
After an update to the MX51 reference manual (Rev. 5), the
values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH
are now clearly wrong:

"Bit 13:
High / Low Output Voltage Range. This bit selects the output voltage mode for
SD2_CMD. 0 High output voltage mode
1 Low output voltage mode"

The values are currently negated in code - fixed.

Reported-by: David Jander <david.jander@protonic.nl>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: David Jander <david.jander@protonic.nl>
Acked-by: David Jander <david.jander@protonic.nl>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-05-15 08:31:35 +02:00
Marek Vasut
8f975865be i.MX28: Add delay after CPU bypass is cleared
This solves issues when larger amount of DRAM is used, like 256MB.
Behave the same in case of CPU bypass as we do in case of EMI
bypass, but wait 15 ms. We need to wait until the clock domain
stabilizes.

This issue seemed to have been caused by not waiting after frobbing
with the CPU bypass, it was unrelated to memory, but had a direct
impact, causing trouble. This was yet another X-File of the
imx-bootlets, sigh. The conclusion is, trying a semi-random delay
(there is delay after the EMI bypass change), the issue is fixed.

Another possible explanation is that we do not do the "simple memory
test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
the memory, while also outputing something on the serial port). This
might have caused the similar delay in the imx-bootlets and therefore
they didn't need to add this explicitly.

For now, this seems good fix enough, but to me, whole that memory
init code in imx-bootlets is completely flunked and it'd need deeper
investigation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2012-05-15 08:31:35 +02:00
Fabio Estevam
54cd1dee8f mx53loco: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.

The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.

Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Timo Ketola
bff969eaf0 imx: Add u-boot.imx as target for ARM9 i.MX SOCs
Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Timo Ketola
8f385e958d i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
types.h must be included in imx-regs.h if one wants to include
imx-regs.h in a board configuration file. That for one's part is
necessary, if one wants to use addresses defined in imx-regs.h.

For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and
a proper thing is to define it with IMX_MMC_SDHCx_BASE in board
configuration file. This patch fixes the build in that case.

Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Timo Ketola
42d25327f5 i.MX25: esdhc: Add mxc_get_clock infrastructure
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's
implement get_clocks function. This is how it seems to be implemented
elsewhere.

Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:33 +02:00
Eric Nelson
64e7cdb5e8 i.MX6: add enable_sata_clock()
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:33 +02:00
Dirk Behme
cac833a98c i.MX6: Add ANATOP regulator init
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.

Note: This should be but can't be done in the DCD. The bootloader
      prevents access to the ANATOP registers.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
2012-05-15 08:31:33 +02:00
Marek Vasut
d2f7ae14d3 Revert "i.MX28: Enable additional DRAM address bits"
This reverts commit 69d26d09de.

Apparently, this commit got mainline only because of out-of-tree
port and causes breakage on board that is mainline. Revert.

Reason:
* The OOT board has 512MB of DRAM, enabling this additional address
  line enabled it to work fine with 512MB of RAM.
* Every mainline port has max. 256MB of DRAM, therefore this revert
  has no impact on any mainline port
* Though this caused a problem with new M28 board with 256MB of DRAM
  where the chips are wired differently. The patch-to-be-reverted
  caused the DRAM to behave like this:

  [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again]

Therefore to retain the current one-memory-init-rules-them-all situation,
revert this patch until another board emerges and will actually be pushed
mainline that needs different setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
2012-05-15 08:31:32 +02:00
Fabio Estevam
1fc56f1cb0 mx53loco: Allow to print CPU information at a later stage
Print CPU information within board_late_init().

This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Fabio Estevam
70cc86a630 mx5: Add clock config interface
mx5: Add clock config interface

Add clock config interface support, so that we
can configure CPU or DDR clock in the later init

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:32 +02:00
Fabio Estevam
6a376046ef imx-common: Factor out get_ahb_clk()
get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:32 +02:00
Stefano Babic
8c38b5d03d MX53: add function to set SATA clock to internal
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.

As stated by Freescale's support:

Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
	SATA_ALT_REF_CLK[1:0] (offset 0x180C)

'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:30 +02:00
Stefano Babic
d87c85ce43 MX5: Add definitions for SATA controller
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
2012-05-15 08:31:30 +02:00
Stefano Babic
4a9677e53f Define UART4 and UART5 base addresses
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:30 +02:00
Donghwa Lee
2c7396cb1a EXYNOS: support EXYNOS MIPI DSI interface driver.
EXYNOS SoC platform has MIPI-DSI controller and MIPI-DSI
based LCD Panel could be used with it. This patch supports MIPI-DSI driver
based Samsung SoC chip.

LCD panel driver based MIPI-DSI should be registered to MIPI-DSI driver at
board file and LCD panel driver specific function registered to mipi_dsim_ddi
structure at lcd panel init function called system init.
In the MIPI-DSI driver, find lcd panel driver by using registered
lcd panel name, and then initialize lcd panel driver.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2012-05-15 08:31:30 +02:00
Donghwa Lee
6d4339f622 EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
This patch support EXYNOS FB and FIMD display drivers.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2012-05-15 08:31:29 +02:00
Donghwa Lee
37835d4ba8 EXYNOS: add LCD and MIPI DSI clock interface.
To sets up lcd and mipi clock in EXYNOS display driver, added clock interface.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-05-15 08:31:29 +02:00
Donghwa Lee
283591f171 EXYNOS: definitions of system resgister and power management registers.
This is definitions of system registers and power mananagement registers for EXYNOS SoC.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-05-15 08:31:29 +02:00
Chander Kashyap
90005092fc EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
TZPC IP is common across Exynos based SoC'c. Renaming exynos5_tzpc
in arch/arm/include/asm/arch-exynos/tzpc.h to exynos_tzpc will allow generic
usase of tzpc.

Also modify board/samsung/smdk5250/tzpc_init.c to use exynos_tzpc.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-05-15 08:31:28 +02:00
Tom Rini
8a87a3d72e omap3: Introduce weak misc_init_r
Introduce a __weak misc_init_r function that just runs dieid_num_r().
Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was
all they did for misc_init_r.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-05-15 08:31:28 +02:00
Tom Rini
aa2889c8c3 omap4+: Remove CONFIG_ARCH_CPU_INIT
OMAP4/5 had an empty arch_cpu_init() so drop that along with
CONFIG_ARCH_CPU_INIT

Signed-off-by: Tom Rini <trini@ti.com>
2012-05-15 08:31:27 +02:00
Grazvydas Ignotas
10cd73bf87 OMAP3: pandora: pin mux updates for DM3730 board variant
DM3730 needs some additional pin mux configuration for GPIOs
126-129 to work, add it.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
2012-05-15 08:31:27 +02:00
Tom Rini
06a119a031 Makefile: Add a 'checkthumb' rule
This rule confirms that if we're on ARM and we have enabled THUMB builds
that we have a new enough toolchain to produce a working binary.

Changes in v2:
- Switch to ALL-$(CONFIG_SYS_THUMB_BUILD) in arch/arm/config.mk (Mike F)
- Simplfy checkthumb test after doing the above

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:26 +02:00
Aneesh V
03f69dc6fd omap4+: Avoid using __attribute__ ((__packed__))
Avoid using __attribute__ ((__packed__)) unless it's
absolutely necessary. "packed" will remove alignment
requirements for the respective objects and may cause
alignment issues unless alignment is also enforced
using a pragma.

Here, these packed attributes were causing alignment
faults in Thumb build.

Signed-off-by: Aneesh V <aneesh@ti.com>
2012-05-15 08:31:26 +02:00
Aneesh V
f61faeba82 armv7: Use -march=armv7-a and thereby enable Thumb-2
Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms if CONFIG_SYS_THUMB_BUILD is enabled.

Signed-off-by: Aneesh V <aneesh@ti.com>
2012-05-15 08:31:26 +02:00
Aneesh V
5356f5451e ARM: enable Thumb build
Enable Thumb build and ARM-Thumb interworking based on the new
config flag CONFIG_SYS_THUMB_BUILD

Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:26 +02:00
Aneesh V
74236acacc armv7: add appropriate headers for assembly functions
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.

Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:26 +02:00
Aneesh V
7245536d19 arm: adapt asm/linkage.h from Linux
This will add ARM specific over-rides for the defines
from linux/linkage.h

Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Mike Frysinger <vapier@gentoo.org>
2012-05-15 08:31:26 +02:00
SRICHARAN R
0696473be7 OMAP5: reset: Use cold reset in case of 5430ES1.0
Warm reset is not functional in case of omap5430ES1.0.
So override the weak reset_cpu function to use
cold reset instead.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:25 +02:00
SRICHARAN R
d417d1db5f OMAP3+: reset: Create a common reset layer.
The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:25 +02:00
Balaji T K
dd23e59d59 omap5: pbias ldo9 turn on
Add omap5 pbias configuration for mmc1/sd lines
and set voltage for sd data i/o lines

Signed-off-by: Balaji T K <balajitk@ti.com>
2012-05-15 08:31:25 +02:00
Balaji T K
f75231b79a arm: omap5: correct boot device mode7 for eMMC
In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-05-15 08:31:25 +02:00
SRICHARAN R
aaec44874f OMAP4/5: emif: Correct the emif power mgt shadow register bit fields.
PD_TIM bit field which specifies the power down timing is defined
to occupy bits 8-11, where as it is actually from 12-15 bits.
So correcting this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:25 +02:00
SRICHARAN R
971f2ba21a OMAP5: ddr: Change the ddr device name.
The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and
not a ELPIDA part. So change this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
c1fa3c37af OMAP4/5: device: Add support to get the device type.
Add support to identify the device as GP/EMU/HS.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
002a2c0c66 OMAP4/5: Make the sysctrl structure common
Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
47c50143aa OMAP5: SRAM: Change the SRAM base address.
The full internal SRAM of size 128kb is public in the case of OMAP5 soc.
So change the base address accordingly.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
087189fb54 OMAP4/5: Make the silicon revision variable common.
The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
cdd50a8d07 OMAP5: hwinit: Add the missing break statement
The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
8de17f4617 OMAP5: palmas: Configure nominal opp vdd values
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.

Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
	http://lists.denx.de/pipermail/u-boot/2012-March/119151.html

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
f40107345c OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
6ad8d67de8 OMAP5: io: Configure the io settings for omap5430 sevm board.
The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
84b16af29f OMAP5: board: Add pinmux data for omap5_evm board.
Adding the full pinmux data for OMAP5430 sevm board.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
SRICHARAN R
5f14d9197e OMAP5: clocks: Change clock settings as required for ES1.0 silicon.
Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
Nishanth Menon
f2ae6c1a83 OMAP4: scale voltage of core before MPU scales
OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior across all OMAP4 SoC, ensure that
vdd_core scale first, then vdd_mpu and finally vdd_iva.

As part of doing this refactor the logic to allow for future
addition of OMAP4470 without much ado. OMAP4470 uses different
SMPS addresses and cannot be introduced in the current code
without major rewrite.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
3acb553439 OMAP4460: TPS Ensure SET1 is selected after voltage configuration
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
a78274b205 OMAP3+: Introduce generic logic for OMAP voltage controller
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.

With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.

NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Jonathan Solnit
bbbc1ae921 ARM:OMAP+:MMC: Add parameters to MMC init
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency.  While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board.  The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.

Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
2012-05-15 08:31:22 +02:00
Vladimir Zapolskiy
cc35fdbc4d serial: add LPC32X0 high-speed UART devices support
This change adds an implementation of high-speed UART found on NXP
LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-05-15 08:31:21 +02:00
Vladimir Zapolskiy
52f69f818c arm926ejs: add NXP LPC32x0 cpu series support
This change adds initial support for NXP LPC32x0 SoC series.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-05-15 08:31:21 +02:00
Jaehoon Chung
442d55685e mmc: support the sdhci instead of s5p_mmc for samsung-soc
In driver mmc, generic s5p_sdhci code is implemented.
s5p_mmc file  is dupulicated.
we are good that use the generic sdhci.
This patch supported the sdhci  for Samsung-SoC.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Lei Wen<leiwen@marvell.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2012-05-08 18:02:22 -05:00
Wolfgang Denk
5f6db68b42 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
  powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
  cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
  PowerPC: correct the SATA for p1/p2 rdb-pc platform
  powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
  powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
  powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
  powerpc/corenet_ds: Slave module for boot from SRIO
  powerpc/corenet_ds: Master module for boot from SRIO
  powerpc/corenet_ds: Document for the boot from SRIO
  powerpc/corenet_ds: Correct the compilation errors about ENV
  powerpc/srio: Rewrite the struct ccsr_rio
  powerpc/85xx:Fix lds for nand boot debug info
  powerpc/p2041rdb: add env in NAND support
  powerpc/p2041rdb: add NAND and NAND boot support
  powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
  powerpc/85xx:Avoid vector table compilation for nand_spl
  powerpc/85xx:Fix IVORs addr after vector table relocation
  powerpc/85xx:Avoid hardcoded vector address for IVORs
  powerpc/p1023rds: Disable nor flash node and enable nand flash node
2012-04-30 16:45:56 +02:00
Wolfgang Denk
04a9cb8c59 Merge branch 'master' of git://git.denx.de/u-boot-i2c
* 'master' of git://git.denx.de/u-boot-i2c:
  i2c:designware Turn off the ctrl when setting the speed
  i2c: Add support for designware i2c controller
  sh: i2c: Add support I2C controller of SH7734
2012-04-30 16:43:49 +02:00
Wolfgang Denk
99310d1448 Merge branch 'master' of git://git.denx.de/u-boot-blackfin
* 'master' of git://git.denx.de/u-boot-blackfin:
  Blackfin: bfin_sdh: drop dos part hardcode
  Blackfin: move gd/bd to bss by default
  Blackfin: gd_t: relocate volatile markings
2012-04-30 16:41:23 +02:00
Wolfgang Denk
4868049309 Merge branch 'master' of git://git.denx.de/u-boot-nds32
* 'master' of git://git.denx.de/u-boot-nds32:
  board/adp-ag102: add configuration of adp-ag102
  board/adp-ag102: add board specific files
  nds32/ag102: add ag102 soc support
  nds32/ag102: add header support of ag102 soc
2012-04-30 16:29:16 +02:00
Wolfgang Denk
e654fac2e6 Merge branch 'marex@denx.de' of git://git.denx.de/u-boot-staging
* 'marex@denx.de' of git://git.denx.de/u-boot-staging:
  CMD: CONFIG_CMD_SETECPR -> CONFIG_CMD_SETEXPR on omap3_logic
  CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE
  CMD: Fix typo CMD_FSL -> CMD_MFSL in readme
  HWW1U1A: Fix CMD_SHA1 -> CMD_SHA1SUM
  CMD: Remove CMD_LOG, it's unused
  CMD: Fix typo KGBD -> KGDB on debris board
  CMD: Drop CONFIG_CMD_EMMC, it's not used
  CMD: Drop CONFIG_CMD_DFL, it's not used
  CMD: Drop CMD_DCR, it's not used
  CMD: Drop CMD_CAN, it's not used
  CMD: Remove CMD_AUTOSCRIPT, it's not used
  AT91: Drop AT91_SPIMUX command from cmd_all
2012-04-29 14:12:10 +02:00
Timur Tabi
822ad60f1c powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-04-24 23:58:34 -05:00
Liu Gang
5056c8e068 powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.

Master needs to:
	1. Set outbound SRIO windows in order to configure slave's registers
	   for the core's releasing.
	2. Check the SRIO port status when release slave core, if no errors,
	   will implement the process of the slave core's releasing.
Slave needs to:
	1. Set all the cores in holdoff by RCW.
	2. Be powered on before master's boot.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
0a85a9e705 powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.

NOTE: Because the slave can not erase, write master's NOR flash by SRIO
	  interface, so it can not modify the ENV parameters stored in
	  master's NOR flash using "saveenv" or other commands.

Master needs to:
	1. Put the slave's ENV into it's own memory space.
	2. Set an inbound SRIO window covered slave's ENV stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
3f1af81b80 powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
5ffa88eca7 powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:32 -05:00
Liu Gang
7d67ed58a2 powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message
units registers.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2012-04-24 23:58:32 -05:00
Prabhakar Kushwaha
5113ee706d powerpc/85xx:Fix lds for nand boot debug info
Currently "u-boot", the elf file generated via u-boot-nand.lds does not
contain required debug information i.e. .debug_{line, info, abbrev, aranges,
ranges} into their respective _global_ sections.

The original ld script line arch/powerpc/cpu/mpc85xx/start.o
KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
not process start.o again for bootpg.

So Fix u-boot-nand.lds to generate these debug information.

Signed-off-by: Anmol Paralkar <b07584@freescale.com>
Signed-off-by: John Russo <John.Russo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:31 -05:00
Prabhakar Kushwaha
119a55f9cf powerpc/85xx:Avoid vector table compilation for nand_spl
NAND SPL code never compile the vector table.
So no need to setup interrupt vector table for NAND SPL.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Prabhakar Kushwaha
64829baf04 powerpc/85xx:Fix IVORs addr after vector table relocation
After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.

As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00  hard-coded values.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Prabhakar Kushwaha
a4107f8617 powerpc/85xx:Avoid hardcoded vector address for IVORs
For e500 and e500v2 architecturees processor IVPR address should be alinged on
64K boundary.

in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
not point to an exception handler.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Vipin KUMAR
031ed2fa74 i2c: Add support for designware i2c controller
Earlier, a driver exists in the u-boot source for designware i2c interface. That
driver was specific to spear platforms. This patch implements the i2c controller
as a generic driver which can be used by multiple platforms

The driver files are now renamed to designware_i2c.c and designware_i2c.h and
these are moved into drivers/i2c folder for reusability by other
platforms

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-24 09:56:37 +02:00
Simon Glass
61ddce07f8 sandbox: Use the new run_command()
Now that run_command() handles both parsers, clean up sandbox to use it.
This fixes a build error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-04-23 22:53:54 +02:00
Stephen Warren
9e02a6b8e5 arm: restore fdt_fixup_ethernet call to do_bootm_linux
Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized
do_bootm_linux for ARM. During the re-organization, the call to
fdt_fixup_ethernet() was removed. I assume this was useful, so add it
back.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
2012-04-23 22:11:18 +02:00
Stephen Warren
1723997610 arm: fix bootm with device tree
Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized
do_bootm_linux() for ARM. During the re-organization, the code to pass
the device tree to the kernel was removed. Add it back. This restores
the ability to boot a kernel using device tree.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Allen Martin <amartin@nvidia.com>
Tested-by: Allen Martin <amartin@nvidia.com>
2012-04-23 22:10:41 +02:00
Mike Frysinger
a4932d7877 Blackfin: move gd/bd to bss by default
We don't need these setup manually, so let the bss do the rest.  On
Blackfin systems, we clear the bss before executing any C code that
would use these, so this should be fine.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-22 13:00:19 -04:00
Mike Frysinger
33e7e60c77 Blackfin: gd_t: relocate volatile markings
This makes Blackfin behave the same as other ports, and fixes many gcc
warnings that show up with 4.5+:
	board.c:40:1: warning: optimization may eliminate reads and/or
		writes to register variables

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-22 13:00:19 -04:00
Macpaul Lin
cf14123021 nds32/ag102: add ag102 soc support
Add lowlevel ag102 soc support.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-04-22 16:58:23 +08:00
Macpaul Lin
1e52fea33a nds32/ag102: add header support of ag102 soc
Add device address offsets header of ag102 soc.
Add ag102 into mach-types.h.
Add asm-offsets.c for helping convert C headers into asm.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-04-22 16:58:23 +08:00
Marek Vasut
b6e95fd47d CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: scottwood@freescale.com
2012-04-19 22:01:13 +02:00
Wolfgang Denk
f5cdc11775 Prepare v2012.04-rc2; minor Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-04-16 23:13:51 +02:00
Marek Vasut
2694bb9bcc ARM926EJS: Fix cache.c to comply with checkpatch.pl
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-04-16 22:12:01 +02:00
Marek Vasut
c6201553ba ARM926EJS: Make asm routines volatile in cache ops
We certainly don't want the compiler to reorganise the code for dcache flushing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-04-16 22:11:57 +02:00
Stefano Babic
fbf4a074e0 ARM1136: MX35: Make asm routines volatile in cache ops
As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
2012-04-16 14:53:59 +02:00
Stefano Babic
38fcc71cc5 ARM: add u-boot.imx as target for i.MX SOCs
Freescale SOCs require an header to u-boot.bin

The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Loïc Minier <loic.minier@linaro.org>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Dirk Behme <dirk.behme@googlemail.com>
2012-04-16 14:53:59 +02:00
Marek Vasut
96666a39ae DMA: Split the APBH DMA init into block and channel init
This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.

The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.

The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.

NOTE: This patch depends on:

	http://patchwork.ozlabs.org/patch/150957/

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:59 +02:00
Vikram Narayanan
a9407f2bc5 imx: Remove unneeded/repititive definitions from imx headers
Remove gpio related unused/repititive definitions from imx headers.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-04-16 14:53:59 +02:00
Stefano Babic
c8d9ceaf06 ARM: 926ejs: use debug() for misaligned addresses
Misaligned warnings are useful to debug faulty drivers.
A misaligned warning is printed also when the driver
is correct - use debug() instead of printf().

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-04-16 14:53:59 +02:00
Anatolij Gustschin
219872c8fe ARM1136: add cache flush and invalidate operations
Since commit 5c1ad3e6f8
(net: fec_mxc: allow use with cache enabled) the FEC_MXC
driver uses flush_dcache_range() and invalidate_dcache_range()
functions. This driver is also configured for ARM1136 based
'flea3' and 'mx35pdk' boards which currently do not build
as there are no ARM1136 specific flush_dcache_range() and
invalidate_dcache_range() functions. Add various ARM1136
cache functions to fix building for 'flea3' and 'mx35pdk'.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-04-16 14:53:58 +02:00
Eric Nelson
4d422fe2dc i.MX6: implement enable_caches()
disabled by default until drivers are fixed

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-04-16 14:53:58 +02:00
Eric Nelson
c415919d57 i.MX6: define CACHELINE_SIZE
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-04-16 14:53:58 +02:00
Wolfgang Denk
3f0675d1a5 Merge branch 'marek.vasut@gmail.com' of git://git.denx.de/u-boot-staging
* 'marek.vasut@gmail.com' of git://git.denx.de/u-boot-staging:
  LMB: Fix undefined lmb_reserve() on non-lmb platforms
  MIPS: fix endianess handling
  MIPS: fix inconsistency in config option for cache operation mode
  MIPS: board.c: fix init of flash data in bd_info
2012-04-09 21:34:27 +02:00
Wolfgang Denk
5c877b1ae0 Merge branch 'master' of git://git.denx.de/u-boot-nios
* 'master' of git://git.denx.de/u-boot-nios:
  nios2 - adjust gbl data off to account for bd_info
  nios2: implement get_ticks and get_tbclk
  nios2: add flush_dcache_range function
2012-04-09 17:00:45 +02:00
Daniel Schwierzeck
6cb461b4f1 MIPS: fix endianess handling
Make endianess of target CPU configurable. Use the new config
option for dbau1550_el and pb1000 boards.

Adapt linking of standalone applications to pass through
endianess options to LD.

Build tested with:
 - ELDK 4 mips_4KC- and mips4KCle
 - Sourcery CodeBench Lite 2011.03-93

With this patch all 26 MIPS boards can be compiled now in one step by
running "MAKEALL -a mips".

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-04-02 15:54:53 +02:00
Daniel Schwierzeck
979cfeaf36 MIPS: fix inconsistency in config option for cache operation mode
Commit ab2a98b117 missed to
use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-04-02 15:54:53 +02:00
Daniel Schwierzeck
71919cf153 MIPS: board.c: fix init of flash data in bd_info
Boards with CONFIG_SYS_NO_FLASH should not forced to define
CONFIG_SYS_FLASH_BASE. In this case the flash data in bd_info
should be initialized with 0 like the other archs do.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-04-02 15:54:52 +02:00
Marek Vasut
44f074c771 BOOT: Add "bootz" command to boot Linux zImage on ARM
This command boots Linux zImage from where the zImage is loaded to. Passing
initrd and fdt is supported.

Tested on i.MX28 based DENX M28EVK
Tested on PXA270 based Voipac PXA270.

NOTE: This currently only supports ARM, but other architectures can be easily
added by defining bootz_setup().

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: albert.u.boot@aribaud.net
Cc: afleming@gmail.com,
Cc: Simon Glass <sjg@chromium.org>,
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2012-03-30 22:58:55 +02:00
Wolfgang Denk
bc6f6c87b6 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (146 commits)
  arm: Use common .lds file where possible
  arm: add a common .lds link script
  arm: Remove unneeded setting of LDCSRIPT
  Define CPUDIR for the .lds link script
  arm: Remove zipitz2 link script
  Allow arch directory to contain .lds without requiring Makefile
  OMAP: Remove omap1610inn-based boards
  arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warnings
  board/ti/beagle/beagle.c: Fix build warnings
  sdrc.c: Fix typo in do_sdrc_init() for SPL
  tegra: i2c: Add I2C driver
  tegra: fdt: i2c: Add extra I2C bindings for U-Boot
  tegra: i2c: Select I2C ordering for Seaboard
  tegra: i2c: Enable I2C on Seaboard
  tegra: i2c: Select number of controllers for Tegra2 boards
  tegra: i2c: Initialise I2C on Nvidia boards
  tegra: Enhance clock support to handle 16-bit clock divisors
  fdt: Add function to allow aliases to refer to multiple nodes
  tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE
  tegra: fdt: Enable FDT support for Ventana
  tegra: fdt: Enable FDT support for Seaboard
  tegra: usb: Enable USB on Seaboard
  tegra: usb: Add common USB defines for tegra2 boards
  tegra: usb: Add USB support to nvidia boards
  arm: Check for valid FDT after console is up
  fdt: Avoid early panic() when there is no FDT present
  tegra: usb: Add support for Tegra USB peripheral
  tegra: fdt: Add function to return peripheral/clock ID
  usb: Add support for txfifo threshold
  tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard
  tegra: usb: fdt: Add additional device tree definitions for USB ports
  tegra: fdt: Add clock bindings for Tegra2 Seaboard
  tegra: fdt: Add clock bindings
  tegra: fdt: Add additional USB binding
  fdt: Add tegra-usb bindings file from linux
  fdt: Add staging area for device tree binding documentation
  tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel
  tegra: fdt: Add Tegra2x device tree file from kernel
  arm: fdt: Add skeleton device tree file from kernel
  fdt: Add basic support for decoding GPIO definitions
  fdt: Add functions to access phandles, arrays and bools
  fdt: Tidy up a few fdtdec problems
  fdt: Add tests for fdtdec
  fdt: Add fdtdec_find_aliases() to deal with alias nodes
  arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load
  net: fec_mxc: allow use with cache enabled
  net: force PKTALIGN to ARCH_DMA_MINALIGN
  i.MX28: Enable caches by default
  i.MX28: Make use of the bounce buffer
  i.MX28: Do data transfers via DMA in MMC driver
  MMC: Implement generic bounce buffer
  i.MX28: Add cache support to MXS NAND driver
  i.MX28: Add cache support into the APBH DMA driver
  ARM926EJS: Implement cache operations
  board/vpac270/onenand.c: Fix build errors
  nhk8815: fix build errors
  atmel-boards: add missing atmel_mci.h
  ARM: highbank: setup env from boot source register
  ARM: highbank: change env config to use nvram
  ARM: highbank: add reset support
  ARM: highbank: Add boot counter support
  ARM: highbank: change TEXT_BASE to 0x8000
  ARM: highbank: fix us_to_tick calculation
  ARM: highbank: add missing get_tbclk
  ARM: highbank: fix warning for calxedaxgmac_initialize
  net: calxedaxgmac: fix build due to missing __aligned definition
  EXYNOS: Add structure for Exynos4 DMC
  EXYNOS: SMDK5250: Support all 4 UARTs
  ARM: fix s3c2410 timer code
  ARM: davinci: fixes for cam_enc_4xx board
  omap3_spi: receive transmit mode
  calimain, enbw_cmc: Fix typo in comments
  Davinci: ea20: use gpio framework to access gpios
  OMAP3: mt_ventoux: sets its own mtdparts
  OMAP3: mt_ventoux: updated timing for FPGA
  twl4030: fix potential power supply handling issues
  NAND: TI: fix warnings in omap_gpmc.c
  cam_enc_4xx: Rename 'images' to 'imgs'
  arm: Add Prep subcommand support to bootm
  OMAP3: twister: add support to boot Linux from SPL
  SPL: call cleanup_before_linux() before booting Linux
  OMAP3: SPL: do not call I2C init if no I2C is set.
  Add cache functions to SPL for armv7
  devkit8000: Implement and activate direct OS boot
  omap/spl: change output of spl_parse_image_header
  omap-common/spl: Add linux boot to SPL
  devkit8000/spl: init GPMC for dm9000 in SPL
  omap-common: Add NAND SPL linux booting
  devkit8000: add config for spl command
  Add cmd_spl command
  mx53ard: Initialize return code with error
  mx53: Make PLL2 to be the parent of UART clock
  configs: imx: Use CONFIG_SF_DEFAULT_CS
  mx28evk: Provide default values for SPI bus and chip select
  USB: ehci-mx6: Add proper IO accessors
  mx6: Read silicon revision from register
  i.MX28: Drop __naked function from spl_mem_init
  mxs_spi: Return proper timeout error
  i.MX28: Make the stabilization delays shorter
  pmic_i2c: Return error in case of invalid pmic_i2c_tx_num
  mx6: Remove duplicate definition of ANATOP_BASE_ADDR
  mx6: Fix reset cause for Power On Reset case
  i.MX6: mx6qsabrelite: add MACH_TYPE_MX6Q_SABRELITE
  i.MX6: mx6q_sabrelite: add CONFIG_REVISION_TAG
  i.MX28: Enable additional DRAM address bits
  mx6q: mx6qsabrelite: setup_spi() should be called in board_init to allow use for environment
  mx31: add "ARM11P power gating" to get_reset_cause
  mx31pdk: Fix CONFIG_SYS_MEMTEST_END
  efikamx: Fix CONFIG_SYS_MEMTEST_END
  mx53smd: Fix CONFIG_SYS_MEMTEST_END
  mx53evk: Fix CONFIG_SYS_MEMTEST_END
  mx51evk: Fix CONFIG_SYS_MEMTEST_END
  i.MX6: mx6qsabrelite: add ext2 support
  imximage: Remove overwriting of flash_offset
  IXP: Fix GPIO_INT_ACT_LOW_SET()
  IXP: Fix NAND build warning on PDNB3 and SCPU
  IXP: Move PDNB3 and SCPU from Makefile to boards.cfg
  IXP: Squash warnings in IXP NPE
  IXP: Fix missing MACH_TYPE_{ACTUX?,PNB3,DVLHOST}
  IXP: Make IXP buildable with arm-linux- toolchains
  Examples: Properly append LDFLAGS to LD command
  SPL: Enable YMODEM support on BeagleBone and AM335x EVM
  SPL: Add YMODEM over UART load support
  SPL: Add README.omap3
  README: document more SPL config options
  spl.c: Use __noreturn decorator
  config.mk: Check for -fstack-usage support
  config.mk: Make cc-option create a file under include/generated
  ...
2012-03-30 18:09:08 +02:00
Simon Glass
4a0764858b arm: Use common .lds file where possible
Each cpu directory currently has its own .lds file. This is only needed
in most cases because the start.o file is in a different subdir.

Now that we can factor out this difference, we can move most cpus over
to the common .lds file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-30 07:43:47 +02:00
Simon Glass
dde3b70dcf arm: add a common .lds link script
Most ARM CPUs use a very similar link script. This adds a basic
script that can be used by most CPUs.

Two new symbols are introduced which are intended to eventually be
defined on all architectures to make things easier for generic relocation
and reduce special-case code for each architecture:

__image_copy_start is the start of the text area (equivalent to the
existing _start on ARM). It marks the start of the region which must be
copied to a new location during relocation. This symbol is called
__text_start on x86 and microblaze.

__image_copy_end is the end of the region which must be copied to a new
location during relocation. It is normally equal to the start of the BSS
region, but this can vary in some cases (SPL?). Making this an explicit
symbol on its own removes any ambiguity and permits common code to always
do the right thing.

This new script makes use of CPUDIR, now defined by both Makefile and
spl/Makefile, to find the directory containing the start.o object file,
which is always placed first in the image.

To permit MMU setup prior to relocation (as used by pxa) we add an area
to the link script which contains space for this. This is taken
from commit 7f4cfcf. CPUs can put the contents in there using their
start.S file. BTW, shouldn't that area be 16KB-aligned?

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-30 07:43:44 +02:00
Simon Glass
9492791ab4 arm: Remove unneeded setting of LDCSRIPT
This is set by the top level Makefile anyway, so drop it. This does
have the effect of changing the order - now the board link script will
have preference over the CPU one. But this seems more correct anyway.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-30 07:43:40 +02:00
Anatolij Gustschin
27ac87d91e arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warnings
Fix:
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
2012-03-29 08:19:29 +02:00
Tom Rini
33fbc9cf82 sdrc.c: Fix typo in do_sdrc_init() for SPL
We need to setup CS0 and CS1 not CS0 and CS0 again.

Signed-off-by: Tom Rini <trini@ti.com>
2012-03-29 08:19:29 +02:00
Yen Lin
96a78ac0c4 tegra: i2c: Add I2C driver
Add basic i2c driver for Tegra2 with 8- and 16-bit address support.
The driver requires CONFIG_OF_CONTROL to obtain its configuration
from the device tree.

(Simon Glass: sjg@chromium.org modified for upstream)

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:50 +02:00
Simon Glass
34fa833aee tegra: fdt: i2c: Add extra I2C bindings for U-Boot
Add U-Boot's peripheral clock information to the Tegra20 device tree file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:50 +02:00
Simon Glass
2e33559f3d tegra: Enhance clock support to handle 16-bit clock divisors
I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:50 +02:00
Simon Glass
f4589a7d6f tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE
Change this name to fit with the current convention in the Tegra
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:49 +02:00
Simon Glass
2866903b3e arm: Check for valid FDT after console is up
When using CONFIG_OF_CONTROL, add a check that we have a valid FDT
and panic() if not. This must be done after the console is ready.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:49 +02:00
Simon Glass
87f938c9f7 tegra: usb: Add support for Tegra USB peripheral
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.

Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb@0xc5008000";
                usb1 = "/usb@0xc5000000";
        };

drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
ed2974493e tegra: fdt: Add function to return peripheral/clock ID
A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
1c1cce99d4 tegra: usb: fdt: Add additional device tree definitions for USB ports
This adds clock references to the USB part of the device tree for U-Boot,
and marks USB1 as supporting legacy mode (which we disable in the driver).

The USB timing information may vary between boards sometimes, but for
now we hard-code it in C. This is because all current T2x boards use
the same values, we will deal with T3x later and we first need to agree
on the format for this timing information in the fdt and may in fact
decide that it has no place there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
1f1a02123c tegra: fdt: Add clock bindings
This adds a basic binding for the oscillator and peripheral clocks. The
second cell is the clock number, defined as the bit number within the clock
enable register if the peripheral clock.

This uses the RFC clock bindings from Grant Likely so may change later:

https://lkml.org/lkml/2011/12/12/498

It is taken from Stephen Warren's patch here:

http://patchwork.ozlabs.org/patch/141359/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:48 +02:00
Simon Glass
c3474ef32d tegra: fdt: Add Tegra2x device tree file from kernel
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

config.mk is updated to provide this file to boards through the
built-in mechanism:

/include/ ARCH_CPU_DTS

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:47 +02:00
Simon Glass
92665df21d arm: fdt: Add skeleton device tree file from kernel
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-03-29 08:12:47 +02:00
Tom Warren
d8bd820935 arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load
The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Change it to use a load
thru another reg using mov sp, %0 : : "r"(CONST).

Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2012-03-29 08:12:47 +02:00
Marek Vasut
345cd3584c i.MX28: Enable caches by default
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2012-03-29 07:57:08 +02:00
Marek Vasut
a4aaad7048 ARM926EJS: Implement cache operations
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-03-29 07:56:02 +02:00
Anatolij Gustschin
b39643b72c nhk8815: fix build errors
Fix:
common/libcommon.o: In function `cread_line':
/home/ag/git/u-boot/common/main.c:695: undefined reference to `get_ticks'
/home/ag/git/u-boot/common/main.c:695: undefined reference to `get_tbclk'
/home/ag/git/u-boot/common/main.c:698: undefined reference to `get_ticks'

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Alessandro Rubini <rubini@unipv.it>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Alessandro Rubini <rubini@unipv.it>
2012-03-28 23:53:22 +02:00
Rob Herring
0c34e69f57 ARM: highbank: add reset support
Implement reset for highbank platform. Reset is triggered via a wfi
instruction, so enabling armv7 for the compiler is necessary.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:31:23 +02:00
Rob Herring
877012df30 ARM: highbank: Add boot counter support
Add boot counter support using an sysreg which is persistent across reset.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:31:20 +02:00
Rob Herring
ceb2071c6b ARM: highbank: fix us_to_tick calculation
udelay calls were off due to failing to convert us to ns. Fix this and drop
the unnecessary shifts since NS_PER_TICK is only 7ns.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:31:08 +02:00
Rob Herring
f1e2d1762d ARM: highbank: add missing get_tbclk
The get_tbclk function was missing and the recent commit "common: add
possibility for readline_into_buffer timeout" makes it required.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-03-28 23:30:54 +02:00
Chander Kashyap
95c2fb371a EXYNOS: Add structure for Exynos4 DMC
Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC).

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-03-27 22:08:28 +02:00
David Müller (ELSOFT AG)
d0b3b49615 ARM: fix s3c2410 timer code
This patch fixes the s3c24x0 timer code to work with the ARM
relocation feature.

Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-03-27 22:08:28 +02:00
Simon Schwarz
0a672d494d arm: Add Prep subcommand support to bootm
Adds prep subcommand to bootm implementation of ARM. When bootm is called
with the subcommand prep the function stops right after ATAGS creation and
before announce_and_cleanup.

This is used in command "cmd_spl export"

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-03-27 22:05:29 +02:00
Stefano Babic
53c4492c0b SPL: call cleanup_before_linux() before booting Linux
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
2012-03-27 22:05:29 +02:00
Stefano Babic
da521387a4 OMAP3: SPL: do not call I2C init if no I2C is set.
Call i2c initialization in spl_board_init only if I2C
is configured for the board.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
2012-03-27 22:05:29 +02:00
Stefano Babic
d460587a44 Add cache functions to SPL for armv7
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
2012-03-27 22:05:29 +02:00
Simon Schwarz
ace73189a5 omap/spl: change output of spl_parse_image_header
This only outputs "Assuming u-boot.bin..." if debug is active.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Simon Schwarz
379c19ab70 omap-common/spl: Add linux boot to SPL
This adds Linux booting to the SPL

This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)

Related CONFIGs:
CONFIG_SPL_OS_BOOT
	Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
	defines the IO-pin number u-boot switch - if pressed u-boot is
	booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
	Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
	Address where the kernel boot arguments are expected - this is
	normaly RAM-begin + 0x100

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Simon Schwarz
9e70c08b6f devkit8000/spl: init GPMC for dm9000 in SPL
Linux crashes if the GPMC isn't configured for the dm9000.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Simon Schwarz
df163a5980 omap-common: Add NAND SPL linux booting
This implements booting of Linux from NAND in SPL

Related config parameters:
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
	Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
	Address where the kernel boot arguments are expected - this is
	normally RAM-start + 0x100 (on ARM)

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
2012-03-27 22:05:28 +02:00
Fabio Estevam
67ee3dd35e mx53: Make PLL2 to be the parent of UART clock
Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.

FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.

On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.

Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.

Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2012-03-27 09:41:17 +02:00
Fabio Estevam
a768386746 mx6: Read silicon revision from register
Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU:   Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
2012-03-27 09:41:16 +02:00
Marek Vasut
494931a674 i.MX28: Drop __naked function from spl_mem_init
Instead of compiling the function and using the result as a constant, simply use
the constant.

NOTE: This patch works around bug:

  http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
2012-03-27 09:41:16 +02:00
Marek Vasut
a89300338a i.MX28: Make the stabilization delays shorter
Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be
enough according to the datasheet and bootlets.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
2012-03-27 09:41:16 +02:00
Fabio Estevam
334bd0e225 mx6: Remove duplicate definition of ANATOP_BASE_ADDR
Remove duplicate definition of ANATOP_BASE_ADDR.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-03-27 09:41:16 +02:00
Fabio Estevam
cece262209 mx6: Fix reset cause for Power On Reset case
After booting mx6qsabrelite from POR the following is reported:

CPU:   Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset

This is because both the POR and WDOG bits are set after reset.

Fix this by also checking both bits in the POR case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-03-27 09:41:16 +02:00
Marek Vasut
69d26d09de i.MX28: Enable additional DRAM address bits
Enables all fourteen address lines for DRAM

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
2012-03-27 09:41:15 +02:00
Helmut Raiger
82081406a2 mx31: add "ARM11P power gating" to get_reset_cause
Add missing reset reason 7 to get_reset_cause().

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
2012-03-27 09:41:15 +02:00
Marek Vasut
cd207cde94 IXP: Fix GPIO_INT_ACT_LOW_SET()
The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7.
This is due to the fact that there are two registers for total of 16 lines.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
2012-03-26 23:09:26 +02:00
Marek Vasut
0c7857f253 IXP: Squash warnings in IXP NPE
IxEthAcc.c: In function ‘ixEthAccInit’:
IxEthAcc.c:105:21: warning: comparison between ‘IxEthDBStatus’ and ‘enum <anonymous>’ [-Wenum-compare]
IxEthDBAPISupport.c: In function ‘ixEthDBPortAddressSet’:
IxEthDBAPISupport.c:633:18: warning: variable ‘ackPortAddressLock’ set but not used [-Wunused-but-set-variable]
IxQMgrDispatcher.c: In function ‘ixQMgrLLPShow’:
IxQMgrDispatcher.c:1194:18: warning: variable ‘q’ set but not used [-Wunused-but-set-variable]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
2012-03-26 23:09:26 +02:00
Marek Vasut
696df71b5f IXP: Make IXP buildable with arm-linux- toolchains
Add -EB flag to LD to switch endianness of the linker. This should make armeb
targets buildable again. Also, make use of U-Boot's internal libgcc instead of
toolchain's one, this works around the use of libraries from GCC, which might be
little endian.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
2012-03-26 23:09:25 +02:00
Matt Porter
24de357a30 SPL: Add YMODEM over UART load support
Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-03-26 23:09:25 +02:00
Tom Rini
ad1820a3c6 spl.c: Use __noreturn decorator
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Rini <trini@ti.com>
2012-03-26 23:09:25 +02:00
Robert Delien
56df16f25a Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers
This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.

Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
2012-03-26 23:09:24 +02:00
Robert Delien
531bb825fd Introducing 8-bit wide register, mx28_register_8
This patch introduces an 8-bit register, mx28_register_8, in order to
prepare for fixing erroneous 32-bit wide access of registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.

Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
2012-03-26 23:09:24 +02:00
Robert Delien
b228e14e96 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8
This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.

Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
2012-03-26 23:09:24 +02:00
Marek Vasut
40083c52f7 i.MX28: Reformat the DRAM memory configuration data
Reformat the data so it's easier to navigate through them.

Signed-off-by: Marek Vasut <marex@denx.de>
2012-03-26 23:09:24 +02:00
Wolfgang Grandegger
3f467529ca usb/ehci: Add USB support for the MX6Q
Currently, only USB Host 1 is supported.

Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2012-03-26 23:09:23 +02:00
Robert Delien
1e94d07faf i.mx28: Replaced magic numbers for scratch register addresses with register definitions
This patch replaces the use of magice numbers for scratch register
addresses with earlier defined register definitions.

Signed-off-by: Robert Delien <robert@delien.nl>
2012-03-26 23:09:23 +02:00
Robert Delien
c67d9c5e58 i.mx28: Added register definitions for DIGCTL registers
This patch adds register definitions for the registers of the DIGCTL
IP-block.

Signed-off-by: Robert Delien <robert@delien.nl>
2012-03-26 23:09:23 +02:00
Marek Vasut
30a14ea2b1 PXA: Fix missing get_tbclk() breaking vpac boards
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2012-03-26 23:09:23 +02:00
Nobuhiro Iwamatsu
e1bc28f02a sh: Add header file of MMC framework
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-03-26 10:09:31 +09:00
Nobuhiro Iwamatsu
068abf0c4c sh: Add header file for interface of SH MMC
This defines the mmcif_mmc_init which is an MMC function of SH.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-03-26 10:09:31 +09:00
Macpaul Lin
1a05bb3c28 nds32/n1213: correct vector table in start.S
Correct definition of vector table in start.S

Signed-off-by: Macpaul Lin <macpaul@gmail.com>
2012-03-19 15:53:14 +08:00
Macpaul Lin
b0c4fae44a nds32: fix ptrace and interrupt register overflow
Fix ptrace and interrupt register overflow warning.
Add missing P0 and P1 (r26 and r27) into register lists.
These register are usually used in OS.

Signed-off-by: Macpaul Lin <macpaul@gmail.com>
2012-03-19 15:53:07 +08:00
Ajay Bhargav
54cb00486e USB: Armada100: EHCI Driver for Armada100 SOCs
This patch adds support for USB EHCI driver for Armada100 SOCs.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2012-03-19 00:08:26 +01:00
Ajay Bhargav
732c7c2446 USB: Armada100: Add UTMI PHY interface driver
This patch adds USB host controller's UTMI PHY interface driver for
Armada100 SOCs.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2012-03-19 00:08:26 +01:00
Mike Frysinger
5b84dd67cf usb: replace wait_ms() with mdelay()
Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func.  This also fixes the build errors:

ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-03-19 00:08:16 +01:00
Simon Glass
f933e84e34 bootstage: arm: Add bootstage calls in board and bootm
Add calls to bootstage before and after relocation, and just
before jumping to the OS.

The idea here is you can call bootstage_report() to get a report.
Additionally, if you define CONFIG_BOOTSTAGE_REPORT then a report is
printed automatically by U-Boot just before jumping to the kernel.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:43:17 +01:00
Simon Glass
770605e4f9 bootstage: Replace show_boot_progress/error() with bootstage_...()
These calls should not be made directly any more, since bootstage
will call the show_boot_...() functions as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:41:39 +01:00
Simon Glass
8ade950638 bootstage: Convert progress numbers 20-41 to enums
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-03-18 21:16:22 +01:00
Simon Glass
5ddb118da4 bootstage: Use show_boot_error() for -ve progress numbers
Rather than the caller negating our progress numbers to indicate an
error has occurred, which seems hacky, add a function to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-18 20:56:00 +01:00
Simon Glass
578ac1e9ba bootstage: Make use of BOOTSTAGE_ID_RUN_OS in show_boot_progress()
This changes the number 15 as used in boot_stage_progress() to use the
new name provided for it. This is a separate patch because it touches
so many files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-18 20:45:57 +01:00
Wolfgang Denk
6e94125f9c Merge branch 'master' of git://git.denx.de/u-boot-avr32
* 'master' of git://git.denx.de/u-boot-avr32:
  atmel_mci.h: remove outdated register macros
  doc/git-mailrc: add <me> to avr32 alias
  ATMEL: remove old atmel_mci driver
  ATMEL: use generic mmc framework
2012-03-17 21:50:59 +01:00
Wolfgang Denk
6ae38b8c58 Merge branch 'sandbox' of git://git.denx.de/u-boot-blackfin
* 'sandbox' of git://git.denx.de/u-boot-blackfin:
  sandbox: mark os_exit as noreturn
  sandbox: add getopt support
  sandbox: allow processing before main loop
  sandbox: add concept of sandbox state
  sandbox: disable fortification
  sandbox: u-boot.lds: tweak style
  sandbox: add get_{tbclk,ticks}
  sandbox: enable GPIO driver
  sandbox: gpio: add basic driver for simulating GPIOs
  sandbox: add flags for open() call
  sandbox: config: enable fdt and snprintf() options
  sandbox: fdt: add support for CONFIG_OF_CONTROL
  sandbox: add lseek helper
  sandbox: add ifdef protection to os.h
  sandbox: add required header to os.c
  sandbox: sort header files in os.c
2012-03-17 21:46:33 +01:00
Sven Schnelle
c9abb4260c ATMEL: remove old atmel_mci driver
All boards are using the gen_atmel_mci driver now, so no need
to carry the old driver around.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-03-13 12:06:42 +01:00
Sven Schnelle
72fa467988 ATMEL: use generic mmc framework
gen_atmel_mci works on AVR32 as well, so no need to use the legacy
mmc driver. This also has the nice side effect of being able to use
SDHC cards an those boards.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-03-13 12:06:41 +01:00
Simon Glass
70db4212fc sandbox: add getopt support
This adds simple command-line parsing to sandbox. The idea is that it
sets up the state with options provided, and this state can then be
queried later, as needed.

New flags are declared with the SB_CMDLINE_OPT_SHORT helper macro,
pointers are automatically gathered up in a special section, and
then the core code takes care of gathering them up and processing
at runtime.  This way there is no central place where we have to
store a list of flags with ifdefs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:06:01 -04:00
Simon Glass
ab4e07eb71 sandbox: allow processing before main loop
In order to pass command line arguments to sandbox we need to be able
to act on them. So take control back at the end of board_init_r() from
where we can call the main loop or do something else.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:06:00 -04:00
Simon Glass
6fb6207821 sandbox: add concept of sandbox state
The state exists through the life of U-Boot. It can be adjusted by command
line options and perhaps later through a config file.  It is available to
U-Boot through state_...() calls (within sandbox code).

The primary purpose of this is to contain the "hardware" state.  It should
only be used by sandbox internal code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:06:00 -04:00
Mike Frysinger
20186a1cbf sandbox: disable fortification
Since we provide all our own library calls, the fortification from
glibc just gets in our way (which some distros enable by default).

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:43 -04:00
Mike Frysinger
3ab7d95aa0 sandbox: u-boot.lds: tweak style
We use tabs for indentation, not spaces.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:43 -04:00
Simon Glass
8d30fcd9a1 sandbox: gpio: add basic driver for simulating GPIOs
This provides a way of simulating GPIOs by setting values which are seen
by the normal gpio_get/set_value() calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:42 -04:00
Simon Glass
d9165153ca sandbox: add flags for open() call
This provides a way for callers to create files for writing. The flags
are translated at runtime, for the ones we support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:42 -04:00
Simon Glass
f7b2af0a22 sandbox: fdt: add support for CONFIG_OF_CONTROL
This adds support for a controlling fdt, mirroring the ARM implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:42 -04:00
Mike Frysinger
e2dcefcb40 sandbox: add lseek helper
Follow up patches want to be able to seek fd's.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:42 -04:00
Simon Glass
3bdf56b786 sandbox: add required header to os.c
We should include the sys/time.h header to avoid warnings.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:42 -04:00
Simon Glass
e101247212 sandbox: sort header files in os.c
Tidy this up as the list is long and likely to get longer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-12 11:03:41 -04:00
Nobuhiro Iwamatsu
78df8c68cd sh: timer: Remove unnecessary variable 'ticks'
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reported-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-03-08 10:26:38 +09:00
Wolfgang Denk
12ae615fba Merge branch 'master' of git://git.denx.de/u-boot-x86
* 'master' of git://git.denx.de/u-boot-x86:
  sc520: fix build warning about unused temp var
2012-03-06 21:28:45 +01:00
Simon Glass
5307153236 Stop using builtin_run_command()
Boards can select either the 'built-in' parser or the hush parser. We
should not call builtin_run_command() if we are using the hush parser.
We use run_command() instead, since it knows how to call the correct
parser.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-06 21:09:26 +01:00
Simon Glass
f47360a74e Rename run_command() to builtin_run_command()
The current run_command() is only one of the parsing options - the other
is hush. We should not call run_command() when the hush parser is being
used. So we rename this function to better explain its purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-06 21:09:18 +01:00
Mike Frysinger
ae806cc6ab sc520: fix build warning about unused temp var
Building the eNET_SRAM board fails for me:
	sc520_timer.c: In function 'sc520_udelay':
	sc520_timer.c:81:7: error: variable 'temp' set but not used
		[-Werror=unused-but-set-variable]
	cc1: all warnings being treated as errors
	make[1]: *** [sc520_timer.o] Error 1

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-06 21:05:18 +11:00
Thomas Weber
b199c6e2d7 Remove execute permissions from source files
Signed-off-by: Thomas Weber <weber@corscience.de>
2012-03-04 21:56:15 +01:00
Simon Glass
d01b17611b ppc: Change memsz variable to signed char
This seems to be unsigned char for no good reason. Tidy this up and
remove the casts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-03 16:56:51 +01:00
Simon Glass
a5466651e9 m68k: Change memsz to a signed char to avoid warning
There doesn't seem to be any reason for using uchar here, so change it
to char. This fixes a warning:

pointer targets in passing argument 1 of 'sprintf' differ in signedness

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-03-03 16:56:43 +01:00
Wolfgang Denk
8a1239e74c Merge branch 'master' of git://git.denx.de/u-boot-nds32
* 'master' of git://git.denx.de/u-boot-nds32:
  nds32/board.c: add PCI prompt at boot up
  nds32/ag101/watchdog.S: add linkage support
  nds32: add linkage support
2012-03-03 15:13:41 +01:00
Macpaul Lin
4ef806794a nds32/board.c: add PCI prompt at boot up
add PCI prompt at boot up for probing PCI device

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-02-28 13:21:40 +08:00
Macpaul Lin
3998586bce nds32/ag101/watchdog.S: add linkage support
Add linkage support to watchdog.S.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-02-28 13:09:23 +08:00
Macpaul Lin
184e6f7db9 nds32: add linkage support
Add linkage support.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-02-28 13:09:23 +08:00
Aneesh V
f1f2c3ca9f armv7: omap3: leave outer cache enabled
Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.

Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f408

However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.

As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.

Signed-off-by: Aneesh V <aneesh@ti.com>
2012-02-27 21:19:25 +01:00
Helmut Raiger
d1300f7686 tt01: add video support
The video setup for the Epson display is provided. Addtionally
some extra info is displayed next to the Linux logo.
Make get_cpu_rev() publicly available (added to sys_proto.h).

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
2012-02-27 21:19:25 +01:00
Troy Kisky
28774cbaac net: fec_mxc: add 1000 Mbps selection
Define FEC_QUIRK_ENET_MAC and add to
arch-mx6/imx-regs.h

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:24 +01:00
prabhakar.csengg@gmail.com
fda9c20c80 dm6467Tevm: Use a common configuration file for davinci_dm6467evm and davinci_dm6467Tevm
In commit 2d575e4685 a separate header
file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h.
The substantial difference between the davinci_dm6467evm and the
davinci_dm6467Tevm configuration is a single bit in the hardware revision
that is passed to the Linux kernel and davinci_dm6467evm has
REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a
REFCLK_FREQ = 33000000.

This patch removes include/configs/davinci_dm6467Tevm.h. Instead the
include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and
renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined
in boards.cfg.

Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Tom Rini <trini@ti.com>
2012-02-27 21:19:24 +01:00
Chase Maupin
0e35bde7b1 am33xx: ddr_defs.h: Change DDR timings
* For cold silicon the DDR timings need to be relaxed in order for
  the device to boot with DDR at 266MHz
* Fix proposed by James Doublesin

Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
2012-02-27 21:19:24 +01:00
Hadli, Manjunath
826e99136e davinci: cleanup davinci_sync_env_enetaddr() fucntion
check for the return status for eth_getenv_enetaddr_by_index()
and eth_setenv_enetaddr() functions and print appropriate message
on failure.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-02-27 21:19:24 +01:00
Fabio Estevam
ec0919f54b mx35: generic: Let get_reset_cause be defined only when CONFIG_DISPLAY_CPUINFO is selected
get_reset_cause() function is only used inside print_cpuinfo(), so let it be
defined only when CONFIG_DISPLAY_CPUINFO is selected.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:24 +01:00
Eric Nelson
d5c37c9cc4 mx6q: Add support for ECSPI through mxc_spi driver
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
2012-02-27 21:19:23 +01:00
Eric Nelson
08c61a589b mxc_spi: move machine specifics into CPU headers
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU

Introduce two new macros to control conditional setup
     MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
     MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-02-27 21:19:23 +01:00
Eric Nelson
4b3a30e9ae mx6q: define GPIO macros for translating between ordinals and port:index
The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The registers themselves
and much of the i.MX documentation are banked in groups of 32, and these
macros allow the use of the port:index numbering for clarity.

GPIO_NUMBER() converts to ordinal value from port:index
GPIO_PORT() returns the port of an ordinal value
GPIO_INDEX() returns the index or offset of the ordinal.

Discussion on the mailing list at
	http://lists.denx.de/pipermail/u-boot/2012-January/116927.html

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-02-27 21:19:23 +01:00
Stefano Babic
63b1e004f5 MX27: add missing get_tbclk()
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-02-27 21:19:23 +01:00
Marek Vasut
ff250f3ed8 MX28: Fix get_timer() / get_tbclk() issue
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
2012-02-27 21:19:23 +01:00
Matthias Fuchs
61698fd563 mx28: fix SPL code to make USB booting work
This patch fixes booting i.MX28 CPUs via USB download.
In this mode the CPU's bootrom implements a USB HID device that
accepts a bootstream.

When downloading the bootstream via USB, first the SPL code is
received and executed. Then the u-boot image is received and
called.

The USB bootmode is interrupt driven.

This patch fixes two things:

1) The ARM's fast interrupt mode is disabled when the SPL code
has been run. So save and restore the CPSR register.

2) Save and restore c1 control register: the exception vector
location needs to be set back to bootrom space to make the USB
interrupts work again. The SPL code needs to change this
option for the ram size probing.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-02-27 21:19:23 +01:00
Marek Vasut
534dbd1219 i.MX28: Fix VDDIO and VDDA setup
The DC power STS shouldn't be checked if booting off 5V supply.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
2012-02-27 21:19:23 +01:00
Stefano Babic
782bb0d236 MX5/MX6: add missing get_ticks() and get_tbclk()
commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Marek Vasut <marek.vasut@gmail.com>
2012-02-27 21:19:23 +01:00
Stefano Babic
60ebcffbf1 MX31: add missing get_tbclk()
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Helmut Raiger <helmut.raiger@hale.at>
2012-02-27 21:19:23 +01:00
Stefano Babic
31bb50f815 MX35: add missing get_ticks() and get_tbclk()
commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-02-27 21:19:23 +01:00
Stephan Linz
0f883267a8 microblaze: avoid interrupt race conditions
The interrupt acknowledge action have to run after the
registered interrupt handler. So we have a chance to
bear out the corresponding interrupt request in the
corresponding controller hardware.

With this reordering, we optain a proper interrupt
handling for level triggered interrupt sources -- for
example the new axi_timer v1.02.a introduced in ISE 13.2.

Signed-off-by: Stephan Linz <linz@li-pro.net>
Acked-by: Michal Simek <monstr@monstr.eu>
2012-02-23 12:16:04 +01:00
Stephan Linz
b9f0b73052 microblaze: fix build failure due to undefined reference to `get_ticks'
after commit "common: add possibility for readline_into_buffer
timeout" (sha1:9c34831) was applied. The Microblaze generic build
fails with error below:

common/libcommon.o: In function `cread_line':
/devel/u-boot/common/main.c:717: undefined reference to `get_ticks'
/devel/u-boot/common/main.c:717: undefined reference to `get_tbclk'
/devel/u-boot/common/main.c:720: undefined reference to `get_ticks'

Signed-off-by: Stephan Linz <linz@li-pro.net>
Acked-by: Michal Simek <monstr@monstr.eu>
2012-02-23 12:15:14 +01:00
Alex Hornung
7bd7b31574 nios2: implement get_ticks and get_tbclk
* Copy over Blackfin's get_ticks and get_tbclk - they work just fine on
   Nios2.

Signed-off-by: Alex Hornung <alex@alexhornung.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2012-02-23 08:31:20 +08:00
Stefan Kristiansson
8875833a86 nios2: add flush_dcache_range function
exposes functionality to flush dcache according to
the common.h API

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2012-02-23 07:53:03 +08:00
Wolfgang Denk
2acca35ce4 Merge branch 'master' of git://git.denx.de/u-boot-mmc
* 'master' of git://git.denx.de/u-boot-mmc:
  mmc: make mmc_send_status() more reliable
  mmc: fix card busy polling
  Tegra: mmc: Fixed handling of interrupts in timeouts.
  omap_hsmmc: Wait for CMDI to be clear
2012-02-17 23:54:46 +01:00
Wolfgang Denk
7dda0c3759 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/8xxx:Add MPH controller support in USB device-tree fixup
  powerpc/8xxx: Cleanup USB device-tree fixup
2012-02-17 23:54:17 +01:00
Wolfgang Denk
e390e87091 Merge branch 'master' of git://git.denx.de/u-boot-x86
* 'master' of git://git.denx.de/u-boot-x86:
  x86: Convert board_init_f_r to a processing loop
  x86: Split init functions out of board.c
  x86: Move relocation code out of board.c
  x86: Move setup_pcat_compatibility() out of board.c
  x86: Move do_go_exec() out of board.c
  CHECKPATCH: arch/x86/lib/*
  x86: Tweak IDT and GDT for alignment and readability
  x86: Allow cache before copy to RAM
  x86: Create weak init_cache() and default enable_caches() functions
  x86: Set GD_FLG_RELOC after entering in-RAM copy of U-Boot
  x86: Use fs for global data
  x86: Rework relocation calculations
  x86: Simplify Flash-to-RAM code execution transition
  x86: Rework Global Descriptor Table loading
  x86: Remove GDR related magic numbers
  x86: Speed up copy-to-RAM and clear BSS operations
  x86: Import glibc memcpy implementation
2012-02-17 23:47:29 +01:00
Tom Rini
a7778f8fbe omap_hsmmc: Wait for CMDI to be clear
Before we can send a command we need both the DATI (command inhibit on
mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear.
The previous behavior of only checking on DATI was insufficient on some
cards and incorrect behavior in any case.  This makes the code check
for both bits being clear and makes the error print more clear as
to what happened.  DATI_CMDDIS is removed as it was unused elsewhere
in the code and stood for 'DATI is set, cmds are disabled still'.

Fix originally spotted by Peter Bigot.

Tested-by: Peter A. Bigot <bigotp@acm.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
2012-02-15 17:42:22 -06:00
ramneek mehresh
79f49120ba powerpc/8xxx:Add MPH controller support in USB device-tree fixup
Add support for fixing usb mode and phy type for
MPH(Multi Port Host) USB controllers in device-tree nodes.
Required for socs like P3060, P5020, etc having MPH USB controller

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-02-15 16:50:14 -06:00
ramneek mehresh
5a52977f28 powerpc/8xxx: Cleanup USB device-tree fixup
Some code cleanup done for USB device-tree fixup:
	- handling error value returned from fdt_fixup_usb_mode_phy_type()
	- using ARRAY_SIZE macro
	- using snprintf instead of sprintf

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-02-15 16:50:14 -06:00
Wolfgang Denk
06576b2efc Merge branch 'master' of git://git.denx.de/u-boot-blackfin
* 'master' of git://git.denx.de/u-boot-blackfin:
  Blackfin: pata_bfin: fix printf warning
  Blackfin: bfin_nand: mark local func static
  linkage.h: move from blackfin to common includes
  Blackfin: br4: new board port
  Blackfin: add in/out le32 variants
  post: add blackfin to the post_time_ms list
  Blackfin: bf537-stamp: drop board reset workaround
  Blackfin: pr1: new board port
2012-02-13 23:13:22 +01:00
Macpaul Lin
273d11eae5 linkage.h: move from blackfin to common includes
1. Add linkage.h support from blackfin to common include,
   which is a reduced version from Linux.
2. Add architecture part support of linkage.h into blackfin
3. Fix include path of in blackfin related to linkage.h
   due to header file movement.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-02-12 15:03:26 -05:00
Mike Frysinger
dae2242ada Blackfin: add in/out le32 variants
These are rarely used, but the post code does currently, so add small
redirect hacks for that.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-02-12 15:03:25 -05:00
Sughosh Ganu
6b873dcabd Changes to move hawkboard to the new spl infrastructure
This patch moves hawkboard to the new spl infrastructure from the
older nand_spl one.

Removed the hawkboard_nand_config build option -- The spl code now
gets compiled with hawkboard_config, after building the main u-boot
image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard
to reflect the same.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
2012-02-12 10:11:33 +01:00
Christian Riesch
d735a99d3b arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
2012-02-12 10:11:33 +01:00
Christian Riesch
b67d8816fd arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x00000000. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
2012-02-12 10:11:33 +01:00
Sughosh Ganu
da104e04ec arm, arm926ejs: Flush the data cache before disabling it
The current implementation invalidates the data cache before turning it
off and causes problems on the hawkboard. See the discussion in
http://lists.denx.de/pipermail/u-boot/2012-January/115212.html

According to the ARM926EJ-S Technical Reference Manual, the cache should
be flushed instead.

Also fix the comments to match code.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>

Rebased and corrected commit message.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
2012-02-12 10:11:33 +01:00
Christian Riesch
27b66622b5 arm, arm926ejs: Do cpu critical inits only for boards that require it
This patch reverts commit ca4b55800e
"arm, arm926ejs: always do cpu critical inits" since it impacts all
arm926ejs based configurations and caused problems, e.g., with
the hawkboard.

Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines
from the board configurations that need low level initialization.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
2012-02-12 10:11:33 +01:00
Christian Riesch
eb93524224 arm, davinci: Add lowlevel_init for SoCs other than DM644X
The low level initialization code in
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for
DM644X SoCs only. This patch makes the lowlevel_init function in this
file a dummy function for SoCs other than DM644X.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Sergey Kubushyn <ksi@koi8.net>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
2012-02-12 10:11:32 +01:00
Peter Barada
9540c7e900 ARMV7: Fix duplicate use of "b" parameter in ACTIM_CTRLA definition
ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS()
instead of "c".  To make usage more clear, replace all single-letter
macro parameters with more descriptive parameter names.

Signed-off-by: Peter Barada <peter.barada@logicpd.com>
2012-02-12 10:11:32 +01:00
Aneesh V
c8ff6a9ed9 OMAP4460: Reduce MPU clock speed from 920 to 700
We do not have thermal management or Smartreflex
enabled at U-Boot level. So, it's better to stick
to OPP100 for MPU instead of the OPP Turbo that is
used now. Adjust the VDD_MPU accordingly.

Tested-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
2012-02-12 10:11:32 +01:00
Hadli, Manjunath
8f5d468721 davinci: add support for printing clock frequency
add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
2012-02-12 10:11:32 +01:00
Hadli, Manjunath
6678cebc09 davinci: remove macro CONFIG_DISPLAY_CPUINFO
remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'bdinfo' command and also remove support print_cpuinfo() as it will
no longer be called.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
2012-02-12 10:11:32 +01:00
Peter Meerwald
a4958313fb omap3: fix comment typos
Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
2012-02-12 10:11:32 +01:00
Schuyler Patton
c8e5ba8034 AM3517: Changed default clock rate for AM3517
AM3517: Changed default clock rate for AM3517

Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows
the AM3517 to boot up at 600MHz instead of 500 MHz

Signed-off-by: Schuyler Patton <spatton@ti.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:31 +01:00
Govindraj.R
860004c103 OMAP4: clock-common: Move the usb dppl configuration to new func
usb dpll configuration is done only part of non-essential
dppl configuration however if CONFIG_USB_EHCI_OMAP is defined
we may have to configure usb dpll's for proper functioning
of usb modules. So move the usb dppl configuration to a new func.
and utilise the same during essential dpll configuration.

Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:31 +01:00
Govindraj.R
95f8791042 OMAP3+: Clock: Adding ehci clock enabling
Adding ehci clock enabling mechanism part of clock framework.
When essential clocks are enabled during init phase usb host
clocks can also be enabled from clock framework.

Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:31 +01:00
Govindraj.R
43b62393da ehci-omap: Clean up added ehci-omap.c
Clean up added ehci-omap.c and make it generic for re-use across
omap-soc having same ehci ip block. Also pass the modes to be configured
from board file and configure the ports accordingly. All usb layers
are not cache aligned, till then keep cache off for usb ops as ehci will use
internally dma for all usb ops.

* Add a generic common header ehci-omap.h having common ip block
  data and reg shifts.
* Rename and modify ehci-omap3 to ehci.h retain only conflicting
  sysc reg shifts remove others and move to common header file.
* pass the board data for beagle/panda accordinly to use
  ehci ports.

Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
2012-02-12 10:11:31 +01:00
Chander Kashyap
37bb6d89de ARM: EXYNOS: Add support for Exynos5 based SoCs
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:30 +01:00
Chander Kashyap
5e46f83cc3 Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:30 +01:00
Minkyu Kang
851db35e2d S5P: support generic watchdog timer
This patch adds support the generic watchdog timer for s5pc1xx and exynos4

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: HeungJun, Kim <riverful.kim@samsung.com>
2012-02-12 10:11:29 +01:00
HeungJun, Kim
77e490e225 ARMV7: Exynos4: Add supoort power for Exynos4
This patch adds power.h and SAMSUNG_BASE() macro for using Exynos4 power.

Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:29 +01:00
HeungJun, Kim
792be0aa80 ARMV7: Exynos4: Add watchdog.h for Exynos4
This patch add watchdog.h for Exynos4

Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:29 +01:00
Chander Kashyap
db68bc2c2d Exynos: Fix ARM Clock frequency calculation
Earliar ARM clock frequency was calculated by:
MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
It is fixed by calculating it as follows:
ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1)

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:28 +01:00
Chander Kashyap
e619a0de93 Exynos: PWM: Add TCMPB3 field in pwm structure
Add TCMPB3 field in pwm structure, earliar this was res1.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12 10:11:28 +01:00
Prafulla Wadaskar
96f5c4b2c9 bugfix: all Marvell specific build fails due to undefined reference to `get_ticks'
after http://patchwork.ozlabs.org/patch/136415/ was applied. All Marvell
build fails with below error

common/libcommon.o: In function `cread_line':
/home/uboot/src/u-boot-arm/common/main.c:717: undefined reference to `get_ticks'
/home/uboot/src/u-boot-arm/common/main.c:717: undefined reference to `get_tbclk'
/home/uboot/src/u-boot-arm/common/main.c:720: undefined reference to `get_ticks'

The same is fixed for Kirkwood, ARMADA100, pantheon and orion5x SoCs

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2012-02-12 10:11:28 +01:00
Michael Walle
679530278d arm, arm-kirkwood: disable l2c before linux boot
The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Wolfgang Denk <wd@denx.de>
2012-02-12 10:11:28 +01:00
Albert ARIBAUD
805ad7ee2d orion5x: add USB host ehci-marvell support
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-02-12 10:11:28 +01:00
Albert ARIBAUD
74d3442111 Remove kirkwood-specifics from marvell EHCI driver
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-02-12 10:11:27 +01:00
Albert ARIBAUD
a14bd41738 Rename ehci-kirkwood as ehci-marvell
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2012-02-12 10:11:27 +01:00
Jason Liu
0d8a749950 i.mx: i.mx5: update imx_get_mac_from_fuse function
FEC does not work on the i.mx51/53evk board, it will hangup
In:    serial
Out:   serial
Err:   serial
Net:

After bisect, it due to the following commit:
be252b6 net: imx: Add multi-FEC support for imx_get_mac_from_fuse
has change the imx_get_mac_from_fuse fucntion prototype, but fail
to update i.mx5, here it does it.

After apply this patch, u-boot works again on i.mx51/53 evk boards.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:27 +01:00
Fabio Estevam
82182720e7 mx28: Show CPU frequency
Showing CPU frequency during boot is useful information.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:26 +01:00
Helmut Raiger
fa47a28661 mmc: access mxcmmc from mx31 boards
This patch modifies mxcmmc.c to be used
not only by i.MX27 but also by i.MX31 boards.
Both use the same SD controller, but have different
clock set-ups.
The i.MX27 imx_get_XXXclock functions are made static to
generic.c and a public mxc_get_clock() function
is provided.  Pins, base address and prototypes for
an i.MX31 specific board_init_mmc() are provided.
Some of the i.MX27 clock getters are unused and marked
as such to avoid warnings (./MAKEALL -s mx27), but
the code was left in for future use.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:26 +01:00
Troy Kisky
4591f523df i.mx6: mx6x_pins: Fix uart txd definitions
The uart txd pad can also provide the rxd function. But it does not stop its
tx role. This could be used for a half duplex serial port.

Change names to reduce confusion.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
2012-02-12 10:11:26 +01:00
Heiko Schocher
2627c8c0a1 arm, davinci: add timer defines for tcr field
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
2012-02-12 10:11:23 +01:00
Heiko Schocher
3f84108b99 arm, davinci: add workaround for not resetting DMA bus and VPSS modules
The Buffer Logic of VPSS is Not Reset by System Reset Pin, see
http://www.ti.com/lit/er/sprz316b/sprz316b.pdf chapter Advisory 1.2.1
on page 9. Add workaroundcode proposed in the errata.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
2012-02-12 10:11:23 +01:00
Dechesne, Nicolas
f59021791b OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()
In 8775471bb, the call to timer_init() was removed from common code
and put in OMAP3 s_init() function. As a result the boot was broken
on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix
boot on all OMAP4 boards.

Signed-off-by: Nicolas Dechesne <n-dechesne@ti.com>
Tested-by: Robert P. J. Day <rpjday@crashcourse.ca>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
2012-02-12 10:11:23 +01:00
Tom Rini
0ae056510f OMAP3: Correct get_sdr_cs_offset mask
The function get_sdr_cs_offset reads the CS_CFG register in the SDRC
to determine where CS1 is mapped to.  make_cs1_contiguous() will set
CS1 to follow after CS0.  The CS_CFG register has values in bits 9:8
and 3:0 but we had erroneously been testing 5:4 and 3:0 resulting in
incorrect offsets on platforms with less than 128MB as 3:0 describe
128MB hunks and 9:8 describe 32MB offsets after the 128MB hunk.

Tested-by: Grant Erickson <marathon96@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-02-12 10:11:23 +01:00
Pali Rohár
204705111c arm: omap3: Define save_boot_params in lowlevel_init.S for SPL only
Wrap the function save_boot_params with CONFIG_SPL_BUILD.  This will
allow non-SPL boards to define their own save_boot_params functions
in U-Boot itself.

Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
2012-02-12 10:11:22 +01:00
Ben Gardiner
d652a344a0 arm, davinci: add PLL0 prediv to da850 lowlevel setup
The OMAP-L138 has a pre-divider available on PLL0.

Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Christian Riesch <christian.riesch@omicron.at>
CC: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
2012-02-12 10:11:22 +01:00
Simon Glass
bd29cb05f2 tegra2: Enable data cache
This enables the data cache on Tegra2 boards.

As discussed on the list, this is better off in the Tegra2 cpu code than in a
particular vendor directory. We should be safe turning on the cache for all
Tegra2 boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
cf06b13903 tegra: Add SDMMC support to funcmux
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
8a1133c607 tegra: Add I2C support to funcmux
Add support to funcmux for selecting I2C functions and programming
the pinmux appropriately.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
2faf1863de tegra: Add enum to select from available funcmux configs
We want to give a name to each available funcmux config. For now we just
use the pin group names (even through it is verbose) since there seems
to be nothing better.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Simon Glass
d693969daa tegra: Adjust funcmux config test to permit expansion
We want to support config options other than zero, so move the test to the
end to allow intermediate code to OK such a config.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Stephen Warren
9057e652c3 tegra2: Fix default RAM size selection in odmdata
A value of 0 in the odmdata RAM size field means default, which is 512MB
not 1GB. Fix this. For reference, see:

http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;\
f=arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h;\
h=1ec7010911454f19a5018952fd245785a62c59ad;\
hb=0e52d7fe25b11a656c376a37890be219470661fb

v2: New patch

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Stephen Warren
4850ab9a4f tegra2: Fix conflicting pinmux for UARTA
Tegra appears to boot with function UARTA pre-selected on mux
group SDB. If two mux groups are both set to the same function,
it's unclear which group's pins drive the RX signals into the
HW module. For UARTA, SDB certainly overrides group IRTX in
practice. To solve this, configure some alternative function on
SDB to avoid the conflict. Also, tri-state the group to avoid
driving any signal onto it until we know what's connected.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12 10:11:22 +01:00
Mike Frysinger
42c6e9ad1b Blackfin: easylogo: add lzma logos
The bf527-ezkit boards are getting too big to fit into their reserved
flash space, so we need to use a lzma compressed logo.

Since the video driver code is very similar, add lzma compressed support
to all of the Blackfin video drivers.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-02-03 20:44:54 -05:00
Wolfgang Denk
66714b1a6d Merge branch 'next' of git://git.denx.de/u-boot-video
* 'next' of git://git.denx.de/u-boot-video:
  ipu_common: Add ldb_clk for use in parenting the pixel clock
  ipu_common: Do not hardcode the ipu_clk frequency
  ipu_common: Rename MXC_CCM_BASE
  ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
  ipu_common: Only apply the erratum to MX51
  video: Rename CONFIG_VIDEO_MX5
  mx6: Allow mx6 to access the IPUv3 registers
  common lcd: minor coding style changes

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-18 10:47:03 +02:00
Thomas Chou
7dfb060291 nios2: move gd and bd into BSS
As suggested by Graeme Russ, move gd and bd data structrures
to BSS instead of calculating the locations around the stack
and heap.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-07-16 09:51:12 +08:00
Fabio Estevam
05d4df1d8a mx6: Allow mx6 to access the IPUv3 registers
Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:38 +02:00
Patil, Rachna
b4116ede36 ARM: AM33XX: Add i2c support
Add i2c driver board hookup for AM335X EVM

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Patil, Rachna <rachna@ti.com>
2012-01-23 11:57:31 +01:00
Graeme Russ
afd855d534 Merge branch 'staging' 2012-01-21 01:22:48 +11:00
Andreas Müller
137703b811 overo: add SPL support
* implementation based on ti beagleboard/omap3evm
* timing data and i2c workaround for revision 0 boards taken from x-loader
* run-tested with overo revision 0 and 1 / boot from NAND and SDcard
* run-tested with x-loader

Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:13 +01:00
Andreas Müller
761ca31e47 omap_rev_string: output to stdout
* avoid potential buffer overflows
* allow SPL-build not to output "Texas Instruments Revision detection unimplemented"

Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:13 +01:00
Andreas Müller
8775471bb3 OMAP SPL: call timer_init in s_init to make udelay work earlier
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
2012-01-16 08:40:12 +01:00
Chandan Nath
8a8f084e4f ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16 08:40:12 +01:00
Chandan Nath
876bdd6d46 ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:12 +01:00
Chandan Nath
fb072a3ead ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr and timer
register offset.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16 08:40:11 +01:00
Chandan Nath
f16da7466f ARM:AM33XX: Replace CONFIG_AM335X with CONFIG_AM33XX
This patch is added to replace CONFIG_AM335X symbol
with CONFIG_AM333XX for AM33XX platforms.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Thomas Weber <weber@corscience.de>
2012-01-16 08:40:11 +01:00
Nikita Kiryanov
715462dd7e omap3: make get_board_rev() function weak
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this function
weak.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16 08:40:11 +01:00
Aneesh V
fe7104b307 omap4: fix boot issue on ES2.0 Panda
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.

Commit 23e9f0723e
wrongly did this for CONTROL_EFUSE_1. Reverting
this and doing it for CONTROL_EFUSE_2.

Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Raúl Porcel <armin76@gentoo.org>
2012-01-16 08:40:11 +01:00
Christian Riesch
a601bed065 arm, davinci: Change byte order of RTC kick register values
Now the values in the defines agree with those in the manuals.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
2012-01-16 08:40:10 +01:00
Jason Liu
f2f7745825 imx: mx6q: add aipstz init for off platform periph
Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW):      0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP):      0 -> allows write accesses.
Trusted Protect(TP):    0 -> allows unstrusted master

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:10 +01:00
Zach Sadecki
8db9eff6c5 mx28: fix clearing of IRQs in power init
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used.  This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear.  Using the correct method to clear the IRQs fixes it.

Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-01-16 08:40:10 +01:00
Jason Liu
bd2e27c043 i.mx6:imx6q: allign MAC address with burned-in ordering
For the i.mx6q, the burned-in MAC address will be the following odering,

fuse: 0x620[7:0]   MAC_ADDR[7:0]     ---> mac[5]
fuse: 0x620[15:8]  MAC_ADDR[15:8]    ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16]   ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24]   ---> mac[2]
fuse: 0x630[7:0]   MAC_ADDR[39:32]   ---> mac[1]
fuse: 0x630[15:8]  MAC_ADDR[47:40]   ---> mac[0]

This patch also fix the error caculation for the fuse bank[0] address

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Fabio Estevam
5bcc6a8901 mx28: Let dram_init be common for mx28
Let dram_init function be a common function, so that other mx28 boards
can reuse it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-01-16 08:40:09 +01:00
Fabio Estevam
5cb525f3d2 mx28: Let imx_get_mac_from_fuse be common for mx28
Let imx_get_mac_from_fuse function be a common function, so that other
mx28 boards can reuse it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Fabio Estevam
be252b654a net: imx: Add multi-FEC support for imx_get_mac_from_fuse
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.

This feature is important on mx28 SoC for example that has two FEC ports.

Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Veli-Pekka Peltola
00699f847d mx28: remove omap specific config options
Config options for OMAP are not used with i.MX28 so remove dead code.

Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:08 +01:00
Jason Liu
ff167df51c i.mx: i.mx6q: Add the enet clock function
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:08 +01:00
Stefan Kristiansson
e0f1fd4c82 openrisc: Add library functions
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2012-01-13 21:16:48 +01:00
Stefan Kristiansson
272f84bbdf openrisc: Add cpu files
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2012-01-13 21:16:44 +01:00
Stefan Kristiansson
ca9d3ab5c7 openrisc: Add architecture header files
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2012-01-13 21:16:37 +01:00
Wolfgang Denk
670c24f6f3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks
2012-01-13 20:38:49 +01:00
Paul Gortmaker
3dc23c7c30 fsl_lbc: add printout of LCRR and LBCR to local bus regs
It can be handy to have these in the output when trying to
debug odd behaviour.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-13 12:56:06 -06:00
Joe Hershberger
4b56579388 mpc83xx: Add a GPIO driver for the MPC83XX family
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Joe Hershberger
365d607033 gpio: Replace ARM gpio.h with the common API in include/asm-generic
ARM boards should use the generic GPIO API
This means changing gpio to unsigned type
Remove the unused gpio_toggle() function which is not part of the API
Comment that free should not modify pin state

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and
extended to the new mxs_gpio.c.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-01-09 20:10:32 -06:00
Graeme Russ
a1d57b7aba x86: Convert board_init_f_r to a processing loop
Create an init function array for board_init_f_r - This finalises the
migration to a purely array based initialisation mechanism

Also tweak a few comments while we are at it so everything is 'correct'

--
Changes for v2:
 - Renamed to a more apt name
 - Fix bug in set_reloc_flag_r
 - Re-instate gd->flags = boot_flags; in board_init_f
 - Added commit message
2012-01-04 22:53:14 +11:00
Graeme Russ
d47ab0ecde x86: Split init functions out of board.c
This patch moves towards reducing board.c to simply a set of init cores for
the three initialisation phases (Flash, Flash/RAM, and RAM), a set of three
init function arrays and a init function array processing function
2012-01-04 22:41:32 +11:00
Graeme Russ
b156ff09aa x86: Move relocation code out of board.c 2012-01-04 22:39:06 +11:00
Graeme Russ
8e18e6e173 x86: Move setup_pcat_compatibility() out of board.c
This function simply does not belong in board.c

--
Changes for v2:
 - Added commit message
2012-01-04 22:37:20 +11:00
Graeme Russ
d13640b7c4 x86: Move do_go_exec() out of board.c
--
Changes for v2:
 - None
2012-01-04 22:35:20 +11:00
Graeme Russ
b843f31193 CHECKPATCH: arch/x86/lib/* 2012-01-04 22:33:59 +11:00
Graeme Russ
58c7a6751d x86: Tweak IDT and GDT for alignment and readability
--
Changes for v2:
 - Renamed to better reflect nature of changes
2012-01-04 22:29:40 +11:00
Graeme Russ
98f1fa9fd4 x86: Allow cache before copy to RAM
--
Changes for v2:
 - None
2012-01-04 22:25:53 +11:00
Graeme Russ
d653244b12 x86: Create weak init_cache() and default enable_caches() functions
--
Changes for v2:
 - Tweaked commit title
2012-01-04 22:19:01 +11:00
Graeme Russ
3766bb33a5 x86: Set GD_FLG_RELOC after entering in-RAM copy of U-Boot
--
Changes for v2:
 - None
2012-01-04 22:18:36 +11:00
Graeme Russ
9e6c572ff0 x86: Use fs for global data
Use the base address of the 'F' segment as a pointer to the global data
structure. By adding the linear address (i.e. the 'D' segment address) as
the first word of the global data structure, the address of the global data
relative to the 'D' segment can be found simply, for example, by:

	fs movl 0, %eax

This makes the gd 'pointer' writable prior to relocation (by reloading the
Global Desctriptor Table) which brings x86 into line with all other arches

NOTE: Writing to the gd 'pointer' is expensive (but we only do it
twice) but using it to access global data members (read and write) is
still fairly cheap

--
Changes for v2:
 - Rebased against changes made to patch #3
 - Removed extra indent
 - Tweaked commit message
2012-01-04 22:17:24 +11:00
Graeme Russ
240ab5aa21 x86: Rework relocation calculations
This commit introduces no functional changes - It simply re-arranges the
calculations so that adding to them in future commits will be cleaner

--
Changes for v2:
 - Fixed typo in title
 - Added commit message
2012-01-04 22:17:22 +11:00
Graeme Russ
f48dd6fc6c x86: Simplify Flash-to-RAM code execution transition
Move the relocation offset calculation out of assembler and into C. This
also paves the way for the upcoming init sequence simplification by adding
the board_init_f_r flash to RAM transitional function

--
Changes for v2:
 - Added commit message
 - Minor adjustment to new stack address comment
2012-01-04 22:17:20 +11:00
Graeme Russ
74bfbe1ba5 x86: Rework Global Descriptor Table loading
The inline assembler is ugly and uses hard coded magic numbers. Make it more
elegant to allow cleaner implementation of future GDT related patches. The
compiler seems smart enough to generate the same code anyway

--
Changes for v2:
 - Rebased against revised patch #3
 - Use GDT size define instead of magic number
 - Added commit message
2012-01-04 22:17:19 +11:00
Graeme Russ
109ad143f8 x86: Remove GDR related magic numbers
--
Changes for v2:
 - Use an enum
 - Add defined for GDT size (previously added in patch 7)
 - Use X86_ namespace (as per Linux headers)
2012-01-04 21:05:09 +11:00
Graeme Russ
1176a7067a x86: Speed up copy-to-RAM and clear BSS operations
The implementations of memcpy and memset are now the optimised versions
from glibc, so use them instead of simple copy loops

--
Changes for v2:
 - Removed unneeded brackets
2012-01-04 21:05:00 +11:00
Graeme Russ
b2c2a03842 x86: Import glibc memcpy implementation
Taken from glibc version 2.14.90

--
Changes for v2:
 - None
2012-01-02 03:58:46 +11:00
Simon Glass
bb6997f840 tegra: Add support for UART init in cpu board.c
We add a way of initialising the selected of UARTs prior to relocation.
Boards can use the board_init_uart_f() instead of repeating this code
themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
b5a5b35197 tegra: Add a function mux feature
funcmux permits selection of config options for particular peripherals,
such as the pins that are used for that peripheral, if there are several
options.

Add UART selection to start with.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
8442fd3c6a tegra: add clock_ll_start_uart() to enable UART prior to reloc
Most boards will want to enable a UART early. This function provides
that feature in Tegra architecture code so the code does not need to be
copied on every board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
905ed41aad tegra: Move clock_early_init() to arch_cpu_init()
The clock init is not board specific, so move it into
the cpu code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Simon Glass
ccdd6eaecb tegra: Move cpu_init_cp15() to arch_cpu_init()
This call is more of an architecture requirement than a board
one, so move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:32 +01:00
Thierry Reding
977a39e600 tegra2: Move tegra2_mmc_init() prototype to public header.
tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:31 +01:00
Thierry Reding
09743ba635 tegra2: Always build with USE_PRIVATE_LIBGCC=yes.
The AVP on Tegra2 doesn't boot properly when U-Boot is linked against
the GCC provided libgcc. To work around this, always build and link
against a private libgcc for Tegra2-based boards.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:31 +01:00
Simon Glass
cb93481268 tegra2: Implement SPI / UART GPIO switch
The Tegra2 Seaboard has the unfortunate feature that SPI and the console
UART are multiplexed on the same pins. We need to switch between one
and the other during SPI and console activity.

This new file implements a switch and keeps track of which peripheral
owns the pins. It also flips over the controlling GPIO as needed

Since we are adding a second file to board/nvidia/common, we create
a proper Makefile there and remove the direct board.o include from
board/nvidia/seaboard/Makefile

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24 10:23:31 +01:00
Tom Warren
9112ef8d89 tegra2: spi: Add SPI driver for Tegra2 SOC
This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-12-24 10:23:30 +01:00
Christian Riesch
8f7431400a arm, davinci: Fix build warnings for cam_enc_4xx
This patch fixes a build warning for the cam_enc_4xx board introduced by
commit d6ec0c0dfc70447cf615ae80a952da81f73f16b4:

spl.c:35:13: warning: 'gdata' defined but not used
spl.c:36:13: warning: 'bdata' defined but not used

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
2011-12-24 10:23:30 +01:00
Christian Riesch
620fd27cfa arm, davinci: Add SPL support for DA850 SoCs
This code adds an SPL for booting from SPI flash on DA850 SoCs.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-24 10:23:30 +01:00
Wolfgang Denk
bfcc40bb09 Merge branch 'next' of ../next
* 'next' of ../next:
  mkenvimage: Add version info switch (-V)
  mkenvimage: Fix getopt() error handling
  mkenvimage: Fix some typos
  phy: add Micrel KS8721BL phy definition
  net: introduce per device index
  mvgbe: remove setting of ethaddr within the driver
  x86: Add support for specifying an initrd with the zboot command
  x86: Refactor the zboot innards so they can be reused with a vboot image
  x86: Add infrastructure to extract an e820 table from the coreboot tables
  x86: Add support for booting Linux using the 32 bit boot protocol
  x86: Clean up the x86 zimage code in preparation to extend it
  x86: Import code from coreboot's libpayload to parse the coreboot table
  x86: Initial commit for running as a coreboot payload
  CHECKPATCH: ./board/esd/hh405/logo_320_240_8bpp.c
  CHECKPATCH: ./board/esd/hh405/logo_1024_768_8bpp.c
  CHECKPATCH: ./board/esd/hh405/logo_320_240_4bpp.c
  CHECKPATCH: ./board/esd/hh405/logo_640_480_24bpp.c
  CHECKPATCH: ./board/esd/apc405/logo_640_480_24bpp.c
  CHECKPATCH: ./board/esd/voh405/logo_320_240_4bpp.c
  CHECKPATCH: ./board/esd/voh405/logo_640_480_24bpp.c
  CHECKPATCH: ./board/esd/hh405/fpgadata.c
  CHECKPATCH: ./board/esd/pci405/fpgadata.c
  CHECKPATCH: ./board/esd/tasreg/fpgadata.c
  CHECKPATCH: ./board/esd/apc405/fpgadata.c
  CHECKPATCH: ./board/esd/voh405/fpgadata.c
  CHECKPATCH: ./board/esd/ash405/fpgadata.c
  CHECKPATCH: ./board/esd/dasa_sim/fpgadata.c
  CHECKPATCH: ./board/esd/ar405/fpgadata_xl30.c
  CHECKPATCH: ./board/esd/ar405/fpgadata.c
  CHECKPATCH: ./board/esd/plu405/fpgadata.c
  CHECKPATCH: ./board/esd/wuh405/fpgadata.c
  CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405.c
  CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405ab.c
  CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci4052.c
  CHECKPATCH: ./board/esd/canbt/fpgadata.c
  CHECKPATCH: ./board/esd/du405/fpgadata.c
  CHECKPATCH: ./board/esd/cpciiser4/fpgadata.c
  CHECKPATCH: ./board/dave/PPChameleonEVB/fpgadata.c
  avr32:mmu.c: fix printf() length modifier
  fat.c: fix printf() length modifier
  cmd_sf.c: fix printf() length modifier
  Make printf and vprintf safe from buffer overruns
  vsprintf: Move function documentation into header file
  Add safe vsnprintf and snprintf library functions
  Move vsprintf functions into their own header

Conflicts:
	tools/mkenvimage.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-12-23 20:53:58 +01:00
Tom Warren
e2132c29d8 arm: Tegra: fix undefined instruction hang immediately after reset
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't
execute on Tegra, due to the AVP (ARM7TDI) not having a CP15.
Result was an undefined instruction hang just after reset.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Aneesh V <aneesh@ti.com>
2011-12-21 20:36:22 +01:00
Sven Schnelle
bf0b631343 AVR32: fix timer_init() function
timer_init() now returns an int (the error code) instead of void.
This makes compilation fail with:

interrupts.c:111: error: conflicting types for 'timer_init'
/home/svens/u-boot/u-boot/include/common.h:246: error: previous
declaration of 'timer_init' was here
make[1]: *** [interrupts.o] Error 1

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-12-20 23:10:04 +01:00
Heiko Schocher
3ea11cacdd arm, fdt: update ethernet mac address before booting Linux
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Gerald van Baren <gvb.uboot@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-12-19 17:52:44 +01:00
David Müller (ELSOFT AG)
9fd6826611 add print_cpuinfo to s3c24x0
Hello

This patch adds support for "print_cpuinfo" on Samsung s3c24x0
based targets. If activated by "#define CONFIG_DISPLAY_CPUINFO", the
chip ID and the 3 main cpu frequencies will be displayed.

Dave

Signed-off-by: David Müller <d.mueller@elsoft.ch>
2011-12-19 17:52:44 +01:00
Chris Lalancette
df65a3fe35 omap4_panda: Initialize the USB phy
During misc_init_r, make sure to setup the clocks
properly for the USB hub on the pandaboard.  With
this in place, the USB hub and the ethernet works
on the pandaboard.

Signed-off-by: Chris Lalancette <clalancette@gmail.com>
Acked-by: Aneesh V <aneesh@ti.com>
2011-12-19 17:52:44 +01:00
Manfred Rudigier
c005d6b193 davinci: Fixed wrong timebase clock frequency.
Signed-off-by: Manfred Rudigier <manfred.rudigier@omicron.at>
2011-12-19 17:52:43 +01:00
Ilya Yanok
076cd49ad1 arm926ejs: remove noop flush_dcache_all function
Commit 2f3427c added noop cache functions implementation for arm926ejs
to fix compilation of drivers depending on these functions (DaVinci
EMAC in particular).

Unfortunately, the bug was introduced: noop implementation calls
dcache_disable which calls flush_dcache_all which in turn calls
dcache_disable thus creating an infinite loop.

This patch removes noop implementation for flush_dcache_all, we already
have default one in arch/arm/lib/cache.c and it should be used instead.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
2011-12-19 17:52:43 +01:00
Wolfgang Denk
6b62b9a31d Coding Style cleanup
Fix trailing white space, indentation by spaces instead of TABs,
excessive blank lines, trailing blank lines.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-12-19 12:03:40 +01:00
Gabe Black
6f9d9986d5 x86: Add support for specifying an initrd with the zboot command
This change finishes plumbing the initrd support built into the zboot
mechanism out to the command interface.

It also fixes a bug in the command declaration where the kernel size could
be passed as an optional second parameter but not enough arguments were
allowed.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:17 +11:00
Gabe Black
69370d144a x86: Refactor the zboot innards so they can be reused with a vboot image
If vboot successfully verifies a kernel, it will leave it in place and
basically ready to boot. The zeropage table which is part of the x86 boot
protocol is at the end of the kernel, though, instead of the beginning, and
because the image is already in place there's no need to copy it around.
This change refactors the code which implements the zboot command so that
the configuration of the zeropage table and loading the pieces of the
kernel into memory are done separately. Also, because the command line goes
before the zeropage table in vboot which is somewhat incompatible with the
normal protocol, where to put the command line is a now a parameter instead
of being hard coded.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:16 +11:00
Gabe Black
f08fa7a201 x86: Add infrastructure to extract an e820 table from the coreboot tables
Also approximate the size of RAM using the largest RAM address available
in the tables. There may be areas which are marked as reserved which are
actually at the end of RAM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:16 +11:00
Gabe Black
233dbc1194 x86: Add support for booting Linux using the 32 bit boot protocol
This change conditionally modifies the zboot command so that it can use the
32 bit boot protocol. This is necessary because the 16 bit realmode entry
point assumes that it can call BIOS services which neither coreboot nor
u-boot provide.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:16 +11:00
Gabe Black
d3a2bc3fd1 x86: Clean up the x86 zimage code in preparation to extend it
This change cleans up some formatting issues in the zimage handling code, and
converts it from using offsets added to a base pointer to using the available
structure definitions which were already being included.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:16 +11:00
Gabe Black
63f559cd12 x86: Import code from coreboot's libpayload to parse the coreboot table
This change also forces the lib_sysinfo structure to be in the .data
section. Otherwise it ends up in the .bss section. U-boot assumes that it
doesn't need to copy it over during relocation, and instead fills that
whole section with zeroes. If we really were booting from ROM that would be
appropriate, but we need some information from the coreboot tables (memory
size) before then and have to fill that structure before relocation. We
skirt u-boot's assumption by putting this in .data where it assumes there
is still read only but non-zero data.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:15 +11:00
Gabe Black
ef5a5b0049 x86: Initial commit for running as a coreboot payload
Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:15 +11:00
Andreas Bießmann
87c24e2580 avr32:mmu.c: fix printf() length modifier
avr32 uses unsigned long addresses, fix the printf() length modifier for that
fact.

Before this patch following warning occours:

---8<---
mmu.c: In function 'mmu_init_r':
mmu.c:25: warning: format '%08x' expects type 'unsigned int', but argument 2 has type 'uintptr_t'
--->8---

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
cc: Mike Frysinger <vapier@gentoo.org>
cc: Thomas Chou <thomas@wytron.com.tw>
cc: Reinhard Meyer <u-boot@emk-elektronik.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-12-17 23:57:18 +01:00
Wolfgang Denk
8b0affecb9 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  USB: Use (get|put)_unaligned for accessing wMaxPacketSize
  usb:gadget:s5p Enable the USB Gadget framework at Exynos4210 (C210 Universal)
  README: add documentation for CONFIG_USB_ULPI*
  USB: ULPI: increase error case verbosity
  USB: ULPI: clean a mixup of return types
  USB: ULPI: switch argument type from u8 to unsigned
2011-12-17 20:51:16 +01:00
Lukasz Majewski
ddc7e541ae usb:gadget:s5p Enable the USB Gadget framework at Exynos4210 (C210 Universal)
This commit enables support for USB Gadgets on the Exynos4210 (C210 Universal)
reference target.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
CC: Remy Bohmer <linux@bohmer.net>
2011-12-16 21:37:17 +01:00
Jerry Huang
509adc8b77 powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
In the current u-boot code, the value of these fields are the reserved
value (0b100), through the signal integrity measurement on freescale's
board with these reserved setting, the signal eye is out of the recommended
spec for non-transition amplitude at 500mV nominal.
According to the errata for MPC8379E, we should make a change to the
recommended setting from essentially nothing at this time to 0b001 for SATA.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-12-12 18:33:39 -06:00
Kumar Gala
3b2001105f powerpc/bootm: Flush ramdisk and device tree image when booting on MP
We already flush the kernel image after we've loaded it to ensure
visiblity to the other cores.  We need to do the same thing for the
ramdisk and device tree images.  In AMP boot scenarios we might not be
HW cache coherent with the secondary core that we are loading and
setting the ramdisk and device tree up for.  Thus we need to ensure
we've flushed the regions of memory utilized by ramdisk and device tree
so the loadding and any modifications (from decompression or fdt updates)
are made visible to the secondary cores.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-12 08:17:52 +01:00
Wolfgang Denk
b2eb7d9bc6 Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb:
  USB: efikamx: Enable USB on EfikaMX and EfikaSB
  USB: Add generic ULPI layer and a viewport
  USB: EHCI: Allow EHCI post-powerup configuration in board files
  USB: mx51evk: add end enable USB host support on port 1
  USB: mx53loco: add end enable USB host support on port 1
  USB: MX5: Add MX5 usb post-init callback
  USB: MX5: Abstract out mx51 USB pixmux configuration
  USB: MX5: add generic USB EHCI support for mx51 and mx53
  USB: MX5: add helper functions to enable USB clocks
  usb:gadget:s5p Enable the USB Gadget framework at GONI
  usb:gadget:s5p USB Device Controller (UDC) implementation
  ehci: speed up initialization
  usb: add help for missing start subcommand
  cosmetic: remove excess whitespace from usb command help
  usb: align usb_endpoint_descriptor to 16-bit boundary
  usbtty: init endpoints prior to startup events
  pxa: convert pxa27x_udc to use read and write functions
  pxa: activate the first usb host port on pxa27x by default
  pxa: fix usb host register mismatch
  ehci-fsl: correct size of ehci caplength
  USB: Add usb_event_poll() to get keyboards working with EHCI
  USB: gadaget: add Marvell controller support
  USB: Fix complaints about strict aliasing in OHCI-HCD
  USB: Drop dead code from usb_kbd.c
  USB: Rework usb_kbd.c
  USB: Add functionality to poll the USB keyboard via control EP
2011-12-12 07:58:58 +01:00
Wolfgang Denk
4f1a2cd163 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  arm: add __aeabi_unwind_cpp_pr1() function to avoid linker complaints
  post: fix compile issue for post tests on kirkwood
2011-12-12 07:56:41 +01:00
Wolfgang Grandegger
5d2947a3fc USB: MX5: add helper functions to enable USB clocks
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>

V2: Fix spacing in crm_regs.h
2011-12-11 14:49:25 +01:00
Lukasz Majewski
a954da2902 usb:gadget:s5p Enable the USB Gadget framework at GONI
This commit enables support for USB Gadgets on the GONI
reference target.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
2011-12-11 14:44:49 +01:00
Stefan Herbrechtsmeier
bdbcdc897f pxa: convert pxa27x_udc to use read and write functions
Signed-off-by: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Remy Bohmer  <linux@bohmer.net>
2011-12-11 14:41:14 +01:00
Stefan Herbrechtsmeier
66a181864d pxa: activate the first usb host port on pxa27x by default
The pxa27x has 3 usb host ports. Activate all by default.

Signed-off-by: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Remy Bohmer  <linux@bohmer.net>
2011-12-11 14:41:05 +01:00
Stefan Herbrechtsmeier
1c0a14ebb7 pxa: fix usb host register mismatch
Signed-off-by: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Remy Bohmer  <linux@bohmer.net>
2011-12-11 14:40:54 +01:00
Wolfgang Grandegger
953209bf5e arm: add __aeabi_unwind_cpp_pr1() function to avoid linker complaints
With the ELDK 5.1 (beta) "armv7a" toolchain I'm get the following
build failure:

  $ ./MAKEALL mx51evk
  ...
  /opt/eldk-5.1/armv7a/sysroots/arm-linux-gnueabi/usr/lib/arm-linux-
  gnueabi/4.6.1/libgcc.a(bpabi.o):(.ARM.exidx+0x0): undefined
  reference to `__aeabi_unwind_cpp_pr1'
  make: *** [u-boot] Error 1

This patch fixes the issue similar to commit
d442b6e7ad6a86e2fd0e6297291fe8872ff26fc6 but I don't know if it's
general enough or if it does harm when using other toolchains.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2011-12-11 13:56:57 +01:00
Andreas Bießmann
f8d2c65fd9 sandbox: fix compiling of cpu/os.c
U-boot itself generally builds with -nostdinc.  This is because the
bootloader needs to be completely standalone.  In the sandbox arch
though, we need a little bit of code to glue the u-boot world to the
host operating system, and we need to be able to access the host
libc's headers in order to do so.

Currently, we're using -I/usr/include to workaround the global
-nostdinc, but that doesn't work for everyone and for all headers.
Instead, let's filter out -nostdinc when building the os.c code.

Without this patch, some distros hit errors such as:
---8<---
In file included from /usr/include/fcntl.h:27:0,
                 from os.c:22:
/usr/include/features.h:323:26: fatal error:
     bits/predefs.h: No such file or directory
--->8---

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-10 17:56:37 -05:00
Matthias Weisser
d99a6874f5 sandbox: Add timer simulation
Making sleep command work

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-10 17:54:04 -05:00
Matthias Weisser
21899b1085 sandbox: Add improved RAM simulation
Using mmap to allocate memory from the OS for RAM simulation we can use
u-boot own malloc implementation.

Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-10 17:54:04 -05:00
Christian Riesch
e21b3dfb0a arm, davinci: Use lldiv for the 64-bit divisions in timer.c
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2011-12-10 23:14:01 +01:00
Marek Vasut
8ba1604d34 M28: Cleanup memsize.o OOT build
The current way memsize.c is built just made a symlink into the directory
with SPL and then compiled it like any other file there. This was bad as that
broke the out-of-tree build.

The new way introduced in this patch uses the standard spl/Makefile methods
(CONFIG_SPL_LIBCOMMON_SUPPORT / CONFIG_SPL_LIBGENERIC_SUPPORT) to let files in
common/ be built. Because common/Makefile says memsize.c is always built (SPL
and non-SPL build), this fixes our issue with memsize.c out-of-tree build.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2011-12-09 17:30:10 +01:00
Marek Vasut
c944a3ef82 i.MX28: Move SPL to arch/arm/cpu/arm926ejs/mx28
This moves SPL to common location so it can be reused by multiple boards. Also,
this commit adjusts M28 SoM to avoid breakage due to the move.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2011-12-09 17:30:10 +01:00
Jason Liu
23608e23fd i.mx: add the initial support for freescale i.MX6Q processor
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
2011-12-09 17:30:10 +01:00
Jason Liu
18936ee2ad i.mx: introduce the armv7/imx-common folder
In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
  added but just fix the checkpatch errors in the old file and remove
  the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-12-09 17:30:10 +01:00
Chander Kashyap
393cb36199 S5PC2XX: Rename S5pc2XX to exynos
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.

In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-12-09 17:30:09 +01:00
Simon Glass
7f8c070ff9 tegra2: Don't use board pointer before it is set up
In board_init_f() the gd->bd pointer is not valid when dram_init() is called.
This only avoids dying because DRAM is at zero on Tegra2. The common ARM
routine sets up the banks in the same way anyway, so we can just remove this
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
e81cdc0350 tegra2: Remove unneeded 'dynamic ram size' message
This message is not required, since it is followed by an 'official' U-Boot
message.

U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23)

TEGRA2
Board: NVIDIA Seaboard
dynamic ram_size = 1073741824
DRAM:  1 GiB

becomes:

TEGRA2
Board: NVIDIA Seaboard
DRAM:  1 GiB

This is a separate commit since it changes behavior.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
e75119d278 tegra2: Remove unneeded boot code
Since we have cache support built in we can remove Tegra's existing cache
initialization code amd other related dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
80433c9ac6 arm: Move CP15 init out of cpu_init_crit()
Some SOCs have do not start up with their 'main' CPU. The first U-Boot
code may then be executed with a CPU which does not have a CP15, or not a
useful one.

Here we split the initialization of CP15 into a separate call, which can
be performed later if required.

Once the main CPU is running, you should call cpu_init_cp15() to perform
this init as early as possible.

Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not
need to change, this CP15 init is still skipped in that case. The only
impact for these boards is that the cpu_init_cp15() will be available
even if it is never used on these boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
210576fc5e tegra2: Simplify tegra_start() boot path
The Tegra2 boot path is more complicated than it needs to be. Since we want
to move to building most of U-Boot with ARMv7 and only a small part with
ARMv4T (for AVP) it should be as simple as possible.

This makes tegra2_start() into a simple function which either does AVP
init or A9 init depending on which core is running it. Both cores now
following the same init path, beginning at _start, and the special Tegra2
boot path code is no longer required.

Only two files need to be built for ARMv4T, and this is handled in the
Tegra2 CPU Makefile.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:09 +01:00
Simon Glass
e43d6ed932 tegra2: Add arch_cpu_init() to fire up Cortex-A9
We want to move away from a special Tegra2 start-up, and just use
arch_cpu_init() instead. However, if we run board_init_f() from boot
we need to build it for ARMv4T, since the Tegra's AVP start-up CPU
does not support ARMv7.

The effect of this is to do the AVP init earlier, and in
arch_cpu_init(), rather that board_early_init_f().

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09 17:30:08 +01:00
Simon Glass
13119bc9fb Fix warnings in arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
Sorry if this is already fixed somewhere - I could not find it.

This fixes these warnings:

usb_ohci.c: In function 'submit_control_msg':
usb_ohci.c:1081: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1081: note: initialized from here
usb_ohci.c:1084: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1084: note: initialized from here
usb_ohci.c:1087: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1087: note: initialized from here

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-12-09 10:32:49 +01:00
Wolfgang Denk
d3042862f6 arch/mips/lib/board.c: Fix GCC 4.6 build warning
Fix:
board.c: In function 'board_init_r':
board.c:262:8: warning: unused variable 's' [-Wunused-variable]

(raised for configurations without ethernet support like
vct_premium_small)

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2011-12-08 21:01:15 +01:00
Wolfgang Denk
cc257e42f3 arch/mips/lib/board.c: make (mostly) checkpatch clean
Fix all errors and all warnings except for "externs should be avoided"
which could require more extensive changes.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2011-12-08 21:01:11 +01:00
Kyle Moffett
01baa05643 powerpc: Minimal private libgcc to build on Debian
Standard Debian powerpc and powerpcspe systems only include hard-float
libgcc in their native compilers, which causes scary build warnings when
building U-Boot.

Debian and other PowerPC-supporting distributions used to provide libgcc
and other libraries in a "nof" (soft-float) form in the "multilib"
packages.  As they were completely unused by the distribution and
therefore tended to be very buggy it was decided to save some time on
the part of the maintainers and build-servers by removing them.

Admittedly, right now the linker warnings do not indicate any problems,
as the included routines do not use any floating point at all.

The concern is that if floating-point code were ever added it might
cause hard-float code to be unexpectedly included in U-Boot without
generating a hard error.  This would cause unexplained crashes or
indeterminate results at runtime.

The easiest way to resolve this is to borrow the routines that U-Boot
needs from the Linux kernel, which has the same issue.

Specifically, the routines are: _ashldi3(), _ashrdi3(), and _lshrdi3().
They were borrowed from arch/powerpc/kernel/misc_32.S as of v2.6.38-rc5,
commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, and are GPLv2+.

The Makefile framework was copied from the U-Boot ARM port.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Stefan Roese <sr@denx.de>
2011-12-07 23:04:32 +01:00
Wolfgang Denk
1086c5d6f8 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/83xx: fix sdram initialization for keymile boards
  powerpc/mpc83xx: cleanup makefile for mpc83xx
2011-12-07 23:01:26 +01:00
Stefan Roese
ce2acd371c ppc4xx: Remove usbdev.c
As this "driver" doesn't seem to be really used, let's remove
it completely.

Signed-off-by: Stefan Roese <sr@denx.de>
2011-12-07 20:00:40 +01:00
Anatolij Gustschin
e8f473548a arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings
Fix:
clocks.c: In function 'setup_post_dividers':
clocks.c:175: warning: comparison is always true due to limited range of
data type
clocks.c:177: warning: comparison is always true due to limited range of
data type
clocks.c:179: warning: comparison is always true due to limited range of
data type
clocks.c:181: warning: comparison is always true due to limited range of
data type
clocks.c:183: warning: comparison is always true due to limited range of
data type
clocks.c:185: warning: comparison is always true due to limited range of
data type
clocks.c:187: warning: comparison is always true due to limited range of
data type
clocks.c:189: warning: comparison is always true due to limited range of
data type

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
2011-12-06 23:59:40 +01:00
Anatolij Gustschin
164a750789 arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings
Fix:
clocks-common.c: In function 'setup_dplls':
clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:40 +01:00
Anatolij Gustschin
b0a86a27ee arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings
Fix:
spl.c: In function 'jump_to_image_no_args':
spl.c:103: warning: assignment makes pointer from integer without a cast
spl.c:105: warning: dereferencing type-punned pointer will break
strict-aliasing rules

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:40 +01:00
Stefano Babic
40f6fffee5 MX: serial_mxc: cleanup removing nasty #ifdef
The serial driver for iMX SOCs is continuosly changed if a
new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port>
defines were used only to find the base address for the selected UART.
Instead of that, move the base address to the board configuration
file and drop all #ifdef from driver.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Helmut Raiger <helmut.raiger@hale.at>
CC: John Rigby <jcrigby@gmail.com>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-12-06 23:59:40 +01:00
Marek Vasut
aa72e43bb7 MXS: Add static annotations to dma driver
Some functions were internal to the apbh dma driver, so annotate them static.
Some of the functions weren't used at all so drop them. This makes the U-Boot
binary smaller by about 1500 bytes.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-12-06 23:59:40 +01:00
Simon Glass
5acc907294 mx5: Correct a warning in clock.c
This corects the warning below, obtained with my gcc 4.6 compiler.

arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll':
arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod'

I am not able to test this on MX5x hardware, but it does improve the
MAKEALL output for me. You may already have a similar patch, but I cannot
see it on the list.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-12-06 23:59:39 +01:00
Tom Rini
ee08a8260a OMAP3: Add SPL_BOARD_INIT hook
Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c.  OMAP4
doesn't need i2c enabled in SPL.  Enable SPL_BOARD_INIT on devkit8000.

Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:39 +01:00
Tom Rini
673283f3fc OMAP3: Add SPL support to omap3_evm
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
75c57a3570 OMAP3: Add SPL support to Beagleboard
This introduces 200MHz Micron parts timing information based on x-loader
to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation.  The memory init
logic is also based on what x-loader does in these cases.  Note that
while previously u-boot would be flashed in with SW ECC in this case it
now must be flashed with HW ECC.  We also change CONFIG_SYS_TEXT_BASE to
0x80100000.

Cc: Dirk Behme <dirk.behme@gmail.com>
Beagleboard rev C5, xM rev A:
Tested-by: Tom Rini <trini@ti.com>
Beagleboard xM rev C:
Tested-by: Matt Ranostay <mranostay@gmail.com>
Beagleboard rev B7, C2, xM rev B:
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
4e647e1207 OMAP3 SPL: Add identify_nand_chip function
A number of boards are populated with a PoP chip for both DDR and NAND
memory.  Other boards may simply use this as an easy way to identify
board revs.  So we provide a function that can be called early to reset
the NAND chip and return the result of NAND_CMD_READID.  All of this
code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
9ae0d55074 OMAP3 SPL: Rework memory initalization and devkit8000 support
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework.  In SPL we try and initialize both CS0 and CS1.

Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
fc41ba1e2b OMAP3: Suffix all Micron memory timing parts with their speed
Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
1be1433b83 OMAP3: Add optimal SDRC autorefresh control values
This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks.  We switch to using this
to provide the default 165MHz value.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
14ca3dee80 omap3: mem: Add MCFG helper macro
This adds an MCFG macro to calculate the correct value, similar to
the ACTIMA/ACTIMB macros and adds a comment that all of the potential
values here are documented in the TRM.  Then we convert the Micron
value to use this macro.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
50e7ff0369 OMAP3: Remove get_mem_type prototype
This function doesn't exist for omap3

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
3bd8437dcc OMAP3: Change mem_ok to clear again after reading back
It's possible to need to call this function on the same banks multiple
times so we want to be sure that 'pos A' is cleared out again at the
end.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
2a04e85870 OMAP3: Add a helper function to set timings in SDRC
Since we go through the sequence to setup the SDRC timings more than
once, break this logic out into its own function and have that function
call mem_ok() to make sure the memory is usable.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:38 +01:00
Tom Rini
5f862b7179 OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
We update the comment in make_cs1_contiguous() to be a little bit
more clear (it's been copy/pasted from other silicons) and then
explain in dram_init() why we need to always try this.

Note that in the previous behavior we were always calling this on
boards that never had cs1 populated anyhow so making sure we do
this always is fine and will correct things like omap3evm detecting
an invalid amount of memory (384MB).

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:37 +01:00
Tom Rini
b7eb9e7895 omap3: mem: Comment enable_gpmc_cs_config more
Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.

Signed-off-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:37 +01:00
Christian Riesch
5cb939fb04 arm: printf() is not available in some SPL configurations
This patch avoids build breakage for SPLs that do not support printf.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-12-06 23:59:37 +01:00
Heiko Schocher
5b51e7f3ca arm, davinci: move misc function in arch tree
move the board/davinci/common/misc.c file to
arch/arm/cpu/arm926ejs/davinci/misc.c, so all
davinci boards can use this functions.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Christian Riesch <christian.riesch@omicron.at>
2011-12-06 23:59:37 +01:00
Heiko Schocher
7f34b1163a arm, davinci, da850: add uart1 tx rx pinmux config
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Tom Rini <trini@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Christian Riesch <christian.riesch@omicron.at>
2011-12-06 23:59:37 +01:00
Heiko Schocher
b5ce18a235 arm, davinci: move davinci_rtc struct to hardware.h
move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h
and add RTC_KICK0R_WE, RTC_KICK1R_WE defines,
so they are global useable.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
2011-12-06 23:59:37 +01:00
Christian Riesch
65204715bd arm, davinci: Remove duplication of pinmux configuration code
This patch replaces the pinmux configuration code in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c by the code from
arch/arm/cpu/arm926ejs/davinci/pinmux.c.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2011-12-06 23:59:37 +01:00
Christian Riesch
516fb1c4c0 arm, da850: Add pinmux configurations to the arch tree
Up to now nearly every davinci board has separate code for the
definition of pinmux configurations. This patch adds pinmux
configurations for the DA850 SoCs to the arch tree which may later
be used for all DA850 based boards.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
2011-12-06 23:59:36 +01:00
Christian Riesch
964930bcfd arm, davinci: Move pinmux functions from board to arch tree
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Nick Thompson <nick.thompson@ge.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Nick Thompson <nick.thompson@ge.com>
2011-12-06 23:59:36 +01:00
Heiko Schocher
ca4b55800e arm, arm926ejs: always do cpu critical inits
always do the cpu critical inits in cpu_init_crit,
and only jump to lowlevel_init, if CONFIG_SKIP_LOWLEVEL_INIT
is not defined.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
2011-12-06 23:59:36 +01:00
Ilya Yanok
ad2a7909a1 AM3517: move AM3517 specific mux defines to generic header
AM3517 specific CONTROL_PADCONF_* defines moved from board-specific
files to <asm/arch-omap3/mux.h>

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2011-12-06 23:59:36 +01:00
Ilya Yanok
b9e65a797b AM35xx: add EMAC support
AM35xx has DaVinci-compatible EMAC.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2011-12-06 23:59:36 +01:00
Ilya Yanok
2f3427ccb9 arm926ejs: add noop implementation for dcache ops
Added noop implementation for dcache operations that will buzz
about missing real implementation and disable the dcache.
This fixes compilation of DaVinci EMAC driver on arm926ejs.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2011-12-06 23:59:35 +01:00
Ilya Yanok
7c587d320d davinci_emac: move arch-independent defines to separate header
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs
also. This patch moves common defines from arch-davinci/emac_defs.h to
drivers/net/davinci_emac.h

DaVinci specific PHY drivers hacked to include the new header. We might
want to switch to phylib in future.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2011-12-06 23:59:35 +01:00
Aneesh V
23e9f0723e omap4: fix IO setting
The value from TRIM is not working for some 4430 silicons.
So, override with hw team recommended value. However, for
4460 TRIM value shall be used as long as the part is trimmed

This fixes boot problem on some OMAP4430 ES2.0 Panda boards
out there.

Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
9404758e9b omap4460: add ES1.1 identification
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
4324c118a0 omap4: emif: fix error in driver
There was a typo in the EMIF driver. It went un-noticed
because it affected only when automatic detection is enabled
and even then half the memory was configured and identified
properly.

Reported-by: Rockefeller <rockefeller.lin@innocomm.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
473673a5c8 omap: remove I2C from SPL
Due to some recent changes I2C is no longer required in SPL.
Remove the i2c_init() call to save some space

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
cd5847ac3a omap4460: fix TPS initialization
TPS power IC is controlled using a GPIO (gpio_wk7).
This GPIO should be maintained at logic 1 always. As
such an internal pull-up on this pin will do the job,
driving the GPIO outuput is not needed. This will avoid
the need of using GPIO library in SPL and also may
save some power.

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
e4fce34e7a start.S: remove omap3 specific code from start.S
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Tom Rini <trini@ti.com>
2011-12-06 23:59:34 +01:00
Aneesh V
a8c686399f armv7: setup vector
The vector is not correctly setup in armv7 except for OMAP3.
Correcting this.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:33 +01:00
Aneesh V
87d3da7b01 armv7: include armv7/cpu.c in SPL build
This allows SPL to have default implementation of
save_boot_params(), useful for SoCs that do
not intend to override this default implementation

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:33 +01:00
Aneesh V
dc7100f408 armv7: disable L2 cache in cleanup_before_linux()
We were not disabling external caches before jumping
to kernel. We were flushing all caches including
external caches and disabling caches globally in
CP15 System Control register. Apparently this is not
enough.

The bootstrap loader in Linux kernel that does decompression
enables data-caches again, flush them after use and disable
them before jumping to kernel proper. However, it's not aware
of the external caches.

Since we have left external cache enabled, external cache will
get used once caches are enabled globally, but it's not flushed
because decompressor is not aware of external caches. When it
jumps to kernel with caches disabled globally, we have stale
data in the external cache and a coherency problem.

This was breaking the boot for OMAP4 with latest mainline
kernel. The solution is to disable external caches in
cleanup_before_linux(). With this fix kernel is booting again.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-12-06 23:59:33 +01:00
Christian Riesch
8f1da53508 arm, arm926ejs: Fix clear bss loop for zero length bss
This patch fixes the clear bss loop for bss sections that have
zero length, i.e., where __bss_start == __bss_end__.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2011-12-06 23:59:33 +01:00
Marek Vasut
f68d2a222f PXA: Rename pxa_dram_init to pxa2xx_dram_init
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-12-06 23:59:33 +01:00
Marek Vasut
77b04c578c PXA: Export cpu_is_ and pxa_dram_init functions
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-12-06 23:59:32 +01:00
Marek Vasut
d1bb9443f0 PXA: Replace timer driver
This new timer driver shall conform to new Timer API.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-12-06 23:59:32 +01:00
Marek Vasut
e8de0fa896 PXA: Add cpuinfo display for PXA2xx
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-12-06 23:59:32 +01:00
Marek Vasut
d10237d275 PXA: Separate PXA2xx CPU init
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-12-06 23:59:32 +01:00
Marek Vasut
abc20aba18 PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-12-06 23:59:32 +01:00
Marek Vasut
7f4cfcf40d PXA: Re-add the Dcache locking as RAM for pxa250
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-12-06 23:59:31 +01:00
Marek Vasut
20f7b1b745 PXA: Rework start.S to be closer to other ARMs
The start.S on PXA was very obscure. This reworks it back to be close to arm1136
start.S and others.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

V2: Don't compile in relocation support if building SPL
2011-12-06 23:59:31 +01:00
Wolfgang Denk
d194837fc3 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
  Makefile: add tools/mkenvimage to target 'clean'
  mv_common.c: get rid of 'defined but not used' warning
  m68k: fix ambiguous bit testing
  sparc: fix unknown escape sequence warnings
  sparc: fix unused variable warnings
  sf: fix erase debug output
2011-12-05 23:33:48 +01:00
Mike Frysinger
65f0d12152 m68k: fix ambiguous bit testing
Building for some m68k boards results in the warning:

cpu_init.c: In function 'cpu_init_f':
cpu_init.c:287: warning: suggest parentheses around
	operand of '!' or change '&' to '&&' or '!' to '~'

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-05 21:55:25 +01:00
Mike Frysinger
8344a6d50b sparc: fix unused variable warnings
Fix the build warnings:
board.c: In function 'board_init_f':
board.c:179:8: warning: unused variable 'e'
board.c:178:6: warning: unused variable 'i'
board.c:173:13: warning: unused variable 'cmdtp'
bootm.c: In function 'do_bootm_linux':
bootm.c:101:28: warning: unused variable 'kernend'
bootm.c:101:15: warning: unused variable 'initrd_addr'
bootm.c💯26: warning: unused variable 'checksum'
bootm.c💯21: warning: unused variable 'len'
bootm.c💯15: warning: unused variable 'data'

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-05 21:55:24 +01:00
Nobuhiro Iwamatsu
bead86a836 sh: Add support Renesas SH7724
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-12-02 13:46:21 +09:00
Mike Frysinger
172106433b sh: avoid multiple definition errors with cache funcs
Recent builds for SH4 boards fail with a lot of errors like:
	cmd_mem.o: In function 'dcache_invalid_range':
	include/asm/cache.h:25: multiple definition of 'dcache_invalid_range'
	include/asm/cache.h:25: first defined here

This is due to the funcs being defined in the header, but not static
or inline or extern.  So move them to the sh4-specific cache.c file.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-12-02 13:46:21 +09:00
Phil Edworthy
cb4046c592 sh: Add ashrsi3 libgcc function
The ashrsi3 function is used by some commands that aren't in SH2A
default configs (e.g. JFFS2).

The ashrsi3.S file has been copied from Linux.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-12-02 13:46:20 +09:00
Mike Frysinger
4cde1740d2 sh: only add -mno-fdpic if the compiler supports it
Not all SuperH toolchains support -mno-fdpic.  Chances are good that if
the flag doesn't work, it isn't defaulting to the FDPIC ABI, so the flag
isn't needed.  So only add it if it is actually supported.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-12-02 13:46:20 +09:00
Wolfgang Denk
ad37ef1a85 arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warning
Fix:
cpu.c: In function 'checkcpu':
cpu.c:51:7: warning: variable 'ver' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-02 00:16:46 +01:00
Wolfgang Denk
d51e6d6de2 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  mpc85xx: support for Freescale COM Express P2020
  arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
  mpc85xx: support board-specific reset function
  powerpc/85xx: verify the localbus device tree address before booting the OS
  mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
  powerpc/p3060qds: Add board related support for P3060QDS platform
  powerpc/85xx: clean up and document the QE/FMAN microcode macros
  powerpc/85xx: always implement the work-around for Erratum SATA_A001
  powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
  powerpc/85xx: Add workaround for erratum A-003474
  powerpc/85xx: fixup flexcan device tree clock-frequency
  powerpc/85xx: Add workaround for erratum CPU-A003999
2011-12-01 23:58:11 +01:00
Ira W. Snyder
9839709ea3 mpc85xx: support for Freescale COM Express P2020
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 09:07:51 -06:00
Kumar Gala
411e150375 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
Fix:

interactive.c: In function 'fsl_ddr_interactive':
interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Ira W. Snyder
c18de0d7ae mpc85xx: support board-specific reset function
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
cc15df57b1 powerpc/85xx: verify the localbus device tree address before booting the OS
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR.  If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.

Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong.  This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Ira W. Snyder
2f3a71f235 mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
f2717b47ea powerpc/85xx: clean up and document the QE/FMAN microcode macros
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both.  A given SOC will only have
a QE or an Fman, so this is safe.

Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND.  There's no way to know by looking at a variable how it's supposed
to be used.

In the future, the code which uploads QE firmware and Fman firmware will
be merged.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
fbc20aab11 powerpc/85xx: always implement the work-around for Erratum SATA_A001
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default.  So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Timur Tabi
3e0529f742 powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files.  So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020.  It was already defined for the
P1010 and P1014.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
York Sun
4108508a96 powerpc/85xx: Add workaround for erratum A-003474
Erratum A-003474: Internal DDR calibration circuit is not supported

Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.

Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf54

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Jia Hongtao
33c875366e powerpc/85xx: fixup flexcan device tree clock-frequency
Make the fixup matchable with dts and kernel.  Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency".  We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.

We now keep the old interfaces to make previous kernel work. They should
be removed in the future.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Kumar Gala
43f082bb7f powerpc/85xx: Add workaround for erratum CPU-A003999
Erratum A-003999: Running Floating Point instructions requires special
initialization.

Impact:
Floating point arithmetic operations may result in an incorrect value.

Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:05 -06:00
Gabe Black
36b2409a3d x86: Wrap small helper functions from libgcc to avoid an ABI mismatch
When gcc compiles some 64 bit operations on a 32 bit machine, it generates
calls to small functions instead of instructions which do the job directly.
Those functions are defined in libgcc and transparently provide whatever
functionality was necessary. Unfortunately, u-boot can be built with a
non-standard ABI when libgcc isn't. More specifically, u-boot uses
-mregparm. When the u-boot and libgcc are linked together, very confusing
bugs can crop up, for instance seemingly normal integer division or modulus
getting the wrong answer or even raising a spurious divide by zero
exception.

This change borrows (steals) a technique and some code from coreboot which
solves this problem by creating wrappers which translate the calling
convention when calling the functions in libgcc. Unfortunately that means
that these instructions which had already been turned into functions have
even more overhead, but more importantly it makes them work properly.

To find all of the functions that needed wrapping, u-boot was compiled
without linking in libgcc. All the symbols the linker complained were
undefined were presumed to be the symbols that are needed from libgcc.
These were a subset of the symbols covered by the coreboot code, so it was
used unmodified.

To prevent symbols which are provided by libgcc but not currently wrapped
(or even known about) from being silently linked against by code generated
by libgcc, a new copy of libgcc is created where all the symbols are
prefixed with __normal_. Without being purposefully wrapped, these symbols
will cause linker errors instead of silently introducing very subtle,
confusing bugs.

Another approach would be to whitelist symbols from libgcc and strip out
all the others. The problem with this approach is that it requires the
white listed symbols to be specified three times, once for objcopy, once so
the linker inserts the wrapped, and once to generate the wrapper itself,
while this implementation needs it to be listed only twice. There isn't
much tangible difference in what each approach produces, so this one was
preferred.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-11-29 21:31:24 +11:00
Gabe Black
dbaef6ef33 x86: Import the glibc memset implementation
The new implementation is about twice as fast as the old. This is from
glibc-2.14, sysdeps/i386/memset.c.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-11-29 21:31:17 +11:00
Gabe Black
60a9b6bfdd x86: Fix a few recently added bugs
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:30:51 +11:00
Gabe Black
769db03a4a x86: Don't relocate symbols which point to things that aren't relocated
This change adds an upper bound for symbols which are fixed up after u-boot
is relocated into RAM. This way portions that are left at their original
location can be referred to without having to manually fix up any pointers.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-11-29 21:30:44 +11:00
Gabe Black
03228b26d5 x86: Fix how the location of the realmode and bios blobs are calculated
There are two blobs embedded into the u-boot image which are linked to run
at an address which is different from where they actually end up in the
ROM, one called "realmode" and one called "bios". There are realmode_setup
and bios_setup functions which prepare those blobs by copying them into the
location they're supposed to run from, among other things.

During u-boot relocation from ROM to RAM, the text and a few data segments
are copied over. The realmode and bios sections are not copied, and so the
only place they can be read from is their original location in the ROM.
Looking specifically at the bios blob, there are symbols defined in the
linker script called __bios_start and __bios_size which are defined to be
the start and size of the blob in the ROM.

In the bios_setup function, there seem to be two mistakes happening. First,
the offset from ROM to RAM is being added to __bios_start which implies that
this code expects to use the copy moved to RAM. No such copy is made, so
that's wrong. More subtly, when u-boot relocates itself, it goes through
all of the relocations stored in .rel.dyn and fixes them up. This has the
effect of transforming the __bios_start reference in bios_setup so that it
refers to the version in RAM (if one existed) instead of the one in ROM. To
correct for that, the offset actually needs to be subtracted out again to
translate the address back into the ROM.

The net effect is that for both blobs, a + needs to be changed to a -.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-11-29 21:30:38 +11:00
Graeme Russ
2f0e0cd246 x86: Misc cleanups
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:10:12 +11:00
Graeme Russ
1cfcf03701 x86: Misc PCI touchups
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:10:08 +11:00
Graeme Russ
303418cc97 x86: Ensure IDT and GDT remain 16-byte aligned post relocation
Some CPUs have strict alignment requirements for these tables

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:10:01 +11:00
Graeme Russ
a76fc70ee1 x86: Provide more configuration granularity
Planned future ports requires more granularity for some options

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:09:52 +11:00
Graeme Russ
a206cc2343 x86: Add multiboot header
By adding a multiboot header, U-Boot can be loaded by GRUB2. Using GRUB2 to
bootstrap U-Boot is useful for using an existing BIOS to get an initial
U-Boot port up and running before implementing the low-level reset vector
code, SDRAM init, etc. and overwriting the BIOS

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:08:02 +11:00
Graeme Russ
311b1a2b38 sc520: Create arch asm-offsets
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:07:42 +11:00
Graeme Russ
facc9e7bf4 x86: Punt cold- and warm-boot flags
Nobody uses them anyway

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-29 21:04:06 +11:00
Graeme Russ
83088afbba cosmetic: checkpatch cleanup of arch/x86/lib/*.c
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:03:43 +11:00
Graeme Russ
01a0f5a1eb cosmetic: checkpatch cleanup of arch/x86/cpu/sc520/*.c
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:01:26 +11:00
Graeme Russ
717979fdd7 cosmetic: checkpatch cleanup of arch/x86/cpu/*.c
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:01:21 +11:00
Graeme Russ
6d7404c4c1 x86: Call hang() on unrecoverable exception
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-11-29 21:01:13 +11:00
Christian Riesch
e722d5d076 hawkboard: Replace HAWKBOARD_KICK{0, 1}_UNLOCK defines
This patch replaces the HAWKBOARD_KICK{0,1}_UNLOCK defines by
DV_SYSCFG_KICK{0,1}_UNLOCK.

The kick register values are not hawkboard specific but may be used
for all davinci boards. In commit f3c149d6c6
new defines for these values wer introduced.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-27 19:45:35 +01:00
Alexander Holler
a67fe5f284 OMAP3: Use sdelay from arch/arm/cpu/armv7/syslib.c instead of cloning that.
There is no need to have such a function twice.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-27 19:44:36 +01:00
Stelian Pop
762e63754b Fix Stelian's email address
Change my old email address which is no longer valid.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-27 19:44:21 +01:00
Wolfgang Denk
fdbe8b9a2d Merge branch 'hs@denx.de' of git://git.denx.de/u-boot-staging
* 'hs@denx.de' of git://git.denx.de/u-boot-staging:
  drivers/net/dnet.c: Fix GCC 4.6 warnings
  board/xaeniax/flash.c: Fix GCC 4.6 warnings
  net/bootp.c: Fix GCC 4.6 warning
  common/cmd_bootm.c: Fix GCC 4.6 warnings
  board/mx1ads/mx1ads.c: Fix GCC 4.6 warning
  board/mx1ads/syncflash.c: Fix GCC 4.6 warnings
  board/lubbock/flash.c: Fix GCC 4.6 warnings
  drivers/net/cs8900.c: Fix GCC 4.6 warning
  arch/arm/cpu/arm926ejs/omap/cpuinfo.c: Fix GCC 4.6 warnings
  drivers/net/lan91c96.c: Fix GCC 4.6 warning
  board/ronetix/pm9263/pm9263.c: Fix GCC 4.6 warning
  drivers/mtd/onenand/samsung.c: Fix GCC 4.6 warning
  drivers/usb/musb/musb_hcd.c: Fix GCC 4.6 warning
2011-11-23 21:23:45 +01:00
Anatolij Gustschin
604256a449 arch/arm/cpu/arm926ejs/omap/cpuinfo.c: Fix GCC 4.6 warnings
Fix:
cpuinfo.c: In function 'print_cpuinfo':
cpuinfo.c:155:6: warning: variable 'system_serial_low' set but not used
[-Wunused-but-set-variable]
cpuinfo.c:154:6: warning: variable 'system_serial_high' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-23 08:14:27 +01:00
Macpaul Lin
39c87743bb nds32/ag101: clean up for SoC related code
Remove unneccessary codes.
1. Clean up for cpu related code.
2. Clean up for timer related code.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-23 14:05:51 +08:00
Mike Frysinger
2cc8b5c0e8 net: rtl8109: drop unused !NET_MULTI driver
No one uses this driver, and it isn't converted to the NET_MULTI
framework (which we dropped recently), so drop this driver too.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-11-22 08:39:25 +01:00
Wolfgang Denk
74faaf9656 Merge branch 'master' of git://git.denx.de/u-boot-blackfin
* 'master' of git://git.denx.de/u-boot-blackfin:
  Blackfin: cache result of cpp check
  Blackfin: traps: fix up printf warnings from debug
  Blackfin: drop now unused local variable
2011-11-21 22:04:17 +01:00
Wolfgang Denk
3bf03add54 Merge branch 'master' of git://git.denx.de/u-boot-nds32
* 'master' of git://git.denx.de/u-boot-nds32:
  nds32/lib: add ide generic support
  nds32: enhance io.h for compatibility with periphals
  ftide020: fix incorrect information display format
2011-11-21 22:02:35 +01:00
Wolfgang Denk
c829ff2e3d Merge branch 'master' of git://git.denx.de/u-boot-nios
* 'master' of git://git.denx.de/u-boot-nios:
  nios2: Offer ft_board_setup() capability and call fdt_fixup_ethernet().
  board/nios2-generic: Use altera_pio driver and remove board specific driver
  gpio: Add driver for Altera's PIO core
  nios2: Pseudo implement dcache_status/enable/disable()
2011-11-21 22:00:37 +01:00
Mike Frysinger
e29ad970f1 Blackfin: cache result of cpp check
Avoid overhead of computing this value multiple times.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-11-18 22:13:26 -05:00
Mike Frysinger
ff1a618ad2 Blackfin: traps: fix up printf warnings from debug
Cast uint32_t to void* for %p, and use %zu for size_t.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-11-18 22:13:26 -05:00
Mike Frysinger
710aa76227 Blackfin: drop now unused local variable
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-11-18 22:13:25 -05:00
Macpaul Lin
a2308547d1 nds32/lib: add ide generic support
Add ide generic support.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-18 17:27:12 +08:00
Macpaul Lin
d21f6e583b nds32: enhance io.h for compatibility with periphals
Enhance io.h for periphals origin design on x86 systems.
For example, pci, ide, etc.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-18 17:26:26 +08:00
Kim Phillips
9da752e97f mpc83xx: spd_sdram - fix gcc 4.6 compiler warning
Configuring for sbc8349 board...
spd_sdram.c: In function 'spd_sdram':
spd_sdram.c:152:41: warning: variable 'trfc_high' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-16 21:40:26 +01:00
Anatolij Gustschin
7a1b07eef9 arch/arm/cpu/armv7/s5p-common/pwm.c: fix GCC 4.6 warning
Fix:
pwm.c: In function 'pwm_config':
pwm.c:85:16: warning: variable 'timer_rate_hz' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:37:01 +01:00
Stefan Roese
bddf144cb6 iop480_uart.c: Fix GCC 4.6 build warnings
Fix:
iop480_uart.c: In function 'serial_init':
iop480_uart.c:137:16: warning: variable 'val' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:17:36 +01:00
Stefan Roese
4a1272662a 40x_spd_sdram.c: Fix GCC 4.6 build warnings
Fix:
40x_spd_sdram.c: In function 'spd_sdram':
40x_spd_sdram.c:137:6: warning: variable 'sdram0_b3cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:136:6: warning: variable 'sdram0_b2cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:129:6: warning: variable 'sdram0_ecccfg' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:59 +01:00
Stefan Roese
deeecb7c7e 44x_spd_ddr2.c: Fix GCC 4.6 build warnings
44x_spd_ddr2.c: In function 'initdram':
44x_spd_ddr2.c:450:17: warning: variable 'dimm_spd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'program_copt1':
44x_spd_ddr2.c:1003:16: warning: variable 'ddrtype' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c: In function 'DQS_calibration_process':
44x_spd_ddr2.c:2498:7: warning: variable 'window_found' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2497:16: warning: variable 'end_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2496:16: warning: variable 'end_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2495:16: warning: variable 'begin_rffd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2494:16: warning: variable 'begin_rqfd' set but not used [-Wunused-but-set-variable]
44x_spd_ddr2.c:2493:7: warning: variable 'min_end' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:51 +01:00
Stefan Roese
6cd71d0f17 44x_spd_ddr.c: Fix GCC 4.6 build warnings
Fix:
44x_spd_ddr.c: In function 'program_cfg0':
44x_spd_ddr.c:384:16: warning: variable 'dimm_64bit' set but not used [-Wunused-but-set-variable]
44x_spd_ddr.c:383:16: warning: variable 'dimm_32bit' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:36 +01:00
Stefan Roese
a6370da13e cmd_ecctest.c: Fix GCC 4.6 build warnings
Fix:
cmd_ecctest.c: In function 'inject_ecc_error':
cmd_ecctest.c:116:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]
cmd_ecctest.c: In function 'rewrite_ecc_parity':
cmd_ecctest.c:154:6: warning: variable 'val' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:20 +01:00
Stefan Roese
8f6db4b7ab 4xx_ibm_ddr2_autocalib.c: Fix GCC 4.6 build warnings
Fix:
4xx_ibm_ddr2_autocalib.c: In function 'get_membase':
4xx_ibm_ddr2_autocalib.c:157:8: warning: variable 'bxcf' set but not used [-Wunused-but-set-variable]
4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB':
4xx_ibm_ddr2_autocalib.c:722:8: warning: variable 'rffd' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:15:07 +01:00
Stefan Roese
fe91a65707 4xx_pcie.c: Fix GCC 4.6 build warnings
Fix:
4xx_pcie.c: In function 'pcie_read_config':
4xx_pcie.c:230:6: warning: variable 'address' set but not used [-Wunused-but-set-variable]
4xx_pcie.c: In function 'pcie_write_config':
4xx_pcie.c:290:6: warning: variable 'address' set but not used [-Wunused-but-set-variable]
4xx_pcie.c: In function 'ppc4xx_setup_pcie_rootpoint':
4xx_pcie.c:1066:17: warning: variable 'rmbase' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:14:39 +01:00
Stefan Roese
af0af524ed usb_ohci.c: Fix GCC 4.6 build warnings
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:756:8: warning: variable 'tdINFO' set but not used [-Wunused-but-set-variable]

Signed-off-by: Stefan Roese <sr@denx.de>
2011-11-16 21:13:26 +01:00
Anatolij Gustschin
d14a94bf68 arch/powerpc/cpu/mpc512x/i2c.c: Fix GCC 4.6 warnings
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:81:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:12:48 +01:00
Anatolij Gustschin
c33b92ebcc arch/powerpc/cpu/mpc512x/pci.c: Fix GCC 4.6 warnings
Fix:
pci.c: In function 'pci_init_board':
pci.c:55:26: warning: variable 'pci_conf' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-11-16 21:12:29 +01:00
Wolfgang Denk
9dfa8da709 Merge branch 'master' of git://git.denx.de/u-boot-video
* 'master' of git://git.denx.de/u-boot-video:
  api: export LCD device to external apps
  font: split font data from video_font.h
  tools: logo: split bmp arrays from bmp_logo.h
  lcd: add clear and draw bitmap declaration
  VIDEO: mx3fb: GCC4.6 fix build warnings
  Powerpc/DIU: Fixed the 800x600 and 1024x768 resolution bug
2011-11-16 20:44:03 +01:00
Wolfgang Denk
0c2dd9a05b Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  arm, davinci: add DAVINCI_MMC_CLKID
  arm, davinci_emac: fix driver bug if more then 3 PHYs are detected
  arm, davinci: da850/dm365 lowlevel cleanup
  omap5: Add omap5_evm board build support.
  omap4/5: Add support for booting with CH.
  omap5: emif: Add emif/ddr configurations required for omap5 evm
  omap5: clocks: Add clocks support for omap5 platform.
  omap5: Add minimal support for omap5430.
  omap: Checkpatch fixes
  omap4: make omap4 code common for future reuse
  GCC4.6: Squash warnings in onenand_base.c
  GCC4.6: Fix common/usb.c on xscale
  OneNAND: Add simple OneNAND SPL
  PXA: vpac270: Enable the new generic MMC driver
  PXA: Cleanup serial_pxa
  PXA: Drop csb226 and innokom boards (unmaintained)
  m28evk: Fix comment about the number of RAM banks
  mx31: Fix checkpatch warnings in generic.c
  mx31: Use proper IO accessor for GPR register
  mx31: Remove duplicate definition for GPR register
  qong: Use generic function for configuring GPR register
  M28EVK: Enable USB HOST support
  iMX28: Add USB HOST driver
  iMX28: Add USB and USB PHY register definitions
  M28: Add memory detection into SPL
  iMX28: Fix ARM vector handling
  M28: Add doc/README.m28 documentation
  M28: Add MMC SPL
  iMX28: Add support for DENX M28EVK board
  iMX28: Add u-boot.sb target to Makefile
  iMX28: Add image header generator tool
  iMX28: Add driver for internal RTC
  iMX28: Add GPMI NAND driver
  iMX28: Add APBH DMA driver
  iMX28: Add SPI driver
  iMX28: Add GPIO control
  iMX28: Add I2C bus driver
  iMX28: Add PINMUX control
  FEC: Add support for iMX28 quirks
  iMX28: Add SSP MMC driver
  iMX28: Initial support for iMX28 CPU
  MX25: zmx25: GCC4.6 fix build warnings
  da850: add new config file for AM18xx
  BeagleBoard: config: Switch to ttyO2
  OMAP3: Change omap3_evm maintainer
  devkit8000: Fix NAND SPL on boards with 256MB NAND
  integrator: enable Vpp and disable flash protection
  integrator: add system controller header
  integrator: make flash writeable on boot
  integrator: use io-accessors for board init
  integrator: move text offset to config
  integrator: pass configs for core modules
  ARM: remove superfluous setting of arch_number in board specific code.
  SPL: Allow ARM926EJS to avoid compiling in the CPU support code
  integrator: do not test first part of the memory
  arm: a320: fix broken timer
  ARM: define CONFIG_MACH_TYPE for all ronetix boards
  dm646x: pass board revision info to kernel
  dm646x: add new configuration for dm6467T
  arm, davinci: Fix setting of the SDRAM configuration register
  arm, davinci: Remove the duplication of LPSC functions
  arm, davinci: Rename AM1808 lowlevel functions to DA850
  da8xxevm: fix build error
  ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
2011-11-16 20:24:41 +01:00
Wolfgang Denk
c7801ee43b Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
  arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning
  drivers/qe/uec.c: Fix GCC 4.6 build warning
  drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning
  drivers/net/fm/fm.c: Fix GCC 4.6 build warning
  board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning
  board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning
  board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning
  board/freescale/common/pixis.c: Fix GCC 4.6 build warning
  board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning
  phylib: Enable AR8021 phy support
  powerpc/85xx: Set max alloc length to 10MB on P1022DS
  powerpc/mpc85xx: Set SYSCLK to the required frequency
  powerpc/85xx: Fix NAND SPL support
  powerpc/85xx: Fix MPC8572DS NAND build
  fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399
  powerpc/85xx: Add support for Book-E MMU Arch v2.0
  powerpc/85xx: Make inclusion of USB device fixup conditional
  powerpc/85xx: Fix warning for USB device-fixup
  powerpc/85xx: resize the boot page TLB before relocating CCSR
  powerpc/85xx: verify the current address of CCSR before relocating it
  powerpc/85xx: add some missing sync instructions in the CCSR relocation code
  powerpc/85xx: fix some comments in the CCSR relocation code
  powerpc/85xx: fix definition of MAS register macros
  powerpc/mpc8548cds: Fix network initialization
  powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129
  powerpc/QorIQ: fix network frame manager TBI PHY address settings
2011-11-16 20:06:21 +01:00
Che-Liang Chiou
d3983ee853 font: split font data from video_font.h
While video_font.h is useful even without referencing the font data, it
is not possible to be included multiple times because it defines font
data array right in the header.

This patch splits the font data array into video_font_data.h and so now
video_font.h can be included multiple times.  This at least solves the
code duplication in board/mcc200/lcd.c.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-15 23:58:26 +01:00
Heiko Schocher
75acc4d7c1 arm, davinci: add DAVINCI_MMC_CLKID
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:51 +01:00
Heiko Schocher
f3c149d6c6 arm, davinci: da850/dm365 lowlevel cleanup
- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
  file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:51 +01:00
Sricharan
78f455c055 omap4/5: Add support for booting with CH.
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.

Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
bb772a5944 omap5: emif: Add emif/ddr configurations required for omap5 evm
Add the emif configurations required for omap5 soc.Add the
correct ddr part configurations required for omap5 evm board.
EDB8164B3PH from ELPIDA is the part used on the board.

Also changes are done to retain some part of the code
common for OMAP4/5 and keep only the remaining in the Soc
specific directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
2e5ba48928 omap5: clocks: Add clocks support for omap5 platform.
Adding the correct configurations required for
dplls, clocks, for omap5 Soc.

Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
508a58fa8e omap5: Add minimal support for omap5430.
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
933efe641a omap: Checkpatch fixes
Fixing them here so that when the files are reused in
subsequent patches for omap5, avoids new checkpatch
warnings.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
ce170beeb7 omap4: make omap4 code common for future reuse
Much of omap4 soc support code can be reused for omap5.
Move them to the omap-common directory to facilitate
this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Marek Vasut
237ce0fe97 PXA: Cleanup serial_pxa
* Cleanup register definitions by introducing new regs-uart.h, compliant with
  rest of U-Boot.
* Remove old register definitions from pxa-regs.h
* Convert serial_pxa to new regs-uart.h
* Cleanup serial_pxa

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-11-15 22:24:50 +01:00
York Sun
2d14e36a50 powerpc/mpc83xx: cleanup makefile for mpc83xx
Remove symbolic link generated by compiling. Fix makefile for out-of-tree
compiling error.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-11 16:40:51 -06:00
Kumar Gala
dea7f88726 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning
Fix:

ctrl_regs.c: In function 'set_ddr_sdram_cfg_2':
ctrl_regs.c:641:15: warning: variable 'rcw_en' set but not used [-Wunused-but-set-variable]
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:951:31: warning: array subscript is above array bounds [-Warray-bounds]
ctrl_regs.c:752:34: warning: array subscript is above array bounds [-Warray-bounds]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:01 -06:00
Kumar Gala
c1ee16b8e0 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning
Fix:

fsl_corenet_serdes.c: In function 'fsl_serdes_init':
fsl_corenet_serdes.c:511:8: warning: variable 'buf' set but not used [-Wunused-but-set-variable]
fsl_corenet_serdes.c:498:18: warning: variable 'lane_prtcl' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:01 -06:00
Kumar Gala
667bc17e07 arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning
Fix:

options.c: In function 'populate_memctl_options':
options.c:486:28: warning: variable 'pdodt' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:01 -06:00
Kumar Gala
e55d637a5f arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning
Fix:

fsl_lbc.c: In function 'upmconfig':
fsl_lbc.c:110:9: warning: variable 'mdr' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Kumar Gala
3d6d9c3116 arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning
Fix:

tlb.c: In function 'disable_tlb':
tlb.c:175:34: warning: variable '_mas7' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Kumar Gala
e4c9a35d21 arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning
Fix:

cpu_init.c: In function 'cpu_init_r':
cpu_init.c:320:7: warning: variable 'l2srbar' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Fabio Estevam
c0225d1138 mx31: Fix checkpatch warnings in generic.c
Fix checkpatch warnings in generic.c.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-11 11:36:58 +01:00
Fabio Estevam
ce93dc9bce mx31: Use proper IO accessor for GPR register
Use proper IO accessor for GPR register.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-11 11:36:58 +01:00
Fabio Estevam
94e6dd2bc5 mx31: Remove duplicate definition for GPR register
GPR register definition is already available at imx-regs.h, so remove the duplication.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-11 11:36:58 +01:00
Marek Vasut
b2d20161f7 iMX28: Add USB and USB PHY register definitions
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
2011-11-11 11:36:58 +01:00
Marek Vasut
22fe68fbdc iMX28: Fix ARM vector handling
This patch introduces proper ARM vector handling for i.MX28 CPU. This issue
wasn't addressed because the interrupts weren't enabled on any ARMv5 core,
therefore the issue wasn't noticed earlier.

In previous implementation, the vectoring code used by i.MX28 CPU when an
exception happened was that of the SPL. With this change, the branch target when
an exception happens can be reconfigured by U-Boot.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-11-11 11:36:58 +01:00
Marek Vasut
31650d64a8 iMX28: Add APBH DMA driver
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-11-11 11:36:57 +01:00
Marek Vasut
6b6440def8 iMX28: Add GPIO control
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-11-11 11:36:57 +01:00
Marek Vasut
d91a672b6d iMX28: Add PINMUX control
Taken from Linux kernel with minor modifications:

commit bf985969e27b507f734435a99df8bf745a3dbb2b
Author: Shawn Guo <shawn.guo@freescale.com>
Date:   Mon Dec 20 22:57:43 2010 +0800

    ARM: mxs: Add iomux support

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-11-11 11:36:57 +01:00
Marek Vasut
71a758e158 iMX28: Add SSP MMC driver
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: Andy Fleming <afleming@gmail.com>
2011-11-11 11:36:56 +01:00
Marek Vasut
6e9a0a3967 iMX28: Initial support for iMX28 CPU
This patch supports:
- Timers
- Debug UART
- Clock

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-11-11 11:36:56 +01:00
Macpaul Lin
6cb144bc26 adp-ag101p: Add SoC and board support of ag101p
Add softcore SoC ag101p and the board adp-ag101p support.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-10 10:46:54 +08:00
Macpaul Lin
c4f4054664 nds32: fix data section of linker script
Make linker script handles .data.rel sections.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-11-09 16:35:27 +08:00
Marek Vasut
99bd341b96 SPL: Allow ARM926EJS to avoid compiling in the CPU support code
This allows the SPL to avoid compiling in the CPU support code.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
2011-11-08 22:16:53 +01:00
Po-Yu Chuang
60d1ea94ea arm: a320: fix broken timer
timer.c used static data and are called before relocation.
Move all static variables into global_data structure. Also cleanup
timer.c from unused stubs and make it truly use 64 bit tick values.

Remove reset_timer_masked() get_timer_masked()

reference: arch/arm/cpu/arm926ejs/at91/timer.c

Based on Reinhard Meyer <u-boot@emk-elektronik.de>'s patches
5dca710a3d
cfff263f41

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Tested-by: Macpaul Lin <macpaul@gmail.com>
2011-11-08 20:52:23 +01:00
Poonam Aggrwal
cfee584eea fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399
Wrong pointer was being used to copy code into L2SRAM.
Also removed the unreferenced variable l2srbar.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:37:25 -06:00
Kumar Gala
50cf3d17ce powerpc/85xx: Add support for Book-E MMU Arch v2.0
A few of the config registers changed definition between MMU v1.0 and
MMUv2.0.  The new e6500 core from Freescale implements v2.0 of the
architecture.

Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:36:51 -06:00
Ramneek Mehresh
4765fb7d73 powerpc/85xx: Fix warning for USB device-fixup
Fix USB device-fixup warning "node not found". This was occuring
because of static nature of start_offset variable

Static start_offset was storing offset of last node modified, and
was becoming issue if node fixup is carried multiple times,
resulting in "node not found" warning

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:36:02 -06:00
Timur Tabi
72243c0194 powerpc/85xx: resize the boot page TLB before relocating CCSR
On some Freescale systems (e.g. those booted from the on-chip ROM), the
TLB that covers the boot page can also cover CCSR, which breaks the CCSR
relocation code.  To fix this, we resize the boot page TLB so that it only
covers the 4KB boot page.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:31:09 -06:00
Timur Tabi
19e4384124 powerpc/85xx: verify the current address of CCSR before relocating it
Verify that CCSR is actually located where it is supposed to be before
we relocate it.  This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:31:06 -06:00
Timur Tabi
452ad61c3f powerpc/85xx: add some missing sync instructions in the CCSR relocation code
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:31:02 -06:00
Timur Tabi
c2efa0aa1e powerpc/85xx: fix some comments in the CCSR relocation code
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:30:59 -06:00
Timur Tabi
5c4a3d431e powerpc/85xx: fix definition of MAS register macros
Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.

Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
the parameter.  This hasn't caused any problems to date because the
parameter was always been 'tsize'.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:30:57 -06:00
chenhui zhao
aada81de70 powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.

Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:30:32 -06:00
Christian Riesch
085d4574c5 arm, davinci: Fix setting of the SDRAM configuration register
da850_ddr_setup() expects the BOOTUNLOCK bit to be set in
If BOOTUNLOCK is not set in this define, several configuration
bits will not be writeable and the code will not work.

Since the BOOTUNLOCK and TIMUNLOCK bits are not configuration options
but access control bits, this patch changes the code to work
irrespective of the value of these bits in CONFIG_SYS_DA850_DDR2_SDBCR.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-08 08:55:13 -05:00
Christian Riesch
95c248f488 arm, davinci: Remove the duplication of LPSC functions
The LPSC functions defined in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
are replaced by those already defined in
arch/arm/cpu/arm926ejs/davinci/psc.c.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-08 08:55:10 -05:00
Christian Riesch
effea9d18c arm, davinci: Rename AM1808 lowlevel functions to DA850
Rename arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c and
arch/arm/include/asm/arch-davinci/am1808_lowlevel.h to da850_lowlevel.c
and da850_lowlevel.h since they apply not only to the AM1808 SoC
but to all DA850 chips. The function names and #defines are changed
likewise.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-08 08:55:07 -05:00
Prabhakar Lad
3f0d4edcdb da8xxevm: fix build error
This patch fixes following compile error for da8xx evm

da830evm.c: In function 'board_init':
da830evm.c:222: error: 'DAVINCI_SYSCFG_SUSPSRC_UART2' undeclared (first use in this function)
da830evm.c:222: error: (Each undeclared identifier is reported only once
da830evm.c:222: error: for each function it appears in.)
make[2]: *** [da830evm.o] Error 1

similarly for da850evm.

introduced through commit:
f9fc237f1f

Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-08 08:55:03 -05:00
Wolfgang Denk
5721385b18 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds
  powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds
  mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code
  mpc83xx: Cleanup usage of LBC constants
  mpc83xx: Cleanup usage of DDR constants
  mpc83xx: Cleanup usage of BAT constants
  mpc83xx: cosmetic: vme8349.h checkpatch compliance
  mpc83xx: cosmetic: ve8313.h checkpatch compliance
  mpc83xx: cosmetic: sbc8349.h checkpatch compliance
  mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance
  mpc83xx: cosmetic: kmeter1.h checkpatch compliance
  mpc83xx: cosmetic: TQM834x.h checkpatch compliance
  mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance
  mpc83xx: cosmetic: MVBLM7.h checkpatch compliance
  mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance
  mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8349ITX.h checkpatch compliance
  mpc83xx: cosmetic: MPC8349EMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8313ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8308RDB.h checkpatch compliance
  mpc83xx: cosmetic: MERGERBOX.h checkpatch compliance
  mpc83xx: Fix ipic structure definition
  powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3 definitions
  cosmetic, powerpc, mpc83xx: checkpatch cleanup
  powerpc/83xx: move km 83xx specific i2c code to km83xx_i2c
  mpc83xx: fix global timer structure definition
2011-11-08 07:44:52 +01:00
Wolfgang Denk
688d8f33f2 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
  arm: jadecpu: Readd MACH_TYPE_JADECPU
  at91: defined mach-types for otc570 board in board config file
  at91: defined mach-types for meesc board in board config file
  mx31pdk: Enable D and I caches
  ehci-mxc: remove incorrect comment
  README: Fix supported i.MX SoC list for CONFIG_MXC_SPI
  mx53: Turn off child clocks before reconfigure perclk_root
  qong: enable support for compressed images
  imx: imx31_phycore.h: fix checkpatch warnings
  vision2: Remove unused get_board_rev function
  mx53smd: Remove unused get_board_rev function
  mx53ard: Remove unused get_board_rev function
  mx53evk: Remove unused get_board_rev function
  mx53evk: Add RTC support
  mx53loco: Remove unused get_board_rev function
  mx53evk: Remove unneeded '1' from mx53evk.h
  OMAP3: mvblx: Initial support for mvBlueLYNX-X
  ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE
  omap3: mem: Move comments next to definitions
  omap3: mem: Clean-up whitespaces
  omap3: mem: Define and use common macros
  Davinci: ea20: added PREBOOT to configuration
  Davinci: ea20: added I2C support
  Davinci: ea20: added video support
  VIDEO: davinci: add framebuffer to da8xx
  ARM: Davinci: added missing registers to hardware.h
  Davinci: ea20: add gpios for LCD backlight control
  Davinci: ea20: add gpio for keeping power on in board_late_init
  Davinci: ea20: Add default U-Boot environment
  Davinci: ea20: Add early init to get early output from console
  Davinci: ea20: Add NAND support
  Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
  Davinci: ea20: set console on UART0
  arm, davinci: add cam_enc_4xx support
  arm926ejs, davinci: add missing spi defines for dm365
  arm926ejs, davinci: add cpuinfo for dm365
  arm, davinci: add lowlevel function for dm365 soc
  arm, davinci: add header files for dm365
  spl, nand: add 4bit HW ecc oob first nand_read_page function
  arm, davinci: add support for new spl framework
  spl: add option for adding post memory test to the SPL framework
  net, davinci_emac: make clock divider in MDIO control register configurable
  arm, usb, davinci: make USBPHY_CTL register configurable
  usb, davinci: add enable_vbus() weak function
  omap3evm: fix errors caused by multiple definitions
  omap3evm: Add (quick) configuration for NAND only
  omap3evm: Add (quick) configuration for MMC/SD only
  omap3evm: move common config options to new file
  omap3evm: Prepare to split configuration
  omap3evm: Reorder related config options
  omap/spl: actually enable the console
  davinci_emac: compilation fix, phy is array now
  omap3evm: Set environment variable 'ethaddr'
  arm, arm926: fix missing symbols in NAND_SPL mode
  arm, davinci: Add function lpsc_syncreset()
  arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
  arm/km: portl2 environment address update to P1B
  arm/km: adapt bootcounter evaluation
  arm/km: enable jffs2 cmds
  arm/km: trigger reconfiguration for the Xilinx FPGA
  arm/km: add boardid and hwkey to kernel command line
  ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards
  netspace_v2: enable I2C EEPROM support
  netspace_v2: fix SDRAM configuration
  armada100: define CONFIG_SYS_CACHELINE_SIZE
  pantheon: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: drop empty asm-offsets.s file
  arm/km/mgcoge3un: enhance "waitforne" feature
  arm/km: add variable waitforne to mgcoge3un
  gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
  ARM: dreamplug: fix compilation
  ARM: DockStar: fix compilation
  ARM: netspace_v2: fix warnings
  am335x: Drop board_sysinfo struct
  am335x: Temporarily add MACH_TYPE define
  misc:pmic:samsung Enable PMIC driver at C210 Universal target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target
  smdkv310: use macro for mmc data read function address
  smdkv310: use spl framework for mmc spl
  SMDKV310: use get_ram_size() to validate dram size
  SMDKV310: Initialize board id using CONFIG_MACH_TYPE
  ORIGEN : use absolute paths and fix tool naming
  ORIGEN : enable device tree support
  MX25: tx25: Fix building due to missing MACH_TYPE
  mx31: Add board support for HALE TT-01
  mx31: add ESD control registers
  mx31: define pins and init for UART2 and CSPI3
  MX35: add support for flea3 board
  MX51: vision2: add MACH_TYPE in config file
  vision2: Remove unused header file
  mx51evk: Remove unused get_board_rev function
  mx51evk: Remove unneeded '1' from mx51evk.h
  I2C: Fix mxc_i2c.c problem on imx31_phycore
  mx35pdk: Add RTC support
  mx51evk: Use GPIO API for configuring the IOMUX
  mx51evk: Add RTC support
  rtc: Make mc13783-rtc driver generic
  qong: remove unneeded IOMUX settings
  qong: Use mx31_set_gpr to setup USBH2 pins
  mx31: Introduce mx31_set_gpr function
  mx31pdk: Add MC13783 PMIC support
  qong: remove unneeded "1" from qong.h
  misc: pmic: fix regression in pmic_fsl.c (SPI)
  mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME
  MX35: Drop unnecessary prototypes from imx-regs.h
  I2C: added I2C-2 and I2C-3 to MX35
  MX35: factorize common assembly code
  MX35: add reset cause as provided by other i.MX
  MX35: add pins definition for UART3
  MX35: added ESDC structure to imx-regs
2011-11-08 00:38:52 +01:00
Wolfgang Denk
69545df0e6 arch/powerpc/cpu/mpc8260/spi.c: Fix GCC 4.6 build warnings
Fix:
spi.c: In function 'spi_init_r':
spi.c:279:22: warning: variable 'cp' set but not used
[-Wunused-but-set-variable]
spi.c: In function 'spi_xfer':
spi.c:361:22: warning: variable 'cp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:47:44 +01:00
Wolfgang Denk
8a33201d0c arch/powerpc/lib/bat_rw.c: Fix GCC 4.6 build warning
Fix:
bat_rw.c: In function 'write_bat':
bat_rw.c:38:6: warning: variable 'batn' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Andy Fleming <afleming@gmail.com>
2011-11-07 22:16:55 +01:00
Wolfgang Denk
8b337be04e mpc8220/i2c.c: Fix GCC 4.6 build warning
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:109:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:16:52 +01:00
Wolfgang Denk
918e34674f mpc8260/i2c.c: replace PRINTD() by debug()
This also fixes some GCC 4.6 build warnings like:
i2c.c: In function 'i2c_init':
i2c.c:221:26: warning: variable 'txbd' set but not used
[-Wunused-but-set-variable]
i2c.c:221:19: warning: variable 'rxbd' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:16:46 +01:00
Wolfgang Denk
86ba925534 mpc8260/i2c.c: CodingStyle cleanup
Make (mostly) checkpatch clean (don't convert to use I/O accessors
yet, so there will be "Use of volatile is usually wrong" warnings
left.  Also accept some other harmless checkpatch warnings.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:16:43 +01:00
Wolfgang Denk
50f87ca556 mpc8220/fec.c: Fix GCC 4.6 build warning
Fix:
fec.c: In function 'mpc8220_fec_recv':
fec.c:733:8: warning: variable 'frame' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:16:39 +01:00
Wolfgang Denk
89a7b78c43 mpc8260/speed.c: Fix GCC 4.6 build warnings
Fix:
speed.c: In function 'get_clocks':
speed.c:113:30: warning: variable 'cpmdf' set but not used
[-Wunused-but-set-variable]
speed.c:113:23: warning: variable 'busdf' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:15:49 +01:00
Wolfgang Denk
4d4aebaa01 mpc8xx/spi.c: Fix GCC 4.6 build warnings
Fix:
spi.c: In function 'spi_init_f':
spi.c:144:21: warning: variable 'iop' set but not used
[-Wunused-but-set-variable]
spi.c:142:22: warning: variable 'cpi' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:14:32 +01:00
Wolfgang Denk
937943d3f0 mpc8xx/i2c.c: replace PRINTD() by debug()
This also fixes some GCC 4.6 build warnings like:
warning: variable 'txbd' set but not used [-Wunused-but-set-variable]
warning: variable 'rxbd' set but not used [-Wunused-but-set-variable]

Signed-off-by: WOlfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:14:10 +01:00
Wolfgang Denk
09e68ffadd mpc8xx/i2c.c: CodungStyle cleanup
Make (mostly) checkpatch-clean

We don't acctually change the code (like convert to use I/O
accessors), so there will be some remaining "Use of volatile"
warnings from checkpatch.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:14:06 +01:00
Wolfgang Denk
bae65019d7 mpc8xx/cpu.c: Fix GCC 4.6 build warnings
Fix:
cpu.c: In function 'check_CPU':
cpu.c:188:8: warning: variable 'mid' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:13:01 +01:00
Wolfgang Denk
90357f1493 mpc8xx/fec.c: Fix GCC 4.6 build warnings
Fix:
fec.c: In function 'fec_pin_init':
fec.c:381:18: warning: variable 'fecp' set but not used
[-Wunused-but-set-variable]
fec.c: In function 'fec8xx_miiphy_write':
fec.c:1013:8: warning: variable 'rdreg' set but not used
[-Wunused-but-set-variable]

Note: The code was slightly rearranged, but no functional changes
attempted, i. e. no conversion to use I/O accessors.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:11:42 +01:00
Wolfgang Denk
a442173048 arch/powerpc/cpu/mpc5xxx/usb_ohci.c: fix GCC 4.6 build warnings
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:751:8: warning: variable 'tdINFO' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:09:42 +01:00
Wolfgang Denk
1c2931d4ec arch/powerpc/lib/board.c: fix build warning
Fix:
board.c: In function 'board_init_r':
board.c:633:8: warning: unused variable 's' [-Wunused-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:09:35 +01:00
Wolfgang Denk
9b998b0c52 arch/powerpc/lib/board.c: make (mostly) checkpatch-clean
CodingStyle cleanup.

Accepted (in this cleanup) checkpatch messages:

- externs should be avoided
  (to be cleaned up later)
- no spaces at the start of a line
  (accepted in multi-line #if's)
- Macros with complex values
  (false reports)
- do not use assignment in if condition
  (accepted in one place, where avoiding it would have required an
  additional level of nesting, resulting in less readable code)

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:09:31 +01:00
Wolfgang Denk
9306749752 arch/powerpc/cpu/mpc5xxx/i2c.c: fix GC 4.6 build warnings
Fix:
i2c.c: In function 'wait_for_bb':
i2c.c:104:16: warning: variable 'temp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2011-11-07 22:09:27 +01:00
Fabio Estevam
41c881c0ca mx53: Turn off child clocks before reconfigure perclk_root
In addition to ensuring that PERCLK remains at least 2.5 times slower
than the AHB clock, certain steps need to be followed to ensure robust
operation of PERCLK when reconfiguring the PERCLK clock source.

To properly configure the PERCLK clock source, the following steps are
required:

1.In the CCGR registers, gate the clocks to all PERCLK-dependent
  modules.
2.Select the desired input clock for the PERCLK root clock (to be either
  source from the peripherals main source clock or the
  lp_apm clock source). Refer to the CMCBR register,  perclk_lp_apm_sel bit.
3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers
  to the desired setting.  Refer to the CBCDR register for details.
4.In the CCGR registers, enable the desired clocks for the
  PERCLK-dependent module clocks.

If these steps aren't followed, GPT timer may stop and the kernel stops
at "Calibrating delay loop".

Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-04 22:06:37 +01:00
Sanjeev Premi
2c5b87561a omap3: mem: Move comments next to definitions
Calculations for ACTIM_CTRLA amd ACTIM_CTRLB values
are defined in 'header' style comments.

Moved them along with definitions. Should help maintain
consistency between comments and code if any of these
are tweaked in future.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-04 13:39:25 -04:00
Sanjeev Premi
f883c5d8fa omap3: mem: Clean-up whitespaces
Consistent use of TABs and align definitions with
neighbouring code.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-04 13:39:21 -04:00
Sanjeev Premi
e3596e35f5 omap3: mem: Define and use common macros
Define common macros to arrive at the values of registers
SDRC_ACTIM_CTRLA and SDRC_ACTIM_CTRLB for different memory
types.

This doesn't make any real change in the execution but
helps readability.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-04 13:39:16 -04:00
Joe Hershberger
7d6a098219 mpc83xx: Cleanup usage of LBC constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:56 -05:00
Joe Hershberger
2fef402097 mpc83xx: Cleanup usage of DDR constants
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:55 -05:00
Joe Hershberger
4713db666c mpc83xx: Fix ipic structure definition
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

Added siprr_{b,c} and sepcr for completeness.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:52 -05:00
Kim Phillips
63063cc7ae mpc83xx: fix global timer structure definition
The byte address distance between GTCFR2 and GTMDR1 is 11, not 10.

Reported-by: Shawn Bai <programassem@hotmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:51 -05:00
Stefano Babic
134028682f VIDEO: davinci: add framebuffer to da8xx
The patch is a port from the framebuffer driver
of the Linux driver drivers/video/da8xx-fb.c, used
on davinci da8xx and OMAP-L138 boards.

As base for the port, the following commit (last changes
for this driver at the moment in the Linux kernel tree)
was taken:

commit 1db41e032d563eb47deab40dc5595be306b143ba
Author: axel lin <axel.lin@gmail.com>
Date:   Tue Feb 22 01:52:42 2011 +0000

    video: da8xx-fb: fix section mismatch warning

    Signed-off-by: Axel Lin <axel.lin@gmail.com>
    Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:26 +01:00
Stefano Babic
829f917854 ARM: Davinci: added missing registers to hardware.h
The hardware base address for ther LCD configuration
registers is missing, as well as some syscfg registers.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:26 +01:00
Bastian Ruppert
ca1646b85d Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: dzu@denx.de
CC: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Bastian Ruppert
f9fc237f1f Davinci: ea20: set console on UART0
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Heiko Schocher
8bfe325c74 arm926ejs, davinci: add missing spi defines for dm365
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Heiko Schocher
29b0bef54c arm926ejs, davinci: add cpuinfo for dm365
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Heiko Schocher
53d3b2ceed arm, davinci: add lowlevel function for dm365 soc
used for booting (for example) from NAND using spl code.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Heiko Schocher
4e28ede208 arm, davinci: add header files for dm365
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Heiko Schocher
435199f380 arm, davinci: add support for new spl framework
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:25 +01:00
Ilya Yanok
b88befa550 omap/spl: actually enable the console
Currently OMAP SPL code does all the initialization but does not set the
gd->have_console value so no output is actually performed. This patch
sets gd->have_console to 1.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:23 +01:00
Heiko Schocher
6a6e1677ad arm, arm926: fix missing symbols in NAND_SPL mode
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:23 +01:00
Christian Riesch
fab19c142e arm, davinci: Add function lpsc_syncreset()
This patch adds a function lpsc_syncreset that allows setting a
lpsc module into Sync Reset state.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-03 22:56:23 +01:00
Lei Wen
abbbbdd7e1 armada100: define CONFIG_SYS_CACHELINE_SIZE
By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-11-03 22:56:22 +01:00
Lei Wen
0caac5f415 pantheon: define CONFIG_SYS_CACHELINE_SIZE
By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-11-03 22:56:22 +01:00
Michael Walle
f779d739d6 kirkwood: define CONFIG_SYS_CACHELINE_SIZE
By default, on Kirkwood SoC DCache Lnd ICache line
lengths are 32 bytes long

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2011-11-03 22:56:22 +01:00
Mike Frysinger
8428a3991f kirkwood: drop empty asm-offsets.s file
This generated file does not belong in the tree -> punt.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2011-11-03 22:56:22 +01:00
Tom Rini
35b541c835 am335x: Drop board_sysinfo struct
This isn't used presumably should be a typedef if needed later.

Signed-off-by: Tom Rini <trini@ti.com>
2011-11-03 22:56:21 +01:00
Helmut Raiger
a6d9de436c mx31: add ESD control registers
This allows to initialize DDR memory in C code.
Currently all mx31 boards use assembler code (lowlevel_init.S)

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:20 +01:00
Helmut Raiger
d121d20195 mx31: define pins and init for UART2 and CSPI3
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:20 +01:00
Fabio Estevam
6d0fb3dbcc mx31: Introduce mx31_set_gpr function
Introduce mx31_set_gpr function for setting the GPR (General Purpose Register) on MX31.

This function can be useful for setting a group of pins into tied to some specific peripherals.

Reuse this function from the linux kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-03 22:56:18 +01:00
Stefano Babic
f6dc192e14 MX35: Drop unnecessary prototypes from imx-regs.h
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:18 +01:00
Stefano Babic
324a131e7c MX35: factorize common assembly code
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:18 +01:00
Stefano Babic
d330883f03 MX35: add reset cause as provided by other i.MX
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:17 +01:00
Stefano Babic
e0a83cc1f5 MX35: add pins definition for UART3
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:17 +01:00
Stefano Babic
9d940442d3 MX35: added ESDC structure to imx-regs
The structure and PLL defines are added to
the imx-regs.h file and dropped from board
header files.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:17 +01:00
Mike Frysinger
fec79acc86 sandbox: drop unused return
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Simon Glass <sjg@chromium.org>
2011-11-03 22:35:25 +01:00
Mike Frysinger
ab06a758b9 sandbox: put stdin into raw mode
This allows us to act like a serial device: we get tab chars and CTRL+C
and respond appropriately.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Simon Glass <sjg@chromium.org>
2011-11-03 22:35:21 +01:00
Anton staaf
cceea66bfe sandbox: Add asm/cache.h for sandbox
This file is required by the new DMA buffer alignment macro.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-03 22:34:49 +01:00
Wolfgang Denk
cca4e4aec1 Reduce build times
U-Boot Makefiles contain a number of tests for compiler features etc.
which so far are executed again and again.  On some architectures
(especially ARM) this results in a large number of calls to gcc.

This patch makes sure to run such tests only once, thus largely
reducing the number of "execve" system calls.

Example: number of "execve" system calls for building the "P2020DS"
(Power Architecture) and "qong" (ARM) boards, measured as:
	-> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board>
	-> grep execve /tmp/foo | wc -l

	Before: After:	Reduction:
==================================
P2020DS 20555	15205	-26%
qong	31692	14490	-54%

As a result, built times are significantly reduced, typically by
30...50%.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Albert Aribaud <albert.aribaud@free.fr>
cc: Graeme Russ <graeme.russ@gmail.com>
cc: Mike Frysinger <vapier@gentoo.org>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
Tested-by: Sanjeev Premi <premi@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-11-03 20:44:58 +01:00
Wolfgang Denk
e5d5ed4b20 4xx_pci.c: add error checking, fix GCC 4.6 build warning
Fix:
4xx_pci.c: In function 'pci_init_board':
4xx_pci.c:855:6: warning: variable 'busno' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
2011-11-03 20:40:38 +01:00
Wolfgang Denk
32bb34a768 4xx_uart.c: fix GCC 4.6 build warnings
Fix:
4xx_uart.c: In function 'get_serial_clock':
4xx_uart.c:204:6: warning: variable 'tmp' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
2011-11-03 20:39:49 +01:00
Wolfgang Denk
a9f4fc3fe5 arch/powerpc/lib/board.c: fix build warning
Commit 1272592 "powerpc: Use getenv_ulong() in place of getenv(),
strtoul" instroduced a build warning for some PPC systems:

board.c: In function 'board_init_r':
board.c:626: warning: unused variable 's'

Fix it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2011-11-03 20:37:27 +01:00
Wolfgang Denk
24769c151e Merge branch 'master' of git://git.denx.de/u-boot-mmc
* 'master' of git://git.denx.de/u-boot-mmc:
  tegra2: Move MMC clock initialization into MMC driver
  mmc: sdhci: fix sdma bug for large file transfer
  mmc: sdhci: add timeout for data transfer
  mmc: sdhci: add mmc structure for host
  mmc: sdhci: fix build warning
  mmc: sdhci: fix cache flush
  mmc: CMD7:MMC_CMD_SELECT_CARD response fix
  mmc: test mmc bus width on startup
  mmc: change magic number to macro define
  mmc: mv_sdhci: fix 8bus width access for 88SV331xV5
  mmc: retry the cmd8 to meet 74 clocks requirement in the spec
  PXA: Add MMC driver using the generic MMC framework
2011-11-03 20:36:16 +01:00
Wolfgang Denk
e84fb175f6 Merge branch 'master' of git://git.denx.de/u-boot-x86
* 'master' of git://git.denx.de/u-boot-x86:
  x86: Fix a compiler warning in arch/x86/lib/realmode.c
  x86: Remove the prototype for the unused function board_init
  x86: Rename include/asm/ic to include/asm/arch-sc520
  x86: turn off cache: set control register properly
2011-11-03 20:36:04 +01:00
Marek Vasut
07133f2e7b PXA: Add MMC driver using the generic MMC framework
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-11-03 02:14:58 -05:00
Gabe Black
4c1c355a68 x86: Fix a compiler warning in arch/x86/lib/realmode.c
Ensure that the value being passed to a %d format specifier is of type
int.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-11-02 21:45:38 +11:00
Gabe Black
fdb711528c x86: Remove the prototype for the unused function board_init
Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-11-02 21:08:16 +11:00
Graeme Russ
3c7db1beac x86: Rename include/asm/ic to include/asm/arch-sc520
Also include some trivial related cleanups
2011-11-02 20:49:17 +11:00
Ondrej Kupka
7b3d5380ee x86: turn off cache: set control register properly
Bits should be ORed when they are supposed to be added together

Signed-off-by: Ondrej Kupka <ondra.cap@gmail.com>
2011-11-02 20:48:30 +11:00
Macpaul Lin
a53ef5e4ba nds32: asm/io.h: add __iormb __iowmb and inline io support
1. This patch add required __iormb and __iowmb to io.h.
   This also fix some misbehavior to periphal drivers.
   This io.h has been fixed with referencing arm/include/asm/io.h.
2. This patch replaced macro writeb and readb into inline function.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-01 12:47:30 +08:00
Macpaul Lin
466e73b19b nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Add ARCH_DMA_MINALIGN definition to asm/cache.h

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-01 12:47:17 +08:00
Macpaul Lin
569bc625e3 nds32: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-11-01 12:47:17 +08:00
Joachim Foerster
4279c53e5b nios2: Offer ft_board_setup() capability and call fdt_fixup_ethernet().
The main motivation is, to have the local-mac-address property of the
ethernet peripherals fixed/synced with U-Boot's environment settings.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2011-10-30 21:02:43 +08:00
Joachim Foerster
03d67e1276 gpio: Add driver for Altera's PIO core
This driver may handle multiple PIO cores and thus needs to be
setup by calling the altera_pio_init() function within the early
board setup routine.

The driver comes with some extras, see below the copyleft header.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Tested-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2011-10-28 09:50:49 +08:00
Joachim Foerster
f956ad98b2 nios2: Pseudo implement dcache_status/enable/disable()
AFAIK the NIOS2 architecture does not have any possibility to
dynamically switch off the data cache. So _status() always reports 1 and
_enable/_disable() just issue a flush of everything.

For example, common/cmd_elf.c depends on these symbols.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2011-10-28 09:50:13 +08:00
Wolfgang Denk
87a5d60103 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM: Add Calxeda Highbank platform
  dkb: make mmc command as default enabled
  Marvell: dkb: add mmc support
  ARM: pantheon: add mmc definition
  davinci: remove config.mk file from the sources
  ARM:AM33XX: Add support for TI AM335X EVM
  ARM:AM33XX: Added timer support
  ARM:AM33XX: Add emif/ddr support
  ARM:AM33XX: Add clock definitions
  ARM:AM33XX: Added support for AM33xx
  omap3/emif4: fix registers definition
  davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
  davinci: emac: add support for more than 1 PHYs
  davinci: emac: add new features to autonegotiate for EMAC
  da850evm: Move LPSC configuration to board_early_init_f()
  omap4_panda: Build in cmd_gpio support on panda
  omap: Don't use gpio_free to change direction to input
  mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
  OMAP3: overo : Add environment variable optargs to bootargs
  OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
  OMAP3: overo : Use ttyO2 instead of ttyS2.
  da830: add support for NAND boot mode
  dm36x: revert cache disable patch
  dm644X: revert cache disable patch
  devkit8000: Add malloc space
  omap: spl: fix build break due to changes in FAT
  OMAP3 SPL: Provide weak omap_rev_string
  omap: beagle: Use ubifs instead of jffs2 for nand boot
  omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
  omap: overo: Configure mux for gpio10
  SPL: Add DMA library
  omap3: Add interface for omap3 DMA
  omap3: Add DMA register accessors
  omap3: Add Base register for DMA
  arm, davinci: add missing LSPC define for MMC/SD1
  U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
  DaVinci: correct MDSTAT.STATE mask
  omap4: splitting padconfs into common, 4430 and 4460
  omap4: adding revision detection for 4460 ES1.1
  omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
  gplug: fixed build error as a result of code cleanup patch
  kirkwood_spi: add dummy spi_init()
  gpio: mvmfp: reduce include platform file
  ARM: orion5x: reduce dependence of including platform file
  serial: reduce include platform file for marvell chip
  ARM: kirkwood: reduce dependence of including platform file
  ARM: armada100: reduce dependence of including platform file
  ARM: pantheon: reduce dependence of including platform file
  Armada100: Add env storage support for Marvell gplugD
  Armada100: Add SPI flash support for Marvell gplugD
  Armada100: Add SPI support for Marvell gplugD
  SPI: Add SPI driver support for Marvell Armada100
  dreamplug: initial board support.
  imx: fix coding style
  misc: pmic: drop old Freescale's pmic driver
  MX31: mx31pdk: use new pmic driver
  MX31: mx31ads: use new pmic driver
  MX31: mx31_litekit: use new pmic driver
  MX5: mx53evk: use new pmic driver
  MX5: mx51evk: use new pmic driver
  MX35: mx35pdk: use new pmic driver
  misc: pmic: addI2C  support to pmic_fsl driver
  misc: pmic: use I2C_SET_BUS in pmic I2C
  MX5: efikamx/efikasb: use new pmic driver
  MX3: qong: use new pmic driver
  RTC: Switch mc13783 to generic pmic code
  MX5: vision2: use new pmic driver
  misc: pmic: Freescale PMIC switches to generic PMIC driver
  misc:pmic:samsung Enable PMIC driver at GONI target
  misc:pmic:max8998 MAX8998 support at a new PMIC driver.
  misc:pmic:core New generic PMIC driver
  mx31pdk: Remove unneeded config
  mx31: provide readable WEIM CS accessor
  MX51: vision2: Set global macros
  I2C: Add i2c_get/set_speed() to mxc_i2c.c
  ARM: Update mach-types
  devkit8000: Add config to enable SPL MMC boot
  devkit8000: protect board_mmc_init
  arm, post: add missing post_time_ms for arm
  cosmetic, post: Codingstyle cleanup
  arm, logbuffer: make it compileclean
  tegra2: Enable MMC for Seaboard
  tegra2: Add more pinmux functions
  tegra2: Rename PIN_ to PINGRP_
  tegra2: Add more clock functions
  tegra2: Clean up board code a little
  tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
2011-10-28 00:15:19 +02:00
Wolfgang Denk
606a76f8ef Merge branch 'master' of git://git.denx.de/u-boot-microblaze
* 'master' of git://git.denx.de/u-boot-microblaze:
  microblaze: Fix strict-aliasing rules for in_be32
  microblaze: Wire up axi_ethernet driver initialization
2011-10-28 00:14:16 +02:00
Marek Vasut
3ff915e886 GCC4.6: Squash warnings in omap4 clocks.c
clocks.c:606:2: warning: format '%08x' expects type 'unsigned int', but argument
2 has type 'u32 * const'
clocks.c:633:2: warning: format '%08x' expects type 'unsigned int', but argument
2 has type 'u32 * const'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:09 +02:00
Marek Vasut
4a34af7114 GCC4.6: Squash warning in tegra2 board.c
board.c:43:2: warning: format '%08lX' expects type 'long unsigned int', but
argument 2 has type 'u32'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:09 +02:00
Marek Vasut
7f2229b5c5 GCC4.6: Squash warnings in mpc86xx/interrupts.c
interrupts.c: In function 'interrupt_init_cpu':
interrupts.c:62: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
interrupts.c:69: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:72: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:75: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:79: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'
interrupts.c:83: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'volatile uint *'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:01 +02:00
Marek Vasut
cd84b1fabf GCC4.6: Squash warnings in ddr[123]_dimm_params.c
ddr1_dimm_params.c: In function 'compute_ranksize':
ddr1_dimm_params.c:44: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'

ddr2_dimm_params.c: In function 'compute_ranksize':
ddr2_dimm_params.c:43: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'

ddr3_dimm_params.c: In function 'compute_ranksize':
ddr3_dimm_params.c:74: warning: format '%16lx' expects type 'long unsigned int',
but argument 2 has type 'long long unsigned int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 23:54:00 +02:00
Marek Vasut
e7fb8ba3a7 GCC4.6: Squash warnings in 4xx_pcie.c
4xx_pcie.c: In function 'pcie_read_config':
4xx_pcie.c:268: warning: format '%08x' expects type 'unsigned int', but argument
3 has type 'volatile unsigned char *'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:00 +02:00
Marek Vasut
bd78ef90e6 GCC4.6: Squash warnings in 4xx_ibm_ddr2_autocalib.c
4xx_ibm_ddr2_autocalib.c: In function 'DQS_calibration_methodB':
4xx_ibm_ddr2_autocalib.c:910: warning: format '%08X' expects type 'unsigned
int', but argument 2 has type 'ulong'
4xx_ibm_ddr2_autocalib.c:911: warning: format '%08X' expects type 'unsigned
int', but argument 2 has type 'ulong'
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
4xx_ibm_ddr2_autocalib.c:1217: warning: format '%08x' expects type 'unsigned
int', but argument 2 has type 'ulong'
4xx_ibm_ddr2_autocalib.c:1230: warning: format '%08x' expects type 'unsigned
int', but argument 2 has type 'ulong'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-10-27 23:54:00 +02:00
Marek Vasut
73dc3075ef GCC4.6: Squash warnings in 44x_spd_ddr.c
44x_spd_ddr.c: In function 'program_tr0':
44x_spd_ddr.c:823: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'long unsigned int'
44x_spd_ddr.c: In function 'program_tr1':
44x_spd_ddr.c:1054: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'long unsigned int'
44x_spd_ddr.c: In function 'program_bxcr':
44x_spd_ddr.c:1127: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 3 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 4 has
type 'long unsigned int'
44x_spd_ddr.c:1196: warning: format '%d' expects type 'int', but argument 5 has
type 'long unsigned int'
44x_spd_ddr.c:1242: warning: format '%d' expects type 'int', but argument 2 has
type 'long unsigned int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:00 +02:00
Marek Vasut
ae484ba1fa GCC4.6: Squash warnings in denali_spd_ddr2.c
denali_spd_ddr2.c: In function 'get_spd_info':
denali_spd_ddr2.c:363: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'check_frequency':
denali_spd_ddr2.c:390: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'get_dimm_size':
denali_spd_ddr2.c:473: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:474: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:475: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:476: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_03':
denali_spd_ddr2.c:571: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:604: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:604: warning: format '%d' expects type 'int', but argument 3
has type 'long unsigned int'
denali_spd_ddr2.c:643: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:644: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:645: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:646: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:676: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_04':
denali_spd_ddr2.c:731: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:733: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:735: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_05':
denali_spd_ddr2.c:772: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:774: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_06':
denali_spd_ddr2.c:831: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:833: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_11':
denali_spd_ddr2.c:860: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_26':
denali_spd_ddr2.c:931: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c:933: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_27':
denali_spd_ddr2.c:944: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_43':
denali_spd_ddr2.c:978: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_spd_ddr2.c: In function 'program_ddr0_44':
denali_spd_ddr2.c:1006: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:00 +02:00
Marek Vasut
b6d5040b0d GCC4.6: Squash warnings in denali_data_eye.c
denali_data_eye.c: In function
'denali_core_search_data_eye':denali_spd_ddr2.c:646: warning: format '%d'
expects type 'int', but argument 2 has type 'long unsigned int'

denali_data_eye.c:320: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_data_eye.c:330: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_spd_ddr2.c:676: warning: format '%d' expects type 'int', but argument 2
has type 'long unsigned int'
denali_data_eye.c:340: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_data_eye.c:350: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'
denali_data_eye.c:360: warning: format '%08lx' expects type 'long unsigned int',
but argument 2 has type 'u32'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:00 +02:00
Marek Vasut
506b9f2b2d PowerPC: Squash warning in mpc512x serial.c
serial.c: In function 'serial_setbrg_dev':
serial.c:143: warning: format '%d' expects type 'int', but argument 4 has type
'long unsigned int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:53:59 +02:00
Helmut Raiger
9660e442de cosmetic: s/BOARD_LATE_INIT/CONFIG_BOARD_LATE_INIT
This renames BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT.
Along the way it removes some leftover

 #define BOARD_LATE_INIT		1

and adds some basic documentation for board specific
callbacks in README.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-10-27 23:53:59 +02:00
Rob Herring
37fc0ed268 ARM: Add Calxeda Highbank platform
Add basic support for Calxeda Highbank platform. Only minimal support with
serial and SATA are included.

Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-10-27 21:56:37 +02:00
Lei Wen
3d90a2adcb ARM: pantheon: add mmc definition
Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-10-27 21:56:37 +02:00
Vladimir Zapolskiy
23365af099 davinci: remove config.mk file from the sources
To compile TI Davinci SoC support the identical config.mk file from
the cpu directory shall be used.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
5289e83a8c ARM:AM33XX: Add support for TI AM335X EVM
This patch adds basic support for booting the board.
This patch adds support for the UART necessary to
get to the u-boot prompt.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
f0f4b5ff50 ARM:AM33XX: Added timer support
This patch adds timer support for AM33xx platform.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
62d7fe7c91 ARM:AM33XX: Add emif/ddr support
This patch adds AM33xx emif/ddr support along with board specific
defines.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
f87fa62af9 ARM:AM33XX: Add clock definitions
This patch adds basic clock definition of am33xx SoC.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Chandan Nath
5655108a82 ARM:AM33XX: Added support for AM33xx
This patch adds basic support for AM33xx which is based on ARMV7
Cortex A8 CPU.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Ilya Yanok
40b95c8956 omap3/emif4: fix registers definition
Fix EMIF4 registers definition.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Manjunath Hadli
fb1d6332b5 davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
remove macro CONFIG_EMAC_MDIO_PHY_NUM and depending macro EMAC_MDIO_PHY_NUM
as they are no longer needed with the support for more than 1 PHYs in davinci
emac driver.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:36 +02:00
Joe Hershberger
b5db0a068a omap: Don't use gpio_free to change direction to input
gpio_free() should not have the side effect of setting the line to input since this prevents the gpio command from being able to set a line as output.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:35 +02:00
Aneesh V
2d01dd953a omap: spl: fix build break due to changes in FAT
FAT library now uses malloc() and free(). But SPL doesn't
have heap until now. Setup a heap in SDRAM to fix this issue.

However this increases SPL footprint beyond the available SRAM
budget. So, compile out some fancy features in the SDARM init
bring back footprint under control

CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Wolfgang Denk <wd@denx.de>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:35 +02:00
Tom Rini
cc3f705843 OMAP3 SPL: Provide weak omap_rev_string
We add an weak version of omap_rev_string in omap-common/spl.c
and while at it drop the omap3 version.  Move the prototype over
to <asm/omap_common.h> with the other SPL functions.

Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:35 +02:00
Simon Schwarz
4c4bb19d05 omap3: Add interface for omap3 DMA
Adds an interface to use the OMAP3 DMA.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:34 +02:00
Simon Schwarz
7b646a6d12 omap3: Add DMA register accessors
Adding the register definitions for omap3 DMA controller to cpu.h

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:34 +02:00
Simon Schwarz
9c60c55be8 omap3: Add Base register for DMA
Adding the base register address of OMAP3 DMA controller.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:34 +02:00
Heiko Schocher
2bc3acb10a arm, davinci: add missing LSPC define for MMC/SD1
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:34 +02:00
Sergei Shtylyov
9e2538e11f DaVinci: correct MDSTAT.STATE mask
MDSTAT.STATE occupies bits 0..5 according to all available documentation, so fix
the mask which previously was leaving out the intermediate state indicator bit.

While at it, introduce two #define's for that mask -- unfortunately, we can't
use a single #define as the assembly code can't include <asm/arch/hardware.h>
due to C-specfic constructs in it.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:34 +02:00
Ricardo Salveti de Araujo
53430a4f25 omap4: splitting padconfs into common, 4430 and 4460
Not all padconfs are the same between 4430 and 4460, so instead of
working around this with an if, we should have an specific padconf
structure for both chips (like handling the differences between the LEDs
GPIOs and TPS).

Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:34 +02:00
Ricardo Salveti de Araujo
8f6a027f62 omap4: adding revision detection for 4460 ES1.1
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>

 2 files changed, 17 insertions(+), 1 deletions(-)
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:33 +02:00
Ricardo Salveti de Araujo
20033c9f87 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
OMAP4460 has a different set of values for the ID code, so moving the
old ones to be related just with 4430.

Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-10-27 21:56:33 +02:00
Lei Wen
5ff8b35412 ARM: orion5x: reduce dependence of including platform file
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to
the definition in the platform definition files.

Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-10-27 21:56:33 +02:00
Lei Wen
a7efd719f4 ARM: kirkwood: reduce dependence of including platform file
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the
definition in the platform definition files.

Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-10-27 21:56:33 +02:00
Lei Wen
ab1b955211 ARM: armada100: reduce dependence of including platform file
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the
definition in the platform definition files.

Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.

Updated cpu.h to remove build errors for gplugd board (by prafulla)

Signed-off-by: Lei Wen <leiwen@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2011-10-27 21:56:33 +02:00
Lei Wen
0c0d9b708b ARM: pantheon: reduce dependence of including platform file
For files like the drivers/serial/serial.c, it must include the platform
file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in
the platform definition files.

Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.

Signed-off-by: Lei Wen <leiwen@marvell.com>
2011-10-27 21:56:33 +02:00
Ajay Bhargav
daa4b2f7f5 Armada100: Add SPI support for Marvell gplugD
This patch add SPI driver support for Marvell gplugD

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-10-27 21:56:32 +02:00
Ajay Bhargav
51100cfcca SPI: Add SPI driver support for Marvell Armada100
This patch provides support for SPI emulated over SSP for Marvell
Armada100 SOC.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-10-27 21:56:32 +02:00
Jason Cooper
2e0c1c7d5c dreamplug: initial board support.
Copied wholeheartedly from board/Marvell/guruplug and modified to add support
for SPI NOR flash.

CONFIG_MACH_DREAMPLUG defined in include/configs/dreamplug.h until Linus's
kernel.org tree adds it to mach-types.h.  Once it trickles down, the definition
can be removed from include/configs/dreamplug.h.

Signed-off-by: Jason Cooper <u-boot@lakedaemon.net>
2011-10-27 21:56:32 +02:00
Fabio Estevam
77f11a99e1 imx: fix coding style
Fix checkpatch warning and errors in several i.MX related files.

While at it also address a checkpatch warning at arch/arm/cpu/armv7/mx5/soc.c
regarding the usage of extern in a C file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-10-27 21:56:32 +02:00
Helmut Raiger
47c5455a48 mx31: provide readable WEIM CS accessor
setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:30 +02:00
Marek Vasut
47af6f61bc ARM: Update mach-types
This commit updates the mach-types based on the latest in Linus's head

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-10-27 21:56:30 +02:00
Heiko Schocher
ee4014b005 arm, logbuffer: make it compileclean
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-10-27 21:56:30 +02:00
Simon Glass
20e18e051f tegra2: Add more pinmux functions
This adds support for changing pinmux functions of pin groups. This is done
by defining a PMUX_FUNC_... enum which can be used to select the function for
each group using pinmux_set_func(). It is also possible to enable
pullup/pulldown, and the existing tristate functionality is retained.

Also provided is a means of configuring a list of pingroups by providing a
configuration table to pinmux_config_table().

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
2011-10-27 21:56:29 +02:00
Simon Glass
c3cf49d247 tegra2: Rename PIN_ to PINGRP_
The pin groupings are better named PINGRP, since on Tegra2 they refer to
multiple pins.

Sorry about this, but better to get it right now when there is only a small
amount of code affected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
2011-10-27 21:56:29 +02:00
Simon Glass
4ed59e70e4 tegra2: Add more clock functions
This adds most of the clock functions required by board and driver code:

-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control

These functions are plumbed in as required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
2011-10-27 21:56:29 +02:00
Simon Glass
03c609f69b tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the
code now deals with both PLL clocks and source clocks.

This also tidied up the assert() to match the one sent upstream, and fixes
an error in the PWM id.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
2011-10-27 21:56:29 +02:00
Simon Glass
eea63e05d0 fdt: ARM: Add fdtcontroladdr to set device tree address in environment
This adds support for a new environment variable called 'fdtcontroladdr'. If
defined, the hex address is used as the address of the control fdt for U-Boot.

Note: I have not changed CONFIG_PRAM section as I already have an
outstanding patch on that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-26 21:40:16 +02:00
Simon Glass
f5437ad141 fdt: ARM: Implement and verify embedded and separate device tree
This locates the device tree either embedded within U-Boot or attached to the
end as a separate binary.

When CONFIG_OF_CONTROL is defined, U-Boot requires a valid fdt. A check is
provided for this early in initialisation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-26 21:39:57 +02:00
Simon Glass
45ba8077f3 fdt: ARM: Add device tree control of U-Boot (CONFIG_OF_CONTROL)
This adds a device tree pointer to the global data. It can be set by
board code. A later commit will add support for making a device
tree binary blob available to U-Boot for run-time configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-26 21:37:17 +02:00
Simon Glass
bc4e14c43c arm: Correct build error introduced by getenv_ulong() patch
Commit dc8bbea removed a local variable that is used in most ARM boards.

Since we want to avoid an 'unused variable' warning with later compilers,
and the #ifdef logic of whether this variable is required is bit painful,
this declares the variable local to the block of code that needs it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-24 21:13:51 +02:00
Simon Glass
aab773a47a powerpc: Correct build warning introduced by getenv_ulong() patch
Commit 1272592 introduced a warning since the variable 's' is no longer
always used, depending on the CONFIG options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-24 21:13:15 +02:00
Michal Simek
1fbd0c36da microblaze: Fix strict-aliasing rules for in_be32
readl should work with unsigned int instead of unsigned long.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-24 07:57:03 +02:00
Bernhard Kaindl
9d256b67f6 powerpc/lib/board.c: Call run_post(POST_ROM) before relocating
The call to run_post(POST_ROM) which can run the POST memory test
is currently called too late when gd has already been copied to DRAM.

This results in failure to boot Linux after a POST_ROM memory test
tested all RAM while gd was already relocated to DRAM due to gd being
overwritten by the POST_ROM memory test.

Support this by moving the call to run_post(POST_ROM) to run earlier,
before U-Boot has started to move data to DRAM (from late board_init_f
to early board_init_f) where DRAM is initialized, but not used yet.

This allows that an POST memory test can test the whole DRAM,
including the area where the board info struct is located.

Signed-off-by: Bernhard Kaindl <bernhard.kaindl@thalesgroup.com>
Cc: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>
2011-10-23 23:34:19 +02:00
Simon Glass
f5ca20c6b6 x86: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:34:19 +02:00
Simon Glass
745937438f sparc: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:33:19 +02:00
Simon Glass
1272592e4b powerpc: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2011-10-23 23:33:19 +02:00
Simon Glass
98e4611f10 mips: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:33:19 +02:00
Simon Glass
94e4dae9fa microblaze: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:33:18 +02:00
Simon Glass
77b8f2033b m68k: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:33:18 +02:00
Simon Glass
c1f485a1e8 blackfin: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-23 23:33:18 +02:00
Simon Glass
eb68b41d5a avr32: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:33:17 +02:00
Simon Glass
dc8bbea017 arm: Use getenv_ulong() in place of getenv(), strtoul
This changes the board code to use the new getenv_ulong() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-23 23:33:17 +02:00
Anton Staaf
3620f860ef x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Graeme Russ <graeme.russ@gmail.com>
2011-10-23 20:50:43 +02:00
Anton Staaf
72d4dd4159 mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
2011-10-23 20:50:43 +02:00
Anton Staaf
ee729afde3 microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Michal Simek <monstr@monstr.eu>
2011-10-23 20:50:43 +02:00
Anton Staaf
75ff24be47 avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-10-23 20:50:42 +02:00
Anton Staaf
3c3f8a7f3e sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
2011-10-23 20:50:42 +02:00
Anton Staaf
2482e3c836 sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-10-23 20:50:42 +02:00
Anton Staaf
0991701a27 powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
2011-10-23 20:50:42 +02:00
Anton Staaf
6fa6035ff2 nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Scott McNutt <smcnutt@psyent.com>
2011-10-23 20:50:42 +02:00
Anton Staaf
a8fc12eb8e m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
2011-10-23 20:50:42 +02:00
Anton Staaf
44d6cbb6a7 arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-10-23 20:50:42 +02:00
Mike Frysinger
26ddff2d8d build: add missing $(AR)->$(cmd_link_o_target) update
Seems people fixed their files to use libfoo.o, but didn't actually
update the creation targets to use $(cmd_link_o_target).  Update the
rest of the Makefile's found with grep.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Simon Glass <sjg@chromium.org>
2011-10-22 01:18:41 +02:00
Anatolij Gustschin
c4c9fbebae consolidate mdelay by providing a common function for all users
There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-22 01:16:08 +02:00
Macpaul Lin
463d47f66c nds32/lib: add generic funcs in NDS32 lib
Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-10-22 00:53:11 +02:00
Macpaul Lin
445a886d7a nds32/ag101: cpu and init funcs of SoC ag101
SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-10-22 00:52:51 +02:00
Macpaul Lin
37e5708afa nds32/core N1213: NDS32 N12 core family N1213
Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.

Start procedure:
 start.S will start up the N1213 CPU core at first,
 then jump to SoC dependent "lowlevel_init.S" and
 "watchdog.S" to configure peripheral devices.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
2011-10-22 00:52:36 +02:00
Macpaul Lin
00f892fcc9 nds32: add header files support for nds32
Add generic header files support for nds32 architecture.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-10-22 00:51:37 +02:00
Wolfgang Denk
02aff558f4 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  mpc85xx: Add inline GPIO acessor functions
  powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
  powerpc/85xx: Fix P2020DS booting
  powerpc/85xx: Update USB device tree status based on pin settings
  fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers
  powerpc/85xx: Add support for RMan LIODN initialization
  powerpc/85xx: Update device tree handling for SRIO
  powerpc/85xx: Update setting of SRIO LIODNs
  fm: Don't allow disabling of FM1-DTSEC1
  fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree
2011-10-21 23:48:46 +02:00
Kyle Moffett
710308ee18 mpc85xx: Add inline GPIO acessor functions
To ease the implementation of other MPC85xx board ports, several common
GPIO helpers are added to <asm/mpc85xx_gpio.h>.

Since each of these compiles to no more than 4-5 instructions it would
be very inefficient to call them out of line, therefore we put them
entirely in the header file.

The HWW-1U-1A board port which these were written for strongly prefers
to set multiple GPIOs as a single batch operation, so the API is
designed around that basis.

To assist other board ports, a small set of wrappers are used which
provides a standard gpio_request() interface around the MPC85xx-specific
functions.  This can be enabled with CONFIG_MPC85XX_GENERIC_GPIO

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-21 00:04:28 -05:00
Timur Tabi
a836626cc4 powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 16:01:37 -05:00
stany MARCEL
aa2bd9b015 ColdFire: Add $(obj) before cpu lib to correct build
Missing $(obj) prevented the build of ColdFire boards in a directory
than sources

Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
2011-10-19 00:13:17 +08:00
Shengzhou Liu
f81f19fafa powerpc/85xx: Update USB device tree status based on pin settings
For P3060 and P4080, USB pins are multiplexed with other functions.
Update the device tree status for USB ports based on setting of
RCW[EC1] & RCW[EC2] which describe if pins are muxed to usb.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:37:31 -05:00
Kumar Gala
4d28db8a1e powerpc/85xx: Add support for RMan LIODN initialization
This patch is intended to initialize RMan LIODN related registers on
P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to
qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:48 -05:00
Kumar Gala
9c42ef6145 powerpc/85xx: Update device tree handling for SRIO
Update device tree handling for SRIO controller to support updated
fsl,srio device tree binding.

We handle disabling of individual ports, the whole controller, RMU, and
RMAN.  Additionally, we setup the SRIO related LIODNs in the device
tree.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:43 -05:00
Kumar Gala
1a0c64219d powerpc/85xx: Update setting of SRIO LIODNs
Properly set the LIODN values associated with SRIO controller.  On
P4080/P3060 we have an LIODN per port and one for the RMU.  On
P2041/P3041/P5020 we have 2 LIODNs per port.

Update the tables for all of these devices to properly handle both
styles.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:15 -05:00
Simon Glass
efb2172ece Move timestamp and version files into 'generated' subdir
There is a rather subtle build problem where the build time stamp is not
updated for out-of-tree builds if there exists an in-tree build which
has a valid timestamp file. So if you do an in-tree build, then an
out-of-tree build your timestamp will not change.

The correct timestamp_autogenerated.h lives in the object tree, but it
is not always found there. The source still lives in the source tree and
when compiling version.h, it includes timestamp_autogenerated.h. Since
the current directory is always searched first, this will come from the
source tree rather than the object tree if it exists there. This affects
dependency generation also, which means that common/cmd_version.o will not
even be rebuilt if you have ever done an in-tree build.

A similar problem exists with the version file.

This change moves both files into the 'generated' subdir, which is already
used for asm-offsets.h. Then timestamp.h and version.h are updated to
include the files from there.

There are other places where these generated files are included, but I
cannot see why these don't just use the timestamp.h and version.h headers.
So this change also tidies that up.

I have tested this with in- and out-of-tree builds, but not SPL. I have
looked at various other options for fixing this, including sed on the dep
files, -I- and -include flags to gcc, but I don't think they can be made
to work. Comments welcome.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-17 23:57:00 +02:00
Simon Glass
bace3d00f2 sandbox: Add main program
Add a main program so that we can run U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-17 23:56:58 +02:00
Simon Glass
7a9219c17a sandbox: Add OS dependent layer
We want to keep all OS-dependent code in once place, with a simple interface
to U-Boot. For now, this is that place.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-17 23:56:58 +02:00
Simon Glass
b8605a1cbd sandbox: Add architecture lib files
These files are taken from the ARM board implementation and then reduced
to remove unneeded cruft.

Ideally we would work towards unifying arch/xxx/lib files, particularly
board.c.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-17 23:53:46 +02:00
Simon Glass
4b0730d242 sandbox: Add cpu files
This is an initial implementation with all functions defined but not working.

The lds file is very simple since we can mostly rely on the linker defaults.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-17 23:53:46 +02:00
Simon Glass
65bf1d39f4 sandbox: Add architecture image support
We won't actually load an image with this architecture, but we still need to
define it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-17 22:46:38 +02:00
Simon Glass
744d9859a7 sandbox: Add architecture header files
This adds required header files for the sandbox architecture, and a basic
description of what sandbox is (README.sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2011-10-17 22:45:50 +02:00
Mike Frysinger
5aa5b88404 Blackfin: define CONFIG_SYS_CACHELINE_SIZE
Common U-Boot API wants this define, so import asm/cache.h from Linux
to provide suitable defines.

Acked-by: Anton Staaf <robotboy@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-17 22:25:32 +02:00
Helmut Raiger
3f480bf7c3 mx31: make HSP clock for mx3fb driver available
This additionally updates mx31/generic.c by
- replacing __REG() macro accesses with readl() and writel()
- providing macros for PDR0 and PLL bit accesses

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-10-17 22:25:32 +02:00
Mike Frysinger
464c79207c punt unused clean/distclean targets
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used.  Punt them all.

MAKEALL didn't report any errors related to this that I could see.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-15 22:20:36 +02:00
Wolfgang Denk
7bf5228ce1 Merge branch 'master' of git://git.denx.de/u-boot-fdt
* 'master' of git://git.denx.de/u-boot-fdt:
  powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
  fdt: update fdt_alloc_phandle to use fdt_get_phandle
  fdt: check for fdt errors in fdt_create_phandle
  fdt: Add a do_fixup_by_path_string() function
2011-10-15 22:00:01 +02:00
Timur Tabi
a2c1229c39 powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
Function fdt_create_phandle() conveniently creates new phandle properties
using both "linux,phandle" and "phandle", so it should be used by all code
that wants to create a phandle.

The Fman firmware code, which embeds an Fman firmware into the device tree,
was creating the phandle properties manually.  Instead, change it to use
fdt_create_phandle().

Signed-off-by: Timur Tabi <timur@freescale.com>
2011-10-15 09:35:15 -04:00
Timur Tabi
7f92c3a275 powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:10 -05:00
Haiying Wang
34fdbdf8d9 powerpc/p3041: fixup portal config info
P3041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
  are utilized the proper mapping tables can be setup uniquely
  (PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
  assignments are tuned around an assumption of at most 5
  partitions.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:10 -05:00
Haiying Wang
510f28cff9 powerpc/p2041: fixup portal config info
P2041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
  are utilized the proper mapping tables can be setup uniquely
  (PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
  assignments are tuned around an assumption of at most 5
  partitions.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:10 -05:00
Haiying Wang
7c7bd635be powerpc/p5020: fixup portal config info
P5020 has 10 qman portals, we need to configure all of them:
* As there are only 2 physical cores sdest can only be 0 or 1
* We assign dqrr & frame data LIODNs for all portals so if they
  are utilized the proper mapping tables can be setup uniquely
  (PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
  assignments are tuned around an assumption of at most 5
  partitions.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:09 -05:00
Wolfgang Denk
d8fffa057c Merge branch 'master' of git://git.denx.de/u-boot-mips
* 'master' of git://git.denx.de/u-boot-mips:
  MIPS: Jz4740: Add qi_lb60 board support
  MIPS: Jz4740: Add NAND driver
  MIPS: Ingenic XBurst Jz4740 processor support
2011-10-12 22:47:15 +02:00
Wolfgang Denk
37eefe80bb Merge branch 'master' of git://git.denx.de/u-boot-microblaze
* 'master' of git://git.denx.de/u-boot-microblaze:
  microblaze: Copy bootfile from variables
  microblaze: Fix unaligned.h for endians
  microblaze: Initialize jumptable and console
  microblaze: Support flashes on lower addresses
  microblaze: Call common console_init_f initialization function
2011-10-12 22:42:28 +02:00
Xiangfu Liu
80421fcc3e MIPS: Ingenic XBurst Jz4740 processor support
Jz4740 is a multimedia application processor targeting for mobile
devices like e-Dictionary, eBook, portable media player (PMP) and
GPS navigator.  Jz4740 is powered by Ingenic 360 MHz XBurst CPU core
(JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture
provides high integration, high performance and low power consumption.

JzRISC incorporated in Jz4740 is the advanced and power-efficient
32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K
D-Cache, and can operate at speeds up to 400 MHz.

On-chip modules such as LCD controller, embedded audio codec, multi-
channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich
suite of peripherals for multimedia application.  NAND controller
(SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are
also available.

For more info about Ingenic XBurst Jz4740:
  http://en.ingenic.cn/eng/
  http://www.linux-mips.org/wiki/Ingenic

This patch introduces XBurst CPU support in U-Boot.  It's compatible
with MIPS32, but requires a bit different cache maintenance, timer
routines, and boot mechanism using USB boot tool, so XBurst support
can go into a separate new home, cpu/xburst/.

Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-10-10 22:06:12 +09:00
Michal Simek
2267e2d132 microblaze: Copy bootfile from variables
Setup bootfile.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-10 08:54:42 +02:00
Michal Simek
6cdf31124c microblaze: Fix unaligned.h for endians
Also support little endian MB.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-10 08:54:28 +02:00
Michal Simek
aa7acdd509 microblaze: Initialize jumptable and console
This changes were done to get support for netconsole.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-10 08:54:21 +02:00
Michal Simek
a93c1a171c microblaze: Support flashes on lower addresses
Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-10 08:54:20 +02:00
Michal Simek
077a4e6b98 microblaze: Call common console_init_f initialization function
Calling console_init_f enables CTRL+C usage.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-10 08:54:19 +02:00
Xie Xiaobo
ae2044d8b3 powerpc/mpc8536ds: Add eSPI support for MPC8536DS
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
   so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
   to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.

Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:54 -05:00
Becky Bruce
1605cc9e1b powerpc/mpc86xx: Disable translation for BAT setup
We really shouldn't be overwriting bat registers with translation enabled,
especially when we're executing code using one of them for translating
the current instruction stream.  Instead, disable address translation
while doing the final BAT setup.

In order to do this, setup_bats has to move back to asm code, because we
require translation to be enabled to have a stack for C code.  The yucky
thing about that is that the assembler doesn't like ULL so we have to
switch to using HIGH/LOW pairs for physical addresses that are > 32 bits
in length.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:54 -05:00
Timur Tabi
3038171628 powerpc/85xx: fix null pointer dereference when init the SGMII TBI PHY
Function dtsec_configure_serdes() needs to know where the TBI PHY registers
are in order to configure SGMII for proper SerDes operation.

During SGMII initialzation, fm_eth_init_mac() passing NULL for 'phyregs'
when it called init_dtsec(), because it was believed that phyregs was not
used.  In fact, it is used by dtsec_configure_serdes() to configure the TBI
PHY registers.

We also need to define the PHY registers in struct fm_mdio.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:53 -05:00
York Sun
6f5e1dc531 powerpc/8xxx: Add support for interactive DDR programming interface
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.

To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:

setenv ddr_interactive on

After reset, U-boot prompts before initializing DDR controllers
FSL DDR>

The available commands are
print      print SPD and intermediate computed data
reset      reboot machine
recompute  reload SPD and options to default and recompute regs
edit       modify spd, parameter, or option
compute    recompute registers from current next_step to end
next_step  shows current next_step
help       this message
go         program the memory controller and continue with u-boot

The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:53 -05:00
Wolfgang Denk
0841ca90f2 arm920t/s3c24x0/usb_ohci.c: fix warning: variable ... set but not used
Fix:
usb_ohci.c: In function 'dl_transfer_length':
usb_ohci.c:768:8: warning: variable 'tdINFO' set but not used [-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
2011-10-09 23:24:50 +02:00
Wolfgang Denk
80c6abc306 arch/arm/lib/board.c: fix warning: variable ... set but not used
Fix:
board.c:445:8: warning: variable 'bd' set but not used [-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-10-09 23:24:48 +02:00
Mike Frysinger
31a4f1e5b6 board configs: drop NET_MULTI references
Now that none of the core checks CONFIG_NET_MULTI, there's not much point
in boards defining it.  So scrub all references to it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-05 22:22:16 +02:00
Mike Frysinger
e2a53458a7 net: drop !NET_MULTI code
This is long over due.  All but two net drivers have been converted, but
those have now been dropped.

The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined.  So here we scrub the
core code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-05 22:22:16 +02:00
Mike Frysinger
476af299b0 image: push default arch values to arch headers
This pushes the ugly duplicated arch ifdef lists we maintain in various
image related files out to the arch headers themselves.

Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-05 22:22:15 +02:00
Valentin Longchamp
79843950b2 POST: add post_log_res field for post results in global data
The current post_log_word in global data is currently split into 2x
16 bits: half for the test start, half for the test success.
Since we alredy have more than 16 POST tests defined and more could
be defined, this may result in an overflow and the post_output_backlog
would not work for the tests defined further of these 16 positions.

An additional field is added to global data so that we can now support up
to 32 (depending of architecture) tests. The post_log_word is only used
to record the start of the test and the new field post_log_res for the
test success (or failure). The post_output_backlog is for this change
also adapted.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
2011-10-05 22:03:10 +02:00
Valentin Longchamp
ea3681a6e4 POST/arm: adaptations needed for POST on ARM to work
For post to run on ARM, 3 things are needed:
- post_log_word to be defined in gd
- a post.h include in arch/arm/lib/board.c

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-05 22:03:10 +02:00
Graeme Russ
9558b48af0 console: Implement pre-console buffer
Allow redirection of console output prior to console initialisation to a
temporary buffer.

To enable this functionality, the board (or arch) must define:
 - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
 - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
 - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)

The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
Any earlier characters are silently dropped.
2011-10-05 22:03:09 +02:00
Wolfgang Denk
1fed668b3f Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/p3060: Add SoC related support for P3060 platform
  powerpc/85xx: Add support for setting up RAID engine liodns on P5020
  powerpc/85xx: Refactor some defines out of corenet_ds.h
  fm-eth: Add ability for board code to disable a port
  powerpc/mpc8548: Add workaround for erratum NMG_LBC103
  powerpc/mpc8548: Add workaround for erratum NMG_DDR120
  powerpc/mpc85xxcds: Fix PCI speed
  powerpc/mpc8548cds: Fix booting message
  powerpc/p4080: Add support for secure boot flow
  powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
  powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
  powerpc/p2041rdb: remove watch dog related codes
  powerpc/p2041rdb: updated description of cpld command
  powerpc/p2041rdb: add more ddr frequencies support
  powerpc/p2041rdb: set sysclk according to status of physical switch SW1
  powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
  powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc8xxx: Add DDR2 to unified DDR driver
  powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
  powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
  powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
  powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  powerpc/85xx: Enable CMD_REGINFO on corenet boards
  powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
  powerpc/85xx: Fix USB protocol definitions for P1020RDB
  powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
  powerpc/mpc8xxx: Move DDR RCW overriding to common code
  powerpc/mpc8xxx: Extend CWL table
  powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
  powerpc/85xx: Cleanup extern in corenet_ds board code
  powerpc/p2041rdb: Add ethernet support on P2041RDB board
  powerpc/85xx: Add networking support to P1023RDS
  powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
  powerpc/85xx: Add FMan ethernet support to P4080DS
  powerpc/85xx: Add support for FMan ethernet in Independent mode
  powerpc/mpc8548cds: Cleanup mpc8548cds.c
  powerpc/mp: add support for discontiguous cores
  powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
  fdt: Add new fdt_create_phandle helper
  fdt: Rename fdt_create_phandle to fdt_set_phandle
  powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
  fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
  powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
  fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
  powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
  powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
  nand: Freescale Integrated Flash Controller NAND support
  powerpc/85xx: Add basic support for P1010RDB
  powerpc/85xx: Add support for new P102x/P2020 RDB style boards
  powerpc/85xx: relocate CCSR before creating the initial RAM area
  powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
  powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
  powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
2011-10-04 22:08:13 +02:00
Shengzhou Liu
6d7b061af1 powerpc/p3060: Add SoC related support for P3060 platform
Add P3060 SoC specific information:cores setup, LIODN setup, etc

The P3060 SoC combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 09:36:28 -05:00
Kumar Gala
6b3a8d0086 powerpc/85xx: Add support for setting up RAID engine liodns on P5020
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020.  Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ).  This just handles RAID Engine in non-DPAA mode.

Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:15 -05:00
Kumar Gala
2b3a1cdd9e powerpc/mpc8548: Add workaround for erratum NMG_LBC103
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document.
Any local bus transaction may fail during LBIU resynchronization
process when the clock divider [CLKDIV] is changing. Ensure there
is no transaction on the local bus for at least 100 microseconds
after changing clock divider LCRR[CLKDIV].

Refer to the erratum LBIU3 of mpc8548.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:15 -05:00
Kumar Gala
5ace2992b5 powerpc/mpc8548: Add workaround for erratum NMG_DDR120
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some
early version silicons. The default settings of the DDR IO receiver
biasing may not work at cold temperature. When a failure occurs,
a DDR input latches an incorrect value. The workaround will set the
receiver to an acceptable bias point.

Signed-off-by: Gong Chen
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:14 -05:00
Ruchika Gupta
7065b7d466 powerpc/p4080: Add support for secure boot flow
Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
   (Please note that ISBC expects all these addresses, images to be
    validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
   at 0xcffffffc.

Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
   CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
   (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
    created by PBL/configuration word within 0 - 3.5G memory range. The
    u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
   PBL/configuration word after switch to AS = 1

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:14 -05:00
Michal Simek
5562bcc241 microblaze: Clean up reset asm code
- Remove code copying
- Reset address is setup from first stage bootloader
- Support reset vector setup on little endian

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03 08:01:56 +02:00
Michal Simek
f3090fce77 microblaze: Save and restore first unused vector
Use one memory space to detect little/big endian platforms.
The first unused address(0x28) is used instead 0x0 address (reset vectors).
Detection rewrited reset vector setup from first stage bootloader.

Workflow:
1. Store 0x28 to r7
2. Do little/big endian test
3. Restore r7 to 0x28

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03 08:01:56 +02:00
Michal Simek
86c1b2a86b microblaze: Setup MB vectors if feature is enable for u-boot
For example: Setup reset vectors if reset address is setup.
Setup user exception vector if user exception is enabled

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03 08:01:56 +02:00
Michal Simek
dfc10703d7 microblaze: Remove debug saving value
Forget to remove debug code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03 08:01:55 +02:00
Paul Gortmaker
b30d41cad6 sbc82xx: delete support for obsolete SBC8240/SBC8260
The EST SBC8260 is over 10 years old, and the SBC8240 older than
that.  With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com
2011-10-01 21:57:13 +02:00
Graeme Russ
e3e454cd72 console: Squelch pre-console output in console functions
There are some locations in the code which anticipate printf() being called
before the console is ready by squelching printf() on gd->have_console.
Move this squelching into printf(), vprintf(), puts() and putc(). Also
make tstc() and getc() return 0 if console is not yet initialised

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
2011-10-01 21:54:49 +02:00
Wolfgang Denk
97d7ab8a8e Merge branch 'post' of git://git.denx.de/u-boot-blackfin
* 'post' of git://git.denx.de/u-boot-blackfin:
  Blackfin: uart: implement loop callback for post
  Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range
  Blackfin: post: generalize led/button tests with GPIOs
  Blackfin: bf537-stamp: drop uart/flash post tests
  Blackfin: post: drop custom test list
  Blackfin: bf537-stamp: convert to gpio post hotkey
2011-10-01 21:42:21 +02:00
Fabio Estevam
e6ec1761cd zmx25: Fix build warning due to 'get_reset_cause' defined but not used
When building the zmx25 target we get:

Configuring for zmx25 board...
generic.c:108: warning: 'get_reset_cause' defined but not used

Fix this warning by defining get_reset_cause only if CONFIG_DISPLAY_CPUINFO is defined.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-09-30 22:01:05 +02:00
Marek Vasut
37a6d2085e MX5: Clean up the output of "clocks" command
The new output looks like this:
> clocks
PLL1            800 MHz
PLL2            665 MHz
PLL3            216 MHz

AHB          133000 kHz
IPG           66500 kHz
IPG PERCLK   665000 kHz

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-09-30 22:01:05 +02:00
Marek Vasut
95c0eb198d MX5: Add AHB clock reporting and fix IPG clock reporting
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-09-30 22:01:05 +02:00
Marek Vasut
bf2eaf5112 MX5: Modify the PLL decoding algorithm
The PLL decoding algorithm didn't take into account many configuration bits.
Adjust it according to Linux kernel. Also, add PLL4 for MX53.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Hui <jason.hui@linaro.org>
Tested-by: Jason Liu <Jason.hui@linaro.org>
2011-09-30 22:01:05 +02:00
Marek Vasut
8edcc6f221 FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.h
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2011-09-30 22:01:03 +02:00
Fabio Estevam
610b53e29b MX31: Disable watchdog during low-power modes
Turn on the watchdog WDZST bit so that watchdog timer does not count during low power modes.

Prior to applying this patch mx31pdk board got watchdog resets because when it booted in the Linux prompt
and there was no activity, the system entered into idle mode while watchdog timer was still active.

Fix this by disabling watchdog timer during idle mode.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:00 +02:00
Fabio Estevam
e6d9b9785c MX25: tx25: Avoid the usage of extern in C file
Avoid the usage of extern in C file as pointed out by checkpatch.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:00 +02:00
Fabio Estevam
b6ce47964d MX31: Improve readability for reset cause
Currently the reset cause is printed like:
CPU:   Freescale i.MX31 rev 2.0 at 531 MHz.Reset cause: POR

Improve readability by adding a new line like it is done on other i.MX boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:00 +02:00
Fabio Estevam
957dc02474 ARM: mx25: Print the source of reset
Print the source of reset during boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:00:59 +02:00
Fabio Estevam
986d0d1bc5 ARM: mx25: Print the silicon revison
Print the silicon revison during boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:00:59 +02:00
Heiko Schocher
0a0522cbff arm, davinci, da8xx: add cpuinfo
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:59 +02:00
Heiko Schocher
310ae55efe arm, davinci, am1808: add lowlevel functions for booting from NOR
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:59 +02:00
Heiko Schocher
337c433383 arm, davinci: add NOR Boot Configuration Word
to add the "NOR Boot Configuration Word" on AM18xx based boards,
define CONFIG_SYS_DV_NOR_BOOT_CFG.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:59 +02:00
Heiko Schocher
a293181819 arm, davinci: add ddr2 definition
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:59 +02:00
Heiko Schocher
198a7fc253 arm, davinci, am1808, gpio: add missing defines for bank 8
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
e6862997bd arm, davinci: add some missing defines in hardware.h
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
b841c01d6a arm, davinci: add SYSCFG1 base and register struct
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
725c2935f6 arm, davinci: add RTC base addr
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
bf569ac8d9 arm, davinci: add internal WDT support for AM1808 cpus
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
fbabac79d0 arm, davinci: add missing timer baseaddresses for !DA8xx cpu
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
de23e7225b arm, davinci: move davinci_timer in header file
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:58 +02:00
Heiko Schocher
4f3c42aca4 net, davinci_emac: add KSZ8864 switch
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:56 +02:00
Sanjeev Premi
939e722276 omap3: Fix compile warning
Building without option CONFIG_DISPLAY_CPUINFO leads to
this warning:
sys_info.c:50:14: warning: 'rev_s_37xx' defined but not used

Signed-off-by: Sanjeev Premi <premi@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:55 +02:00
Balaji T K
14fa2dd00f mmc: omap: config VMMC, MMC1_PBIAS
Config VMMC voltage to 3V for MMC/SD card slot
and PBIAS settings needed for OMAP4
Fixes MMC/SD detection on boot from eMMC.

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:55 +02:00
Sandeep Paulraj
d6cac9c83d devkit8000: Fix build break
Found a build erros when i ran MAKEALL.
So fix it.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:55 +02:00
Simon Schwarz
9ea5c6efd8 omap-common: reorganize spl.c
split-up spl.c into spl.c, spl_mmc.c and spl_nand.c. This avoids problems
with missing defines if a board does not use mmc or nand. This includes
adding spl_ prefix to some functions which are now public. spl_image_t is now
a public type. Added some of the common functions to omap-common.h

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:55 +02:00
Simon Schwarz
409ef1bcfb omap3: implement boot parameter saving
Implements the saving of boot params passed by OMAP3 ROM code.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:55 +02:00
Simon Schwarz
78ce977967 omap3: new SPL structure support
Support for the new spl structure. Using the interface defined by Aneesh V for
OMAP4

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:54 +02:00
Simon Schwarz
bb085b87e5 omap-common: add nand spl support
Add NAND support for the new SPL structure.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:54 +02:00
Simon Schwarz
b88e42560b omap3: Configure RAM bank 0 if in SPL
OMAP3 relied on the memory config done by X-loader or Configuration Header. This
has to be reworked for the implementation of a SPL. This patch configures RAM
bank 0 if CONFIG_SPL_BUILD is set. Settings for Micron-RAM used by devkit8000
are added to mem.h

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:54 +02:00
Simon Schwarz
63ffcfcbd0 omap-common/omap4: relocate early UART clock setup
Moves the early UART clock setup setup_clocks_for_console() from
preloader_console_init() to s_init() of OMAP4.

This is done to prepare for OMAP3 integration.

This patch was posted seperatly to the mailinglist but I decidet - since it is
a prereqesit for this patch to add it. Former port to ML:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/104395

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:54 +02:00
Philip Balister
5213d24d7b OMAP3: Overo: Update GPMC timing for ethernet chip
The existing timing does not quite meet the minimum requirements
in the LAN9221 datasheet. The timing in this patch solves problems
noticed on some parts. The patch also combines the CS configuration
for the overo and igep0020 boards per request.

Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30 22:00:53 +02:00
Ajay Bhargav
aa0ecfeb9d Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-09-30 22:00:53 +02:00
Ajay Bhargav
79788bb19a net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2011-09-30 22:00:53 +02:00
Ajay Bhargav
3cf97f4543 gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-09-30 22:00:53 +02:00
York Sun
d29d17d7ba powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
Unified DDR driver is maintained for better performance, robustness and bug
fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of
overall improvement. It requires changes for board files to customize
platform-dependent parameters.

To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx
in the header file. No more boards will be accepted without such definition.

Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1
and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
4e57382faa powerpc/mpc8xxx: Add DDR2 to unified DDR driver
DDR2 has different ODT table and values. Adding table according to Samsung
application note.

Fix additive latency calculation to avoid interger underflow.

Also converted typedef dynamic_odt_t to struct dynamic_odt.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
905acde21a powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
Reduce the calculation error to 1ps.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
639f330f5f powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
The two slots on the same controller have different addresses.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
cae7c1b56b powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
cda1de21de powerpc/mpc8xxx: Move DDR RCW overriding to common code
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
2bba85f412 powerpc/mpc8xxx: Extend CWL table
Extend CAS write Latency (CWL) table to comply with DDR3 spec

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
a598643267 powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
The MPC8536 seems to use only 3 bits for the major revision field in the
SVR rather than the 4 bits used by all other processors.  The most
significant bit is used as a mfg code on MPC8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Roy Zang
fe1a1da038 powerpc/85xx: Add networking support to P1023RDS
The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII.  The second can only do SGMII & RGMII.

We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
c916d7c914 powerpc/85xx: Add support for FMan ethernet in Independent mode
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration
architecture) is the ethernet contoller block.  Normally it is utilized
via Queue Manager (Qman) and Buffer Manager (Bman).  However for boot
usage the FMan supports a mode similar to QE or CPM ethernet collers
called Independent mode.

Additionally the FMan block supports multiple 1g and 10g interfaces as a
single entity in the system rather than each controller being managed
uniquely.  This means we have to initialize all of Fman regardless of
the number of interfaces we utilize.

Different SoCs support different combinations of the number of FMan as
well as the number of 1g & 10g interfaces support per Fman.

We add support for the following SoCs:
 * P1023 - 1 Fman, 2x1g
 * P4080 - 2 Fman, each Fman has 4x1g and 1x10g
 * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Dai Haruki <dai.haruki@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Timur Tabi
fbb9ecf749 powerpc/mp: add support for discontiguous cores
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more.  We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
f117c0f073 fdt: Rename fdt_create_phandle to fdt_set_phandle
The old fdt_create_phandle didn't actually create a phandle it just
set one.  We'll introduce a new helper that actually does creation.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-09-29 19:01:05 -05:00
Kumar Gala
e2d0f255cf powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
Add ifdef protection around fman specific code related to device tree
clock setup.  If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
bc6bbd6be8 fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.

Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.

Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
fb855f43a1 powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.

Impact:
Boot from IFC may not be successful if IFC_CS3 is used.

Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
42aee64bd9 fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size

Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data

Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
e8e6197ab2 powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.

Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Dipen Dudhat
52f90dad60 nand: Freescale Integrated Flash Controller NAND support
Add NAND support (including spl) on IFC, such as is found on the p1010.

Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC.  UBI should
work, as it does not use OOB for anything but ECC.

When hardware ECC is not enabled in CSOR, software ECC is now used.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-09-29 19:01:04 -05:00
Timur Tabi
6ca88b0958 powerpc/85xx: relocate CCSR before creating the initial RAM area
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) structure.  This is
called the initial RAM area, or initram.  The L1 cache is locked and the TLBs
point to a non-existent address (so that there's no chance it will overlap
main memory or any device).  The L1 cache is also configured not to write
out to memory or the L2 cache, so everything stays in the L1 cache.

One of the things we might do while running out of initram is relocate CCSR.
On reset, CCSR is typically located at some high 32-bit address, like
0xfe000000, and this may not be the best place for CCSR.  For example, on
36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit
memory space.

On some future Freescale SOCs, the L1 cache will be forced to write to the
backing store, so we can no longer have the TLBs point to non-existent address.
Instead, we will point the TLBs to an unused area in CCSR.  In order for this
technique to work, CCSR needs to be relocated before the initram memory is
enabled.

Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs
we create now for relocating CCSR are deleted after the relocation is finished.
cpu_init_early_f() will still need to create a TLB for CCSR (at the new
location) for normal U-Boot purposes.  This is done to keep the impact to
existing U-Boot code minimal and to better isolate the CCSR relocation code.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Timur Tabi
e46fedfeb2 powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.

CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file.  Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.

CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.

Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot).  All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Kumar Gala
b6c3722dfa powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:03 -05:00
Ramneek Mehresh
1b719e6654 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
Add UTMI and ULPI PHY support for USB controller on qoriq series of
processors with internal UTMI PHY implemented, for example P1010/P1014
 - Use both getenv() and hwconfig to get USB phy type till getenv()
   is depricated
 - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc
   has internal UTMI phy

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:03 -05:00
Mike Frysinger
90a75b050b Blackfin: uart: implement loop callback for post
This allows the Blackfin UART driver to be tested via post.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29 16:38:05 -04:00
Mike Frysinger
2151374fa6 Blackfin: post: generalize led/button tests with GPIOs
Make it easy for any Blackfin board to enable led/push button tests.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29 16:38:05 -04:00
Mike Frysinger
4257ea4efd Blackfin: post: drop custom test list
The few tests that are Blackfin-specific have been migrated to common
code or been rewritten with the existing "bsp-specific" defines.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29 16:38:05 -04:00
Stefan Roese
226502e01b ppc4xx: Flush dcache after DDR2 autocalibration with caches on
Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).

Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-19 11:51:21 +02:00
Weirich, Bernhard
25fb02abdf Fix incorrect array size of phy settings for 405EX
Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since
405EX has 2 ethernet interfaces.

Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net>
Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-19 11:51:21 +02:00
Jason Kridner
2d3be7c456 led: remove camel casing of led identifiers globally
Result of running the following command to address Wolfgang's
comment about camel case:

for file in `find . | grep '\.[chS]$'`; do perl -i -pe
's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done

Discussion:
http://patchwork.ozlabs.org/patch/84988/

Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:30:52 +02:00
Aneesh V
4ecfcfaa9e omap4: IO settings
Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:16 +02:00
Aneesh V
025bc4254b omap4: make SDRAM init work for ES1.0 silicon
SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Sanjeev Premi
3b690ebbbf omap: gpio: generic changes after changing API
This patch contains the generic changes required after
change to generic API in the previous patch.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Sanjeev Premi
81bdc155c7 omap: gpio: Use generic API
Convert all OMAP specific functions to use the common API
definitions in include/asm/gpio.h. In the process, made
few additional changes:
 - Use -EINVAL consistently. -1 was used in many places.
 - Removed one-liner static functions that were used only
   once. Replaced the content as necessary.
 - Combines implementation of functions omap_get_gpio_dataout()
   and omap_get_gpio_datain(). To do so, new static function
   _get_gpio_direction() was added.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Howard D. Gray
32b58ce736 ARMV7: OMAP3: Add 37xx ESx revision numbers.
OMAP3: Add 37xx ESx revision numbers.

Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Signed-off-by: Howard D. Gray <howard.gray@matrix-vision.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12 17:40:48 +02:00
Joel A Fernandes
569919d8e2 OMAP: Add function to get state of a GPIO output
Read directly from OMAP_GPIO_DATAOUT to get the output state of the GPIO pin

Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12 17:40:48 +02:00
Wolfgang Denk
04e5ae7931 Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-11 21:24:09 +02:00
Wolfgang Denk
3aa7782ac4 tegra2: fix warning: "assert" redefined
Commit 21726a7 "Add assert() for debug assertions" caused build
warnings for all tegra2 based boards:

clock.c:36:1: warning: "assert" redefined
In file included from clock.c:29:
include/common.h:144:1: warning: this is the location of the previous definition

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2011-09-10 16:17:25 +02:00
Greg Ungerer
3a52cfa5cc KS8695: move TIMER_ definitions before code use
Move the TIMER_ definitions before they are used in KS8695 timer.c code.
Fixes:

timer.c: In function ‘timer_init’:
timer.c:37: error: ‘TIMER_COUNT’ undeclared (first use in this function)
timer.c:37: error: (Each undeclared identifier is reported only once
timer.c:37: error: for each function it appears in.)
timer.c:38: error: ‘TIMER_PULSE’ undeclared (first use in this function)

Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
2011-09-10 00:12:13 +02:00
Marek Vasut
b793bb92a2 PXA: FIX: Deep-sleep return address in stored in PSPR
FIX for a typo-bug: The address is stored in PSPR, not PSSR.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-09-07 23:51:37 +02:00
Stefano Babic
67f463b06d MX31: fix missing mxc_get_clk() call
Add missing case to be used in common MXC code.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-09-07 22:11:23 +02:00
Wolfgang Denk
6636eb97e4 omap24xx: fix 'reset_timer_masked' declaration error
Commit 17659d7 "Timer: Remove reset_timer_masked()" introduced a
static declaration for reset_timer_masked() which causes build errors:

timer.c:45: error: static declaration of 'reset_timer_masked' follows non-static declaration
include/asm/u-boot-arm.h:70: error: previous declaration of 'reset_timer_masked' was here

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Graeme Russ <graeme.russ@gmail.com>
Cc: Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-07 22:03:06 +02:00
Wolfgang Denk
c1f8750f9f ARM: remove broken "impa7" board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marius Gröger <mag@sysgo.de>
2011-09-07 21:46:40 +02:00
Wolfgang Denk
c8f63b415f ARM: remove broken "ep7312" board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marius Gröger <mag@sysgo.de>
2011-09-07 21:46:39 +02:00
Stefano Babic
a4814a69d3 Makefile : fix generation of cpu related asm-offsets.h
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
2011-09-07 21:41:27 +02:00
Diana CRACIUN
99ffccbd3e Flush cache after the OS image is loaded into the memory.
Since we are loading an executable image into memory we need flush it
out of the cache to possible maintain coherence on CPUs with split
instruction and data caches.  We do this for other executable image
loading command.

On PowerPC once we do this we no longer need to explicitly flush the
dcache on multi-core systems in the BOOTM_STATE_OS_PREP phase.  We now
treat the BOOTM_STATE_OS_PREP as a no-op to maintain backwards
compatibility with the bootm subcommand.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-05 16:07:44 +02:00
Wolfgang Denk
684cad5717 Merge branch 'master' of git://git.denx.de/u-boot-coldfire
* 'master' of git://git.denx.de/u-boot-coldfire:
  ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage
  ColdFire:Add mb for 5253 dram initialization
  ColdFire:Define the DM9000 byteswap for M5253 board.
  ColdFire:Update the env settings for several boards.
  ColdFire:disable the NFS define for 52277 board.
  ColdFire:Update the timer_init since it was unified.
  ColdFire: Cleanup for partial linking and --gc-sections
  ColdFire: Update compile flags for each CPUs
  ColdFire:Fix the configuration broken for some boards.
2011-09-04 22:53:04 +02:00
Wolfgang Denk
6dfbf49c6d Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (145 commits)
  beagleboard: enable HUB power on all variants of the BeagleBoard
  dm3730: enable dpll5
  ehci-hcd: Allow cleanups to happen gracefully on a timeout.
  OMAP3: Add DSS driver for OMAP3
  led: Remove state-saving of led for toggle functionality and add toggle option to led command
  led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all'
  led: correct off/on locations in structure
  led: added cmd_led to Makefile
  BeagleBoard: fix LED 0/1 in driver
  Corrected LED name match finding avoiding extraneous Usage printouts
  BeagleBoard: config: updated default configuration
  BeagleBoard: config: Enabled multibus support for I2C in configuration
  BeagleBoard: config: add optargs/buddy/camera
  BeagleBoard: config: increase command-line functionality
  BeagleBoard: config: make mtest run
  BeagleBoard: config: enable DSS
  BeagleBoard: config: enable asix driver and dhcp
  BeagleBoard: config: enable networking
  BeagleBoard: config: decrease bootdelay to 2 seconds
  BeagleBoard: config: use uImage.beagle for tftp
  BeagleBoard: config: hardcode MAC for onboard SMSC
  BeagleBoard: config: load kernel from MMC ext, not FAT
  BeagleBoard: Configure DVI/S-video
  BeagleBoard: Added userbutton command
  BeagleBoard: turn off clocks in ehci_stop
  USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor
  beagleboard: add support for xM revision C
  beagle: pass expansionboard name in bootargs
  OMAP: Remove omapfb.debug=y from Beagle and Overo env settings
  OMAP3 Beagle Pin Mux initialization glitch fix
  da850: modifications for Logic PD Rev.3 AM18xx EVM
  da850: fix the channel number for EMAC teardown init
  da850: add support for Spectrum Digital AM18xx EVM
  da850: add support to wake up DSP during board init
  da850: modify the U-Boot prompt string
  da850: add NOR boot mode support
  da8xx: add support for multiple PLL controllers
  da850: indicate cache usage disable in config file
  dm365: modify boot prompt from dm365 to dm36x
  dm365: disable cache usage due to coherency issues
  dm6446: disable cache usage due to coherency issues
  OMAP3: Remove legacy mmc driver
  devkit8000: Use generic MMC driver
  TI OMAP3 SDP3430: Use generic MMC driver
  AM3517 CraneBoard: Use generic MMC driver
  OMAP3: pandora: Use generic MMC driver
  OMAP3: Zoom2: Use generic MMC driver
  OMAP3: Zoom1: Use generic MMC driver
  OMAP3: DIG297: Use generic MMC driver
  OMAP3: CM-T35: Use generic MMC driver
  am3517evm: Use generic MMC driver
  omap3evm: Use generic MMC driver
  omap3:clock: check cpu_family before enabling clks for IVA & CAM
  omap3:clock: configure GFX clock to 200MHz for AM/DM37x
  OMAP3/4: Increase console I/O buffer size
  PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE
  PXA: Fix CSB226, fix monitor length
  PXA: Fix Lubbock, remove redundant parenthesis
  armv7: cache: remove flush on un-aligned invalidate
  armv7: stronger barrier for cache-maintenance operations
  omap: enable caches at system start-up
  arm: do not force d-cache enable on all boards
  ORIGEN: Add MMC SPL support
  ARMV7: Add support for Samsung ORIGEN board
  i2c:gpio:s5p: Enable I2C GPIO on the GONI target
  i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
  Tegra2: Use clock and pinmux functions to simplify code
  Tegra2: Add additional pin multiplexing features
  Tegra2: Add more clock support
  Tegra2: Add microsecond timer function
  ARM: remove broken "at91rm9200dk" board
  ARM: remove broken "m501sk" board
  ARM: remove broken "kb9202" board
  ARM: remove broken "csb637" board
  ARM: remove broken "cmc_pu2" board
  ARM: remove broken "at91cap9adk" board
  ARM: remove broken "voiceblue" board
  ARM: remove broken "smdk2400" board
  ARM: remove broken "sbc2410x" board
  ARM: remove broken "netstar" board
  ARM: remove broken "mx1fs2" board
  ARM: remove broken "lpd7a40x" boards
  ARM: remove broken "edb93xx" boards
  ARM: remove broken "B2" board
  ARM: remove broken "armadillo" board
  ARM: remove broken "assabet" board
  ARM: versatile: drop warnings
  IMX: scb9328: drop warnings
  MX31: imx31_litekit: make use of GPIO framework
  MX31: mx31ads: make use of GPIO framework
  MX5: mx51evk: make use of GPIO framework
  MX35: mx35pdk: make use of GPIO framework
  MX5: mx53loco: make use of GPIO framework
  MX5: mx53evk: make use of GPIO framework
  MX5: vision2: make use of GPIO framework
  MX5: mx53smd: make use of GPIO framework
  MX5: mx53ard: make use of GPIO framework
  MX25: zmx25: make use of GPIO framework
  MX5: efikamx: make use of GPIO framework
  MX31: QONG: make use of GPIO framework
  MX35: make use of GPIO framework for MX35 processor
  MX5: make use of GPIO framework for MX5 processor
  MX31: make use of GPIO framework for MX31 processor
  MX25: make use of GPIO framework for MX25 processor
  IMX: uniform GPIO interface using GPIO framework
  MX: MX35 / MX5: uniform clock command with powerpc
  MX35: MX35PDK: support additional RAM on CSD1
  mx53: ddr3: Update DD3 initialization
  ARM: MX51: PLL errata workaround
  ARM: versatilepb : drop warnings due to double definitions
  omap4: increase SRAM budget to fix build error
  omap4: fix build warning due to signed unsigned comparison
  mkimage: Fix 'Unknown OMAP image type - 5'
  omap: fix gpio related build breaks
  gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal)
  SMDKV310: MMC SPL: Remove unwanted dummy functions
  SMDKV310: Fix undefined reference error
  SMDKV310: Fix build error for smdkv310 board
  gpio:samsung s5p_ suffix add for GPIO functions
  mmc: S5P: Support DMA restarts at buffer boundaries
  SMDKV310: Fix host compilation of mkv310_image
  arm: fix bd pointer dereference prior initialization
  arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize
  mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
  MX31: removed warnings due to clock.h
  integrator: convert to new build system
  integratorcp: make the board compile
  integratorap: remove hardcoded 32MB memory cmdline
  ...
2011-09-04 21:12:18 +02:00
Jason Jin
3f8ce93956 ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage
Remove the additional linker options for CONFIG_STANDALONE_LOAD_ADDR

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Jason Jin
6752da6b26 ColdFire:Add mb for 5253 dram initialization
The dram initialization sequence should be in order.
This patch add mb for the dram intialization code to make
sure the compiler do not disorder the code.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Jason Jin
444ddfc751 ColdFire:Update the timer_init since it was unified.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Jason Jin
6c0bf27d74 ColdFire: Cleanup for partial linking and --gc-sections
Introduce the --gc-sections for ColdFire platform and clean up the
corresponding lds file.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Jason Jin
45263ec4c0 ColdFire: Update compile flags for each CPUs
Remove compiler version check for gcc 4.1 in config.mk.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Eric Benard
31c8598425 dm3730: enable dpll5
which is used to provide 120MHz to USB EHCI
This allows EHCI to work on BeagleBoard XM

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:22 +02:00
Syed Mohammed Khasim
de701d1183 OMAP3: Add DSS driver for OMAP3
* Supports dynamic panel configuration
* Supports dynamic tv standard selection
* Adds support for DSS register access through generic APIs
* Incorporated DSS register access using structures.
* DSS makefile update

Previous discussions are here:
http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:22 +02:00
Nagabhushana Netagunte
0f3d6b06ea da850: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:19 +02:00
Nagabhushana Netagunte
cf2c24e399 da850: add support to wake up DSP during board init
add support for DSP wake-up by default on DA850/OMAP-L138
during board initialization. Enable hwconfig environment and added
extra env setting through CONFIG_EXTRA_ENV_SETTINGS.
To prevent DSP from being woken up,set the environment variable as,
set hwconfig "dsp:wake=no"

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:19 +02:00
Sudhakar Rajashekhara
b7e6843f97 da8xx: add support for multiple PLL controllers
Modify clk_get() function in cpu file to work for
multiple PLL controllers.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:18 +02:00
Vaibhav Hiremath
7dd5a5be2f omap3:clock: check cpu_family before enabling clks for IVA & CAM
In case of AM3517 and AM3505 (which is OMAP3 varients), IVA2 and
ISP-CAMERA modules have been removed. So add check for cpu_family before
enabling clocks for these modules, else this impacts subsequent
power consumption and system suspend/resume functionality.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:17 +02:00
Vaibhav Hiremath
f4dac3e16c omap3:clock: configure GFX clock to 200MHz for AM/DM37x
AM/DM37x is another OMAP3 variant, where the GFX clock has been
boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change.

HW Errata: Due to dependency of TV out clock of 54MHz, it is not
possible to configure GFX to 192MHz. So as per HW errats, the
recommended GFX clock is 200MHz (=CORE_CLK/2).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-04 11:36:17 +02:00
Aneesh V
cabe2878a8 armv7: cache: remove flush on un-aligned invalidate
Remove the flush of boundary cache-lines done as part
of invalidate on a non cache-line boundary aligned
buffer

Also, print a warning when this situation is recognized.

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-09-04 11:36:16 +02:00
Aneesh V
882f80b993 armv7: stronger barrier for cache-maintenance operations
set-way operations need a DSB after them to ensure the
operation is complete. DMB may not be enough. Use DSB
after all operations instead of DMB.

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-09-04 11:36:16 +02:00
Aneesh V
13d4f9bd74 omap: enable caches at system start-up
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-09-04 11:36:16 +02:00
Aneesh V
cba4b1809f arm: do not force d-cache enable on all boards
c2dd0d4554 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-09-04 11:36:16 +02:00
Łukasz Majewski
9f15bc0c1c i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
This patch adds support for software I2C for GONI and Universal C210 reference targets.
It adds support for access to GPIOs by number, not as it is present,
by bank and offset.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
2011-09-04 11:36:15 +02:00
Simon Glass
d07dc4993d Tegra2: Use clock and pinmux functions to simplify code
Signed-off-by: Simon Glass <sjg@chromium.org>
2011-09-04 11:36:15 +02:00