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EXYNOS5: support display system register control

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This patch supports display block system regisger control.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Donghwa Lee 2012-07-02 01:15:53 +00:00 committed by Albert ARIBAUD
parent 2c5cd25cf9
commit 46524beb4a
1 changed files with 18 additions and 0 deletions
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18
arch/arm/cpu/armv7/exynos/system.c
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@ -62,8 +62,26 @@ static void exynos4_set_system_display(void)
writel(cfg, &sysreg->display_ctrl);
}
static void exynos5_set_system_display(void)
{
struct exynos5_sysreg *sysreg =
(struct exynos5_sysreg *)samsung_get_base_sysreg();
unsigned int cfg = 0;
/*
* system register path set
* 0: MIE/MDNIE
* 1: FIMD Bypass
*/
cfg = readl(&sysreg->disp1blk_cfg);
cfg |= (1 << 15);
writel(cfg, &sysreg->disp1blk_cfg);
}
void set_system_display_ctrl(void)
{
if (cpu_is_exynos4())
exynos4_set_system_display();
else
exynos5_set_system_display();
}