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ARM: OMAP4+: Cleanup the clocks layer

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Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
SRICHARAN R 2013-02-04 04:22:01 +00:00 • committed by Tom Rini
parent 01b753ff7b
commit ee9447bfe3
10 changed files with 869 additions and 895 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

89
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -47,6 +47,16 @@
#define puts(s)
#endif
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
13000000, /* 13 MHz */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
};
static inline u32 __get_sys_clk_index(void)
{
u32 ind;
@ -76,6 +86,29 @@ u32 get_sys_clk_freq(void)
return sys_clk_array[index];
}
void setup_post_dividers(u32 const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->m4_h11 >= 0)
writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
if (params->m5_h12 >= 0)
writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
if (params->m6_h13 >= 0)
writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
if (params->m7_h14 >= 0)
writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
if (params->h22 >= 0)
writel(params->h22, &dpll_regs->cm_div_h22_dpll);
if (params->h23 >= 0)
writel(params->h23, &dpll_regs->cm_div_h23_dpll);
}
static inline void do_bypass_dpll(u32 const base)
{
struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
@ -124,6 +157,46 @@ inline u32 check_for_lock(u32 const base)
return lock;
}
const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->mpu[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->core[sysclk_ind];
}
const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->per[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->iva[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->usb[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->abe[sysclk_ind];
#else
return dpll_data->abe;
#endif
}
static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
@ -184,7 +257,7 @@ u32 omap_ddr_clk(void)
omap_rev = omap_revision();
sys_clk_khz = get_sys_clk_freq() / 1000;
core_dpll_params = get_core_dpll_params();
core_dpll_params = get_core_dpll_params(*dplls_data);
debug("sys_clk %d\n ", sys_clk_khz * 1000);
@ -251,7 +324,7 @@ void configure_mpu_dpll(void)
setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
params = get_mpu_dpll_params();
params = get_mpu_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
@ -272,7 +345,7 @@ static void setup_usb_dpll(void)
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
params = get_usb_dpll_params();
params = get_usb_dpll_params(*dplls_data);
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
@ -294,7 +367,7 @@ static void setup_dplls(void)
debug("setup_dplls\n");
/* CORE dpll */
params = get_core_dpll_params(); /* default - safest */
params = get_core_dpll_params(*dplls_data); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
@ -314,7 +387,7 @@ static void setup_dplls(void)
debug("Core DPLL configured\n");
/* lock PER dpll */
params = get_per_dpll_params();
params = get_per_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
@ -337,11 +410,11 @@ static void setup_non_essential_dplls(void)
clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
params = get_iva_dpll_params();
params = get_iva_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
/* Configure ABE dpll */
params = get_abe_dpll_params();
params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
@ -459,7 +532,7 @@ void freq_update_core(void)
const struct dpll_params *core_dpll_params;
u32 omap_rev = omap_revision();
core_dpll_params = get_core_dpll_params();
core_dpll_params = get_core_dpll_params(*dplls_data);
/* Put EMIF clock domain in sw wakeup mode */
enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);

393
arch/arm/cpu/armv7/omap4/clocks.c
View file

@ -46,221 +46,6 @@
#define puts(s)
#endif /* !CONFIG_SPL_BUILD */
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
13000000, /* 13 MHz */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
};
/*
* The M & N values in the following tables are created using the
* following tool:
* tools/omap/clocks_get_m_n.c
* Please use this tool for creating the table for any new frequency.
*/
/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
{175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
{50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
{619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
{800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
{125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
{127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
{762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
{635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
{254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
{496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
{200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
{800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
{619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
{800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
{125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
{64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
{768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
{320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
{256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
{20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
{291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
void setup_post_dividers(u32 const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->m4 >= 0)
writel(params->m4, &dpll_regs->cm_div_m4_dpll);
if (params->m5 >= 0)
writel(params->m5, &dpll_regs->cm_div_m5_dpll);
if (params->m6 >= 0)
writel(params->m6, &dpll_regs->cm_div_m6_dpll);
if (params->m7 >= 0)
writel(params->m7, &dpll_regs->cm_div_m7_dpll);
}
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
const struct dpll_params *get_mpu_dpll_params(void)
{
u32 omap_rev, sysclk_ind;
omap_rev = omap_revision();
sysclk_ind = get_sys_clk_index();
if (omap_rev == OMAP4430_ES1_0)
return &mpu_dpll_params_1200mhz[sysclk_ind];
else if (omap_rev < OMAP4460_ES1_0)
return &mpu_dpll_params_1600mhz[sysclk_ind];
else
return &mpu_dpll_params_1400mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
switch (omap_revision()) {
case OMAP4430_ES1_0:
return &core_dpll_params_es1_1524mhz[sysclk_ind];
case OMAP4430_ES2_0:
case OMAP4430_SILICON_ID_INVALID:
/* safest */
return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
default:
return &core_dpll_params_1600mhz[sysclk_ind];
}
}
const struct dpll_params *get_per_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &per_dpll_params_1536mhz[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &iva_dpll_params_1862mhz[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &usb_dpll_params_1920mhz[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(void)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
return &abe_dpll_params_32k_196608khz;
#endif
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
@ -336,181 +121,3 @@ u32 get_offset_code(u32 offset)
/* The code starts at 1 not 0 */
return ++offset_code;
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_2_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
/* Enable optional 48M functional clock for USB PHY */
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbotg_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_clksel_usb_60mhz,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 const clk_domains_non_essential[] = {
(*prcm)->cm_mpu_m3_clkstctrl,
(*prcm)->cm_ivahd_clkstctrl,
(*prcm)->cm_dsp_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sgx_clkstctrl,
(*prcm)->cm1_abe_clkstctrl,
(*prcm)->cm_c2c_clkstctrl,
(*prcm)->cm_cam_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sdma_clkstctrl,
0
};
u32 const clk_modules_hw_auto_non_essential[] = {
(*prcm)->cm_l3instr_l3_3_clkctrl,
(*prcm)->cm_l3instr_l3_instr_clkctrl,
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
(*prcm)->cm_l3init_hsi_clkctrl,
0
};
u32 const clk_modules_explicit_en_non_essential[] = {
(*prcm)->cm1_abe_aess_clkctrl,
(*prcm)->cm1_abe_pdm_clkctrl,
(*prcm)->cm1_abe_dmic_clkctrl,
(*prcm)->cm1_abe_mcasp_clkctrl,
(*prcm)->cm1_abe_mcbsp1_clkctrl,
(*prcm)->cm1_abe_mcbsp2_clkctrl,
(*prcm)->cm1_abe_mcbsp3_clkctrl,
(*prcm)->cm1_abe_slimbus_clkctrl,
(*prcm)->cm1_abe_timer5_clkctrl,
(*prcm)->cm1_abe_timer6_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
(*prcm)->cm1_abe_wdt3_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
(*prcm)->cm_l4per_gptimer10_clkctrl,
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_hdq1w_clkctrl,
(*prcm)->cm_l4per_mcbsp4_clkctrl,
(*prcm)->cm_l4per_mcspi2_clkctrl,
(*prcm)->cm_l4per_mcspi3_clkctrl,
(*prcm)->cm_l4per_mcspi4_clkctrl,
(*prcm)->cm_l4per_mmcsd3_clkctrl,
(*prcm)->cm_l4per_mmcsd4_clkctrl,
(*prcm)->cm_l4per_mmcsd5_clkctrl,
(*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart2_clkctrl,
(*prcm)->cm_l4per_uart4_clkctrl,
(*prcm)->cm_wkup_keyboard_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_cam_iss_clkctrl,
(*prcm)->cm_cam_fdif_clkctrl,
(*prcm)->cm_dss_dss_clkctrl,
(*prcm)->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

367
arch/arm/cpu/armv7/omap4/hw_data.c
View file

@ -27,12 +27,377 @@
*/
#include <common.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/io.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
/*
* The M & N values in the following tables are created using the
* following tool:
* tools/omap/clocks_get_m_n.c
* Please use this tool for creating the table for any new frequency.
*/
/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
{175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
{50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
{619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
{800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
{125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
{127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
{762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
{635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
{254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
{496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
{200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
{800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
{619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
{800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
{125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
{64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */
{768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */
{320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */
{256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */
{20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */
{931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */
{665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */
{291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
struct dplls omap4430_dplls_es1 = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_es1_1524mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
};
struct dplls omap4430_dplls = {
.mpu = mpu_dpll_params_1600mhz,
.core = core_dpll_params_es2_1600mhz_ddr200mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
};
struct dplls omap4460_dplls = {
.mpu = mpu_dpll_params_1400mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_2_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
/* Enable optional 48M functional clock for USB PHY */
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbotg_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_clksel_usb_60mhz,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 const clk_domains_non_essential[] = {
(*prcm)->cm_mpu_m3_clkstctrl,
(*prcm)->cm_ivahd_clkstctrl,
(*prcm)->cm_dsp_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sgx_clkstctrl,
(*prcm)->cm1_abe_clkstctrl,
(*prcm)->cm_c2c_clkstctrl,
(*prcm)->cm_cam_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sdma_clkstctrl,
0
};
u32 const clk_modules_hw_auto_non_essential[] = {
(*prcm)->cm_l3instr_l3_3_clkctrl,
(*prcm)->cm_l3instr_l3_instr_clkctrl,
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
(*prcm)->cm_l3init_hsi_clkctrl,
0
};
u32 const clk_modules_explicit_en_non_essential[] = {
(*prcm)->cm1_abe_aess_clkctrl,
(*prcm)->cm1_abe_pdm_clkctrl,
(*prcm)->cm1_abe_dmic_clkctrl,
(*prcm)->cm1_abe_mcasp_clkctrl,
(*prcm)->cm1_abe_mcbsp1_clkctrl,
(*prcm)->cm1_abe_mcbsp2_clkctrl,
(*prcm)->cm1_abe_mcbsp3_clkctrl,
(*prcm)->cm1_abe_slimbus_clkctrl,
(*prcm)->cm1_abe_timer5_clkctrl,
(*prcm)->cm1_abe_timer6_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
(*prcm)->cm1_abe_wdt3_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
(*prcm)->cm_l4per_gptimer10_clkctrl,
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_hdq1w_clkctrl,
(*prcm)->cm_l4per_mcbsp4_clkctrl,
(*prcm)->cm_l4per_mcspi2_clkctrl,
(*prcm)->cm_l4per_mcspi3_clkctrl,
(*prcm)->cm_l4per_mcspi4_clkctrl,
(*prcm)->cm_l4per_mmcsd3_clkctrl,
(*prcm)->cm_l4per_mmcsd4_clkctrl,
(*prcm)->cm_l4per_mmcsd5_clkctrl,
(*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart2_clkctrl,
(*prcm)->cm_l4per_uart4_clkctrl,
(*prcm)->cm_wkup_keyboard_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_cam_iss_clkctrl,
(*prcm)->cm_cam_fdif_clkctrl,
(*prcm)->cm_dss_dss_clkctrl,
(*prcm)->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
void hw_data_init(void)
{
*prcm = &omap4_prcm;
u32 omap_rev = omap_revision();
(*prcm) = &omap4_prcm;
switch (omap_rev) {
case OMAP4430_ES1_0:
*dplls_data = &omap4430_dplls_es1;
break;
case OMAP4430_ES2_0:
case OMAP4430_ES2_1:
case OMAP4430_ES2_2:
case OMAP4430_ES2_3:
*dplls_data = &omap4430_dplls;
break;
case OMAP4460_ES1_0:
case OMAP4460_ES1_1:
*dplls_data = &omap4460_dplls;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}

396
arch/arm/cpu/armv7/omap5/clocks.c
View file

@ -47,210 +47,6 @@
#define puts(s)
#endif
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
0, /* NA */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
0, /* NA */
38400000, /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
void setup_post_dividers(u32 const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->h11 >= 0)
writel(params->h11, &dpll_regs->cm_div_h11_dpll);
if (params->h12 >= 0)
writel(params->h12, &dpll_regs->cm_div_h12_dpll);
if (params->h13 >= 0)
writel(params->h13, &dpll_regs->cm_div_h13_dpll);
if (params->h14 >= 0)
writel(params->h14, &dpll_regs->cm_div_h14_dpll);
if (params->h22 >= 0)
writel(params->h22, &dpll_regs->cm_div_h22_dpll);
if (params->h23 >= 0)
writel(params->h23, &dpll_regs->cm_div_h23_dpll);
}
const struct dpll_params *get_mpu_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &mpu_dpll_params_800mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
/* Configuring the DDR to be at 532mhz */
return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
}
const struct dpll_params *get_per_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &per_dpll_params_768mhz[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &iva_dpll_params_2330mhz[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &usb_dpll_params_1920mhz[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(void)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
return &abe_dpll_params_32k_196608khz;
#endif
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
@ -300,195 +96,3 @@ u32 get_offset_code(u32 volt_offset)
*/
return offset_code + 6;
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_2_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
/* Select 384Mhz for GPU as its the POR for ES1.0 */
setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_HYD_GCLK_MASK);
setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_CORE_GCLK_MASK);
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 const clk_domains_non_essential[] = {
(*prcm)->cm_mpu_m3_clkstctrl,
(*prcm)->cm_ivahd_clkstctrl,
(*prcm)->cm_dsp_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sgx_clkstctrl,
(*prcm)->cm1_abe_clkstctrl,
(*prcm)->cm_c2c_clkstctrl,
(*prcm)->cm_cam_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sdma_clkstctrl,
0
};
u32 const clk_modules_hw_auto_non_essential[] = {
(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
(*prcm)->cm_ivahd_ivahd_clkctrl,
(*prcm)->cm_ivahd_sl2_clkctrl,
(*prcm)->cm_dsp_dsp_clkctrl,
(*prcm)->cm_l3instr_l3_3_clkctrl,
(*prcm)->cm_l3instr_l3_instr_clkctrl,
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
(*prcm)->cm_l3init_hsi_clkctrl,
(*prcm)->cm_l4per_hdq1w_clkctrl,
0
};
u32 const clk_modules_explicit_en_non_essential[] = {
(*prcm)->cm1_abe_aess_clkctrl,
(*prcm)->cm1_abe_pdm_clkctrl,
(*prcm)->cm1_abe_dmic_clkctrl,
(*prcm)->cm1_abe_mcasp_clkctrl,
(*prcm)->cm1_abe_mcbsp1_clkctrl,
(*prcm)->cm1_abe_mcbsp2_clkctrl,
(*prcm)->cm1_abe_mcbsp3_clkctrl,
(*prcm)->cm1_abe_slimbus_clkctrl,
(*prcm)->cm1_abe_timer5_clkctrl,
(*prcm)->cm1_abe_timer6_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
(*prcm)->cm1_abe_wdt3_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
(*prcm)->cm_l4per_gptimer10_clkctrl,
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_mcspi2_clkctrl,
(*prcm)->cm_l4per_mcspi3_clkctrl,
(*prcm)->cm_l4per_mcspi4_clkctrl,
(*prcm)->cm_l4per_mmcsd3_clkctrl,
(*prcm)->cm_l4per_mmcsd4_clkctrl,
(*prcm)->cm_l4per_mmcsd5_clkctrl,
(*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart2_clkctrl,
(*prcm)->cm_l4per_uart4_clkctrl,
(*prcm)->cm_wkup_keyboard_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_cam_iss_clkctrl,
(*prcm)->cm_cam_fdif_clkctrl,
(*prcm)->cm_dss_dss_clkctrl,
(*prcm)->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

355
arch/arm/cpu/armv7/omap5/hw_data.c
View file

@ -27,12 +27,367 @@
*/
#include <common.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/io.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
struct dplls omap5_dplls_es1 = {
.mpu = mpu_dpll_params_800mhz,
.core = core_dpll_params_2128mhz_ddr532,
.per = per_dpll_params_768mhz,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_2_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
/* Select 384Mhz for GPU as its the POR for ES1.0 */
setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_HYD_GCLK_MASK);
setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_CORE_GCLK_MASK);
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 const clk_domains_non_essential[] = {
(*prcm)->cm_mpu_m3_clkstctrl,
(*prcm)->cm_ivahd_clkstctrl,
(*prcm)->cm_dsp_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sgx_clkstctrl,
(*prcm)->cm1_abe_clkstctrl,
(*prcm)->cm_c2c_clkstctrl,
(*prcm)->cm_cam_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sdma_clkstctrl,
0
};
u32 const clk_modules_hw_auto_non_essential[] = {
(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
(*prcm)->cm_ivahd_ivahd_clkctrl,
(*prcm)->cm_ivahd_sl2_clkctrl,
(*prcm)->cm_dsp_dsp_clkctrl,
(*prcm)->cm_l3instr_l3_3_clkctrl,
(*prcm)->cm_l3instr_l3_instr_clkctrl,
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
(*prcm)->cm_l3init_hsi_clkctrl,
(*prcm)->cm_l4per_hdq1w_clkctrl,
0
};
u32 const clk_modules_explicit_en_non_essential[] = {
(*prcm)->cm1_abe_aess_clkctrl,
(*prcm)->cm1_abe_pdm_clkctrl,
(*prcm)->cm1_abe_dmic_clkctrl,
(*prcm)->cm1_abe_mcasp_clkctrl,
(*prcm)->cm1_abe_mcbsp1_clkctrl,
(*prcm)->cm1_abe_mcbsp2_clkctrl,
(*prcm)->cm1_abe_mcbsp3_clkctrl,
(*prcm)->cm1_abe_slimbus_clkctrl,
(*prcm)->cm1_abe_timer5_clkctrl,
(*prcm)->cm1_abe_timer6_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
(*prcm)->cm1_abe_wdt3_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
(*prcm)->cm_l4per_gptimer10_clkctrl,
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_mcspi2_clkctrl,
(*prcm)->cm_l4per_mcspi3_clkctrl,
(*prcm)->cm_l4per_mcspi4_clkctrl,
(*prcm)->cm_l4per_mmcsd3_clkctrl,
(*prcm)->cm_l4per_mmcsd4_clkctrl,
(*prcm)->cm_l4per_mmcsd5_clkctrl,
(*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart2_clkctrl,
(*prcm)->cm_l4per_uart4_clkctrl,
(*prcm)->cm_wkup_keyboard_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_cam_iss_clkctrl,
(*prcm)->cm_cam_fdif_clkctrl,
(*prcm)->cm_dss_dss_clkctrl,
(*prcm)->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
break;
case OMAP5432_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}

45
arch/arm/include/asm/arch-omap4/clocks.h
View file

@ -242,55 +242,10 @@
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
#define NUM_SYS_CLKS 7
struct dpll_regs {
u32 cm_clkmode_dpll;
u32 cm_idlest_dpll;
u32 cm_autoidle_dpll;
u32 cm_clksel_dpll;
u32 cm_div_m2_dpll;
u32 cm_div_m3_dpll;
u32 cm_div_m4_dpll;
u32 cm_div_m5_dpll;
u32 cm_div_m6_dpll;
u32 cm_div_m7_dpll;
};
/* DPLL parameter table */
struct dpll_params {
u32 m;
u32 n;
s8 m2;
s8 m3;
s8 m4;
s8 m5;
s8 m6;
s8 m7;
};
extern const u32 sys_clk_array[8];
void scale_vcores(void);
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
u32 get_offset_code(u32 offset);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
void setup_post_dividers(u32 const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
const struct dpll_params *get_mpu_dpll_params(void);
const struct dpll_params *get_core_dpll_params(void);
const struct dpll_params *get_per_dpll_params(void);
const struct dpll_params *get_iva_dpll_params(void);
const struct dpll_params *get_usb_dpll_params(void);
const struct dpll_params *get_abe_dpll_params(void);
struct omap4_scrm_regs {
u32 revision; /* 0x0000 */

3
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -179,7 +179,8 @@ struct control_lpddr2io_regs {
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
/* ROM code defines */
/* Boot device */

50
arch/arm/include/asm/arch-omap5/clocks.h
View file

@ -234,58 +234,8 @@
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
#define NUM_SYS_CLKS 7
struct dpll_regs {
u32 cm_clkmode_dpll;
u32 cm_idlest_dpll;
u32 cm_autoidle_dpll;
u32 cm_clksel_dpll;
u32 cm_div_m2_dpll;
u32 cm_div_m3_dpll;
u32 cm_div_h11_dpll;
u32 cm_div_h12_dpll;
u32 cm_div_h13_dpll;
u32 cm_div_h14_dpll;
u32 reserved[3];
u32 cm_div_h22_dpll;
u32 cm_div_h23_dpll;
};
/* DPLL parameter table */
struct dpll_params {
u32 m;
u32 n;
s8 m2;
s8 m3;
s8 h11;
s8 h12;
s8 h13;
s8 h14;
s8 h22;
s8 h23;
};
extern const u32 sys_clk_array[8];
void scale_vcores(void);
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
u32 get_offset_code(u32 offset);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
void setup_post_dividers(u32 const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_non_essential_clocks(void);
void enable_basic_uboot_clocks(void);
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
const struct dpll_params *get_mpu_dpll_params(void);
const struct dpll_params *get_core_dpll_params(void);
const struct dpll_params *get_per_dpll_params(void);
const struct dpll_params *get_iva_dpll_params(void);
const struct dpll_params *get_usb_dpll_params(void);
const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP5_H_ */

3
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -272,7 +272,8 @@ struct omap_sys_ctrl_regs {
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF

63
arch/arm/include/asm/omap_common.h
View file

@ -27,6 +27,8 @@
#include <common.h>
#define NUM_SYS_CLKS 7
struct prcm_regs {
/* cm1.ckgen */
u32 cm_clksel_core;
@ -324,11 +326,72 @@ struct prcm_regs {
u32 prm_vc_cfg_channel;
};
struct dpll_params {
u32 m;
u32 n;
s8 m2;
s8 m3;
s8 m4_h11;
s8 m5_h12;
s8 m6_h13;
s8 m7_h14;
s8 h22;
s8 h23;
};
struct dpll_regs {
u32 cm_clkmode_dpll;
u32 cm_idlest_dpll;
u32 cm_autoidle_dpll;
u32 cm_clksel_dpll;
u32 cm_div_m2_dpll;
u32 cm_div_m3_dpll;
u32 cm_div_m4_h11_dpll;
u32 cm_div_m5_h12_dpll;
u32 cm_div_m6_h13_dpll;
u32 cm_div_m7_h14_dpll;
u32 reserved[3];
u32 cm_div_h22_dpll;
u32 cm_div_h23_dpll;
};
struct dplls {
const struct dpll_params *mpu;
const struct dpll_params *core;
const struct dpll_params *per;
const struct dpll_params *abe;
const struct dpll_params *iva;
const struct dpll_params *usb;
};
extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
extern struct prcm_regs const omap4_prcm;
extern struct dplls const **dplls_data;
extern const u32 sys_clk_array[8];
void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
const struct dpll_params *get_core_dpll_params(struct dplls const *);
const struct dpll_params *get_per_dpll_params(struct dplls const *);
const struct dpll_params *get_iva_dpll_params(struct dplls const *);
const struct dpll_params *get_usb_dpll_params(struct dplls const *);
const struct dpll_params *get_abe_dpll_params(struct dplls const *);
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
u32 omap_ddr_clk(void);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
/* Max value for DPLL multiplier M */
#define OMAP_DPLL_MAX_N 127