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powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'
If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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3 changed files with 92 additions and 1 deletions
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@ -607,6 +607,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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/* delete crypto node if not on an E-processor */
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if (!IS_E_PROCESSOR(get_svr()))
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fdt_fixup_crypto_node(blob, 0);
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#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
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else {
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ccsr_sec_t __iomem *sec;
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sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
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fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
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}
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#endif
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fdt_fixup_ethernet(blob);
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@ -297,10 +297,86 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
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fdt_strerror(err));
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}
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#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
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static u8 caam_get_era(void)
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{
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static const struct {
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u16 ip_id;
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u8 maj_rev;
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u8 era;
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} caam_eras[] = {
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{0x0A10, 1, 1},
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{0x0A10, 2, 2},
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{0x0A12, 1, 3},
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{0x0A14, 1, 3},
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{0x0A14, 2, 4},
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{0x0A16, 1, 4},
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{0x0A10, 3, 4},
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{0x0A11, 1, 4},
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{0x0A18, 1, 4},
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{0x0A11, 2, 5},
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{0x0A12, 2, 5},
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{0x0A13, 1, 5},
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{0x0A1C, 1, 5}
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};
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ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
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u32 secvid_ms = in_be32(&sec->secvid_ms);
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u32 ccbvid = in_be32(&sec->ccbvid);
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u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
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SEC_SECVID_MS_IPID_SHIFT;
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u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
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SEC_SECVID_MS_MAJ_REV_SHIFT;
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u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
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int i;
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if (era) /* This is '0' prior to CAAM ERA-6 */
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return era;
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for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
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if (caam_eras[i].ip_id == ip_id &&
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caam_eras[i].maj_rev == maj_rev)
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return caam_eras[i].era;
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return 0;
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}
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static void fdt_fixup_crypto_era(void *blob, u32 era)
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{
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int err;
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int crypto_node;
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crypto_node = fdt_path_offset(blob, "crypto");
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if (crypto_node < 0) {
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printf("WARNING: Missing crypto node\n");
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return;
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}
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err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
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sizeof(era));
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if (err < 0) {
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printf("ERROR: could not set fsl,sec-era property: %s\n",
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fdt_strerror(err));
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}
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}
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void fdt_fixup_crypto_node(void *blob, int sec_rev)
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{
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if (!sec_rev)
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u8 era;
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if (!sec_rev) {
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fdt_del_node_and_alias(blob, "crypto");
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return;
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}
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/* Add SEC ERA information in compatible */
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era = caam_get_era();
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if (era) {
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fdt_fixup_crypto_era(blob, era);
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} else {
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printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
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sec_rev);
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}
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}
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#endif
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@ -2748,6 +2748,12 @@ typedef struct ccsr_sec {
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#define SEC_CHANUM_MS_JRNUM_SHIFT 28
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#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
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#define SEC_CHANUM_MS_DECONUM_SHIFT 24
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#define SEC_SECVID_MS_IPID_MASK 0xffff0000
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#define SEC_SECVID_MS_IPID_SHIFT 16
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#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
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#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
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#define SEC_CCBVID_ERA_MASK 0xff000000
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#define SEC_CCBVID_ERA_SHIFT 24
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#endif
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typedef struct ccsr_qman {
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@ -2983,6 +2989,7 @@ struct ccsr_pman {
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#endif
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#define CONFIG_SYS_MDIO1_OFFSET 0x24000
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#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
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#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
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#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
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#define CONFIG_SYS_SNVS_OFFSET 0xE6000
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