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https://github.com/AsahiLinux/u-boot
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Tegra2: Use clock and pinmux functions to simplify code
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
858bd095e1
commit
d07dc4993d
3 changed files with 20 additions and 76 deletions
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@ -40,23 +40,21 @@ void init_pllx(void)
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u32 reg;
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/* If PLLX is already enabled, just return */
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reg = readl(&pll->pll_base);
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if (reg & PLL_ENABLE)
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
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return;
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/* Set PLLX_MISC */
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reg = CPCON; /* CPCON[11:8] = 0001 */
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writel(reg, &pll->pll_misc);
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writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
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/* Use 12MHz clock here */
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reg = (PLL_BYPASS | PLL_DIVM_VALUE);
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reg |= (1000 << 8); /* DIVN = 0x3E8 */
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reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
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reg |= 1000 << PLL_DIVN_SHIFT;
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writel(reg, &pll->pll_base);
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reg |= PLL_ENABLE;
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reg |= PLL_ENABLE_MASK;
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writel(reg, &pll->pll_base);
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reg &= ~PLL_BYPASS;
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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}
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@ -90,16 +88,11 @@ static void enable_cpu_clock(int enable)
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* always stop the clock to CPU 1.
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*/
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clk = readl(&clkrst->crc_clk_cpu_cmplx);
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clk |= CPU1_CLK_STP;
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if (enable) {
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/* Unstop the CPU clock */
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clk &= ~CPU0_CLK_STP;
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} else {
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/* Stop the CPU clock */
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clk |= CPU0_CLK_STP;
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}
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clk |= 1 << CPU1_CLK_STP_SHIFT;
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/* Stop/Unstop the CPU clock */
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clk &= ~CPU0_CLK_STP_MASK;
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clk |= !enable << CPU0_CLK_STP_SHIFT;
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writel(clk, &clkrst->crc_clk_cpu_cmplx);
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clock_enable(PERIPH_ID_CPU);
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@ -177,9 +170,6 @@ static void enable_cpu_power_rail(void)
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static void reset_A9_cpu(int reset)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 cpu;
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset
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* or take it out of reset, every processor in the CPU complex
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@ -188,19 +178,10 @@ static void reset_A9_cpu(int reset)
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* are multiple processors in the CPU complex.
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*/
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/* Hold CPU 1 in reset */
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cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
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writel(cpu, &clkrst->crc_cpu_cmplx_set);
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if (reset) {
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/* Now place CPU0 into reset */
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cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
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writel(cpu, &clkrst->crc_cpu_cmplx_set);
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} else {
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/* Take CPU0 out of reset */
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cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
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writel(cpu, &clkrst->crc_cpu_cmplx_clr);
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}
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/* Hold CPU 1 in reset, and CPU 0 if asked */
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reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
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reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
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reset);
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/* Enable/Disable master CPU reset */
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reset_set_enable(PERIPH_ID_CPU, reset);
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@ -140,43 +140,6 @@ struct clk_rst_ctlr {
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uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
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};
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#define PLL_BYPASS (1 << 31)
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#define PLL_ENABLE (1 << 30)
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#define PLL_BASE_OVRRIDE (1 << 28)
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#define PLL_DIVP_VALUE (1 << 20) /* post divider, b22:20 */
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#define PLL_DIVM_VALUE 0x0C /* input divider, b4:0 */
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#define SWR_UARTD_RST (1 << 1)
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#define CLK_ENB_UARTD (1 << 1)
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#define SWR_UARTA_RST (1 << 6)
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#define CLK_ENB_UARTA (1 << 6)
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#define SWR_CPU_RST (1 << 0)
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#define CLK_ENB_CPU (1 << 0)
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#define SWR_CSITE_RST (1 << 9)
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#define CLK_ENB_CSITE (1 << 9)
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#define SET_CPURESET0 (1 << 0)
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#define SET_DERESET0 (1 << 4)
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#define SET_DBGRESET0 (1 << 12)
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#define SET_CPURESET1 (1 << 1)
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#define SET_DERESET1 (1 << 5)
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#define SET_DBGRESET1 (1 << 13)
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#define CLR_CPURESET0 (1 << 0)
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#define CLR_DERESET0 (1 << 4)
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#define CLR_DBGRESET0 (1 << 12)
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#define CLR_CPURESET1 (1 << 1)
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#define CLR_DERESET1 (1 << 5)
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#define CLR_DBGRESET1 (1 << 13)
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#define CPU0_CLK_STP (1 << 8)
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#define CPU1_CLK_STP (1 << 9)
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#define CPCON (1 << 8)
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/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
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#define CPU1_CLK_STP_SHIFT 9
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@ -81,20 +81,20 @@ static void clock_init_uart(void)
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u32 reg;
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reg = readl(&pll->pll_base);
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if (!(reg & PLL_BASE_OVRRIDE)) {
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if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
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/* Override pllp setup for 216MHz operation. */
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reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP_VALUE);
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reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE);
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reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
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(1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
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reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
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writel(reg, &pll->pll_base);
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reg |= PLL_ENABLE;
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reg |= PLL_ENABLE_MASK;
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writel(reg, &pll->pll_base);
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reg &= ~PLL_BYPASS;
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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}
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/* Now do the UART reset/clock enable */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
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/* Assert UART reset and enable clock */
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reset_set_enable(PERIPH_ID_UART1, 1);
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