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Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
Signed-off-by: Bastian Ruppert <Bastian.Ruppert@Sewerin.de> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: dzu@denx.de CC: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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f9fc237f1f
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ca1646b85d
2 changed files with 33 additions and 1 deletions
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@ -176,6 +176,10 @@ typedef volatile unsigned int * dv_reg_p;
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#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
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#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
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#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
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#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
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#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
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#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
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#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
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#endif /* CONFIG_SOC_DA8XX */
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/* Power and Sleep Controller (PSC) Domains */
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@ -35,6 +35,7 @@
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#include <asm/arch/emac_defs.h>
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#include <asm/io.h>
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#include <asm/arch/davinci_misc.h>
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#include <asm/arch/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -90,6 +91,12 @@ const struct pinmux_config nand_pins[] = {
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};
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#endif
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const struct pinmux_config gpio_pins[] = {
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{ pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
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{ pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
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{ pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/
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};
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static const struct pinmux_resource pinmuxes[] = {
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#ifdef CONFIG_SPI_FLASH
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PINMUX_ITEM(spi1_pins),
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@ -110,11 +117,32 @@ static const struct lpsc_resource lpsc[] = {
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int board_init(void)
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{
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struct davinci_gpio *gpio6_base =
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(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
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/* PinMux for GPIO */
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if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
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return 1;
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/* Set the RESETOUTn low */
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writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
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&gpio6_base->set_data);
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writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
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/* Set U0_SW0 low for UART0 as console*/
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writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
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&gpio6_base->set_data);
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writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
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/* Set U0_SW1 low for UART0 as console*/
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writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
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&gpio6_base->set_data);
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writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
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#ifndef CONFIG_USE_IRQ
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irq_init();
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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/*
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* NAND CS setup - cycle counts based on da850evm NAND timings in the
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