Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-25 14:10:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

powerpc/85xx: Add networking support to P1023RDS

Browse source 
The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII.  The second can only do SGMII & RGMII.

We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Roy Zang 2011-02-04 13:42:45 -06:00 committed by Kumar Gala
parent cba4614862
commit fe1a1da038
3 changed files with 45 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/powerpc/include/asm/immap_85xx.h
View file

@ -1984,6 +1984,9 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
#endif
#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
#else
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
@ -2002,6 +2005,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_QE10 0x00000020
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
#endif
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
#define MPC85xx_PMUXCR_TDM 0x00014800

40
board/freescale/p1023rds/p1023rds.c
View file

@ -38,6 +38,11 @@
#include <fdt_support.h>
#include <netdev.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include "bcsr.h"
@ -143,6 +148,39 @@ unsigned long get_board_ddr_clk(ulong dummy)
int board_eth_init(bd_t *bis)
{
u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
/*
* Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
* is not correct.
*/
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_mdio(FM1_DTSEC1,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
fm_info_set_mdio(FM1_DTSEC2,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
/* Make SERDES connected to SGMII by cleaing bcsr19[7] */
if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L);
#ifdef CONFIG_FMAN_ENET
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
@ -158,5 +196,7 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_fman_ethernet(blob);
}
#endif

2
include/configs/P1023RDS.h
View file

@ -525,9 +525,9 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_MARVELL
#endif
#define CONFIG_SYS_FMAN_FW
#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */