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ARM: OMAP4+: Clean up the pmic code

Browse source 
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
SRICHARAN R 2013-02-04 04:22:02 +00:00 committed by Tom Rini
parent ee9447bfe3
commit 3fcdd4a5f8
13 changed files with 199 additions and 260 deletions
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83
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -443,44 +443,45 @@ static void setup_non_essential_dplls(void)
}
#endif
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
{
u32 step;
int ret = 0;
u32 offset_code;
/* See if we can first get the GPIO if needed */
if (gpio >= 0)
ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
if (ret < 0) {
printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
gpio = -1;
}
volt_offset -= pmic->base_offset;
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (gpio >= 0)
gpio_direction_output(gpio, 0);
offset_code = (volt_offset + pmic->step - 1) / pmic->step;
step = volt_mv - TPS62361_BASE_VOLT_MV;
step /= 10;
debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
puts("Scaling voltage failed for vdd_mpu from TPS\n");
/* Pull the GPIO high to select SET1 register */
if (gpio >= 0)
gpio_direction_output(gpio, 1);
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
return offset_code + pmic->start_code;
}
void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
int ret = 0;
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
if (ret < 0) {
printf("%s: gpio %d request failed %d\n", __func__,
pmic->gpio, ret);
return;
}
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 0);
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
offset_code = get_offset_code(offset);
offset_code = get_offset_code(offset, pmic);
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
@ -488,6 +489,36 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(struct vcores_data const *vcores)
{
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
do_scale_vcore(vcores->core.addr, vcores->core.value,
vcores->core.pmic);
do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
vcores->mpu.pmic);
do_scale_vcore(vcores->mm.addr, vcores->mm.value,
vcores->mm.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, (*prcm)->prm_sldo_core_setup);
writel(2, (*prcm)->prm_sldo_mpu_setup);
writel(2, (*prcm)->prm_sldo_mm_setup);
}
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
@ -656,7 +687,7 @@ void prcm_init(void)
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
scale_vcores();
scale_vcores(*omap_vcores);
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();

1
arch/arm/cpu/armv7/omap4/Makefile
View file

@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).o
COBJS += sdram_elpida.o
COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
COBJS += prcm-regs.o
COBJS += hw_data.o

123
arch/arm/cpu/armv7/omap4/clocks.c
View file

@ -1,123 +0,0 @@
/*
*
* Clock initialization for OMAP4
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*
* Based on previous work by:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#ifndef CONFIG_SPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
*/
#define printf(fmt, args...)
#define puts(s)
#endif /* !CONFIG_SPL_BUILD */
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(void)
{
u32 volt, omap_rev;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
omap_rev = omap_revision();
/*
* Scale Voltage rails:
* 1. VDD_CORE
* 3. VDD_MPU
* 3. VDD_IVA
*/
if (omap_rev < OMAP4460_ES1_0) {
/*
* OMAP4430:
* VDD_CORE = TWL6030 VCORE3
* VDD_MPU = TWL6030 VCORE1
* VDD_IVA = TWL6030 VCORE2
*/
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
/*
* note on VDD_MPU:
* Setting a high voltage for Nitro mode as smart reflex is not
* enabled. We use the maximum possible value in the AVS range
* because the next higher voltage in the discrete range
* (code >= 0b111010) is way too high.
*/
volt = 1325;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
} else {
/*
* OMAP4460:
* VDD_CORE = TWL6030 VCORE1
* VDD_MPU = TPS62361
* VDD_IVA = TWL6030 VCORE2
*/
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
/* TPS62361 */
volt = 1203;
do_scale_tps62361(TPS62361_VSEL0_GPIO,
TPS62361_REG_ADDR_SET1, volt);
/* VCORE 2 - supplies vdd_iva */
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
}
}
u32 get_offset_code(u32 offset)
{
u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
if (omap_revision() == OMAP4430_ES1_0)
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
else
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
offset_code = (offset + step - 1) / step;
/* The code starts at 1 not 0 */
return ++offset_code;
}

70
arch/arm/cpu/armv7/omap4/hw_data.c
View file

@ -30,12 +30,15 @@
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
/*
* The M & N values in the following tables are created using the
@ -194,6 +197,70 @@ struct dplls omap4460_dplls = {
.usb = usb_dpll_params_1920mhz
};
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 10 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 10 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data tps62361 = {
.base_offset = TPS62361_BASE_VOLT_MV,
.step = 10000, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
.gpio_en = 1
};
struct vcores_data omap4430_volts_es1 = {
.mpu.value = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030_4430es1,
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030_4430es1,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030_4430es1,
};
struct vcores_data omap4430_volts = {
.mpu.value = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030,
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
struct vcores_data omap4460_volts = {
.mpu.value = 1203,
.mpu.addr = TPS62361_REG_ADDR_SET1,
.mpu.pmic = &tps62361,
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
.core.pmic = &tps62361,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &tps62361,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@ -382,6 +449,7 @@ void hw_data_init(void)
case OMAP4430_ES1_0:
*dplls_data = &omap4430_dplls_es1;
*omap_vcores = &omap4430_volts_es1;
break;
case OMAP4430_ES2_0:
@ -389,11 +457,13 @@ void hw_data_init(void)
case OMAP4430_ES2_2:
case OMAP4430_ES2_3:
*dplls_data = &omap4430_dplls;
*omap_vcores = &omap4430_volts;
break;
case OMAP4460_ES1_0:
case OMAP4460_ES1_1:
*dplls_data = &omap4460_dplls;
*omap_vcores = &omap4460_volts;
break;
default:

1
arch/arm/cpu/armv7/omap5/Makefile
View file

@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
COBJS += sdram.o
COBJS += prcm-regs.o

98
arch/arm/cpu/armv7/omap5/clocks.c
View file

@ -1,98 +0,0 @@
/*
*
* Clock initialization for OMAP5
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* Based on previous work by:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
*/
#define printf(fmt, args...)
#define puts(s)
#endif
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(void)
{
u32 volt_core, volt_mpu, volt_mm;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
/* Palmas settings */
if (omap_revision() != OMAP5432_ES1_0) {
volt_core = VDD_CORE;
volt_mpu = VDD_MPU;
volt_mm = VDD_MM;
} else {
volt_core = VDD_CORE_5432;
volt_mpu = VDD_MPU_5432;
volt_mm = VDD_MM_5432;
}
do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, (*prcm)->prm_sldo_core_setup);
writel(2, (*prcm)->prm_sldo_mpu_setup);
writel(2, (*prcm)->prm_sldo_mm_setup);
}
}
u32 get_offset_code(u32 volt_offset)
{
u32 offset_code, step = 10000; /* 10 mV represented in uV */
volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
offset_code = (volt_offset + step - 1) / step;
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
return offset_code + 6;
}

43
arch/arm/cpu/armv7/omap5/hw_data.c
View file

@ -30,12 +30,15 @@
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@ -179,6 +182,44 @@ struct dplls omap5_dplls_es1 = {
.usb = usb_dpll_params_1920mhz
};
struct pmic_data palmas = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
};
struct vcores_data omap5430_volts = {
.mpu.value = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.core.value = VDD_CORE,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value = VDD_MM,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
struct vcores_data omap5432_volts = {
.mpu.value = VDD_MPU_5432,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.core.value = VDD_CORE_5432,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value = VDD_MM_5432,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@ -380,11 +421,13 @@ void hw_data_init(void)
case OMAP5430_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
*omap_vcores = &omap5430_volts;
break;
case OMAP5432_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
*omap_vcores = &omap5432_volts;
break;
default:

5
arch/arm/include/asm/arch-omap4/clocks.h
View file

@ -242,11 +242,6 @@
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
void scale_vcores(void);
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
u32 get_offset_code(u32 offset);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
struct omap4_scrm_regs {
u32 revision; /* 0x0000 */
u32 pad00[63];

3
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -180,7 +180,8 @@ struct control_lpddr2io_regs {
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20)
/* ROM code defines */
/* Boot device */

4
arch/arm/include/asm/arch-omap5/clocks.h
View file

@ -234,8 +234,4 @@
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
void scale_vcores(void);
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
u32 get_offset_code(u32 offset);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
#endif /* _CLOCKS_OMAP5_H_ */

3
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -273,7 +273,8 @@ struct omap_sys_ctrl_regs {
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF

24
arch/arm/include/asm/omap_common.h
View file

@ -364,10 +364,31 @@ struct dplls {
const struct dpll_params *usb;
};
struct pmic_data {
u32 base_offset;
u32 step;
u32 start_code;
unsigned gpio;
int gpio_en;
};
struct volts {
u32 value;
u32 addr;
struct pmic_data *pmic;
};
struct vcores_data {
struct volts mpu;
struct volts core;
struct volts mm;
};
extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
extern struct prcm_regs const omap4_prcm;
extern struct dplls const **dplls_data;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
void hw_data_init(void);
@ -391,6 +412,9 @@ u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
/* Max value for DPLL multiplier M */
#define OMAP_DPLL_MAX_N 127

1
include/configs/omap5_evm.h
View file

@ -265,5 +265,6 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
#define CONFIG_SPL_GPIO_SUPPORT
#endif /* __CONFIG_H */