Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 08:01:08 +00:00
Code Issues Projects Releases Packages Wiki Activity

x86: Create weak init_cache() and default enable_caches() functions

Browse source 
--
Changes for v2:
 - Tweaked commit title
This commit is contained in:
Graeme Russ 2011-12-27 22:46:43 +11:00
parent 3766bb33a5
commit d653244b12
3 changed files with 17 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
arch/x86/cpu/cpu.c
View file

@ -139,6 +139,14 @@ int x86_cpu_init_f(void)
int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
int x86_cpu_init_r(void)
{
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts();
return 0;
}
int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
void x86_enable_caches(void)
{
const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
@ -147,12 +155,16 @@ int x86_cpu_init_r(void)
"andl %0, %%eax\n"
"movl %%eax, %%cr0\n"
"wbinvd\n" : : "i" (nw_cd_rst) : "eax");
}
void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
int x86_init_cache(void)
{
enable_caches();
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts();
return 0;
}
int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{

1
arch/x86/include/asm/u-boot-x86.h
View file

@ -39,6 +39,7 @@ int x86_cpu_init_f(void);
int cpu_init_f(void);
void init_gd(gd_t *id, u64 *gdt_addr);
void setup_gdt(gd_t *id, u64 *gdt_addr);
int init_cache(void);
/* cpu/.../timer.c */
void timer_isr(void *);

1
arch/x86/lib/board.c
View file

@ -140,6 +140,7 @@ init_fnc_t *init_sequence_f[] = {
init_fnc_t *init_sequence_r[] = {
copy_gd_to_ram,
init_cache,
cpu_init_r, /* basic cpu dependent setup */
board_early_init_r, /* basic board dependent setup */
dram_init, /* configure available RAM banks */