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https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
omap4: IO settings
Tuning some IO settings for better performance and power. And consolidate all such IO settings at one place. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Aneesh V
Albert ARIBAUD
parent
025bc4254b
commit
4ecfcfaa9e
4 changed files with 105 additions and 45 deletions
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@ -70,6 +70,67 @@ u32 omap_boot_mode(void)
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{
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return omap4_boot_mode;
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}
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/*
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* Some tuning of IOs for optimal power and performance
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*/
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static void do_io_settings(void)
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{
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u32 lpddr2io;
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struct control_lpddr2io_regs *lpddr2io_regs =
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(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
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struct omap4_sys_ctrl_regs *const ctrl =
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(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
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u32 omap4_rev = omap_revision();
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if (omap4_rev == OMAP4430_ES1_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
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else if (omap4_rev == OMAP4430_ES2_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
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else
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lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
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/* EMIF1 */
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
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/* No pull for GR10 as per hw team's recommendation */
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writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
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&lpddr2io_regs->control_lpddr2io1_2);
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writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
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/* EMIF2 */
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
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/* No pull for GR10 as per hw team's recommendation */
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writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
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&lpddr2io_regs->control_lpddr2io2_2);
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writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
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/*
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* Some of these settings (TRIM values) come from eFuse and are
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* in turn programmed in the eFuse at manufacturing time after
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* calibration of the device. Do the software over-ride only if
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* the device is not correctly trimmed
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*/
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if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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&ctrl->control_ldosram_iva_voltage_ctrl);
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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&ctrl->control_ldosram_mpu_voltage_ctrl);
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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&ctrl->control_ldosram_core_voltage_ctrl);
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}
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if (!readl(&ctrl->control_efuse_1))
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writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
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if (!readl(&ctrl->control_efuse_2))
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writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
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}
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#endif
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void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
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@ -197,6 +258,7 @@ void s_init(void)
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set_mux_conf_regs();
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#ifdef CONFIG_SPL_BUILD
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preloader_console_init();
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do_io_settings();
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#endif
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prcm_init();
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#ifdef CONFIG_SPL_BUILD
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@ -1063,30 +1063,6 @@ static void do_sdram_init(u32 base)
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debug("<<do_sdram_init() %x\n", base);
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}
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void sdram_init_pads(void)
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{
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u32 lpddr2io;
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struct control_lpddr2io_regs *lpddr2io_regs =
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(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
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u32 omap4_rev = omap_revision();
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if (omap4_rev == OMAP4430_ES1_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
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else if (omap4_rev == OMAP4430_ES2_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
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else
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return; /* Post ES2.1 reset values will work */
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
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writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
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}
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static void emif_post_init_config(u32 base)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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@ -1243,7 +1219,6 @@ void sdram_init(void)
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debug("in_sdram = %d\n", in_sdram);
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if (!in_sdram) {
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sdram_init_pads();
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bypass_dpll(&prcm->cm_clkmode_dpll_core);
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}
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@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {
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u32 dmm_lisa_map_3;
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};
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struct control_lpddr2io_regs {
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u32 control_lpddr2io1_0;
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u32 control_lpddr2io1_1;
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u32 control_lpddr2io1_2;
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u32 control_lpddr2io1_3;
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u32 control_lpddr2io2_0;
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u32 control_lpddr2io2_1;
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u32 control_lpddr2io2_2;
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u32 control_lpddr2io2_3;
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};
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#define CS0 0
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#define CS1 1
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/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
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@ -823,13 +812,6 @@ struct control_lpddr2io_regs {
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/* MR16 value: refresh full array(no partial array self refresh) */
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#define MR16_REF_FULL_ARRAY 0
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/* LPDDR2 IO regs */
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#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
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#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
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/* CONTROL_EFUSE_2 */
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#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
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/*
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* Maximum number of entries we keep in our array of timing tables
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* We need not keep all the speed bins supported by the device
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@ -54,8 +54,6 @@
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/* LPDDR2 IO regs */
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#define LPDDR2_IO_REGS_BASE 0x4A100638
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#define CONTROL_EFUSE_2 0x4A100704
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/* CONTROL_ID_CODE */
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#define CONTROL_ID_CODE 0x4A002204
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@ -84,6 +82,9 @@
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/* GPMC */
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#define OMAP44XX_GPMC_BASE 0x50000000
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/* SYSTEM CONTROL MODULE */
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#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
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/*
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* Hardware Register Details
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*/
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@ -108,6 +109,22 @@
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#define PRM_RSTCTRL PRM_DEVICE_BASE
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#define PRM_RSTCTRL_RESET 0x01
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/* Control Module */
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#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
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#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
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#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
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#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
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/* LPDDR2 IO regs */
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#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
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#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
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#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
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#define LPDDR2IO_GR10_WD_MASK (3 << 17)
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#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
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/* CONTROL_EFUSE_2 */
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#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
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#ifndef __ASSEMBLY__
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struct s32ktimer {
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@ -115,6 +132,30 @@ struct s32ktimer {
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unsigned int s32k_cr; /* 0x10 */
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};
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struct omap4_sys_ctrl_regs {
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unsigned int pad1[129];
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unsigned int control_id_code; /* 0x4A002204 */
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unsigned int pad11[22];
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unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
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unsigned int pad2[47];
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unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
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unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
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unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
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unsigned int pad3[260341];
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unsigned int control_efuse_1; /* 0x4A100700 */
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unsigned int control_efuse_2; /* 0x4A100704 */
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};
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struct control_lpddr2io_regs {
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unsigned int control_lpddr2io1_0;
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unsigned int control_lpddr2io1_1;
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unsigned int control_lpddr2io1_2;
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unsigned int control_lpddr2io1_3;
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unsigned int control_lpddr2io2_0;
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unsigned int control_lpddr2io2_1;
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unsigned int control_lpddr2io2_2;
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unsigned int control_lpddr2io2_3;
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};
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#endif /* __ASSEMBLY__ */
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/*
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