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powerpc/mpc85xx: move debug tlb entry after TLB is in known state

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Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
This commit is contained in:
Scott Wood 2012-10-25 19:27:41 -05:00
parent cb55b33200
commit f545d300b0
1 changed files with 40 additions and 44 deletions
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84
arch/powerpc/cpu/mpc85xx/start.S
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@ -282,46 +282,6 @@ l2_disabled:
isync
.endm
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
* As on debug exception MSR is cleared i.e. Address space is changed
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
* in AS1.
*/
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_4M, \
CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* because "nexti" will resize TLB to 4K
*/
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_256K, \
CONFIG_SYS_MONITOR_BASE, MAS2_I, \
CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
#endif
/*
* Ne need to setup interrupt vector for NAND SPL
* because NAND SPL never compiles it.
@ -534,10 +494,6 @@ nexti: mflr r1 /* R1 = our PC */
li r3, 0
mtspr MAS1, r3
1: cmpw r3, r14
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
cror cr0*4+eq, cr0*4+eq, cr1*4+eq
#endif
rlwinm r5, r3, 16, MAS0_ESEL_MSK
addi r3, r3, 1
beq 2f /* skip the entry we're executing from */
@ -553,6 +509,46 @@ nexti: mflr r1 /* R1 = our PC */
2: cmpw r3, r4
blt 1b
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
* As on debug exception MSR is cleared i.e. Address space is changed
* to 0. A TLB entry (in AS0) is required to handle debug exception generated
* in AS1.
*/
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_4M, \
CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_1M, \
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* because "nexti" will resize TLB to 4K
*/
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
0, BOOKE_PAGESZ_256K, \
CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
#endif
/*
* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
* location is not where we want it. This typically happens on a 36-bit