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am335x: Update timings for the beaglebone again
After further testing we can run DDR at 400MHz so update the timings again. Tested-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com>
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2 changed files with 11 additions and 11 deletions
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@ -84,19 +84,19 @@
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#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
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/* Micron MT41K256M16HA-125E */
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#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
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#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
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#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
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#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
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#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
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#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
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#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
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#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA
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#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2
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#define MT41K256M16HA125E_EMIF_SDREF 0xC30
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#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
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#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
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#define MT41K256M16HA125E_RATIO 0x40
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#define MT41K256M16HA125E_RATIO 0x80
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#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
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#define MT41K256M16HA125E_RD_DQS 0x3C
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#define MT41K256M16HA125E_WR_DQS 0x45
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#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
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#define MT41K256M16HA125E_RD_DQS 0x3A
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#define MT41K256M16HA125E_WR_DQS 0x42
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#define MT41K256M16HA125E_PHY_WR_DATA 0x7E
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#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
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#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
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@ -379,7 +379,7 @@ void s_init(void)
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config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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else if (board_is_bone_lt())
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config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE,
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config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
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&ddr3_beagleblack_data,
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&ddr3_beagleblack_cmd_ctrl_data,
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&ddr3_beagleblack_emif_reg_data, 0);
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