mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-17 15:27:00 +00:00
ARM:AM33XX: Added support for AM33xx
This patch adds basic support for AM33xx which is based on ARMV7 Cortex A8 CPU. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
parent
40b95c8956
commit
5655108a82
5 changed files with 545 additions and 0 deletions
44
arch/arm/cpu/armv7/am33xx/Makefile
Normal file
44
arch/arm/cpu/armv7/am33xx/Makefile
Normal file
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
# kind, whether express or implied; without even the implied warranty
|
||||
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
COBJS += sys_info.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
72
arch/arm/cpu/armv7/am33xx/lowlevel_init.S
Normal file
72
arch/arm/cpu/armv7/am33xx/lowlevel_init.S
Normal file
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* lowlevel_init.S
|
||||
*
|
||||
* AM33XX low level initialization.
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Initial Code by:
|
||||
* Mansoor Ahamed <mansoor.ahamed@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
_mark1:
|
||||
.word mark1
|
||||
_lowlevel_init1:
|
||||
.word lowlevel_init
|
||||
_s_init_start:
|
||||
.word s_init_start
|
||||
|
||||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
|
||||
|
||||
/*****************************************************************************
|
||||
* lowlevel_init: - Platform low level init.
|
||||
****************************************************************************/
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
/* The link register is saved in ip by start.S */
|
||||
mov r6, ip
|
||||
/* check if we are already running from RAM */
|
||||
ldr r2, _lowlevel_init1
|
||||
ldr r3, _TEXT_BASE
|
||||
sub r4, r2, r3
|
||||
sub r0, pc, r4
|
||||
ldr sp, SRAM_STACK
|
||||
mark1:
|
||||
ldr r5, _mark1
|
||||
sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
|
||||
sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
|
||||
mov r10, #0x0 /* r10 has in_ddr used by s_init() */
|
||||
|
||||
ands r0, r0, #0xC0000000
|
||||
/* MSB 2 bits <> 0 then we are in ocmc or DDR */
|
||||
cmp r0, #0x80000000
|
||||
bne s_init_start
|
||||
mov r10, #0x01
|
||||
b s_init_start
|
||||
|
||||
s_init_start:
|
||||
mov r0, r10 /* passing in_ddr in r0 */
|
||||
bl s_init
|
||||
/* back to arch calling code */
|
||||
mov pc, r6
|
||||
/* the literal pools origin */
|
||||
.ltorg
|
||||
|
||||
SRAM_STACK:
|
||||
/* Place stack at the top */
|
||||
.word LOW_LEVEL_SRAM_STACK
|
130
arch/arm/cpu/armv7/am33xx/sys_info.c
Normal file
130
arch/arm/cpu/armv7/am33xx/sys_info.c
Normal file
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* sys_info.c
|
||||
*
|
||||
* System information functions
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
|
||||
|
||||
/**
|
||||
* get_cpu_rev(void) - extract rev info
|
||||
*/
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
u32 id;
|
||||
u32 rev;
|
||||
|
||||
id = readl(DEVICE_ID);
|
||||
rev = (id >> 28) & 0xff;
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_cpu_type(void) - extract cpu info
|
||||
*/
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
u32 id = 0;
|
||||
u32 partnum;
|
||||
|
||||
id = readl(DEVICE_ID);
|
||||
partnum = (id >> 12) & 0xffff;
|
||||
|
||||
return partnum;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_board_rev() - setup to pass kernel board revision information
|
||||
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
|
||||
*/
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return BOARD_REV_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_device_type(): tell if GP/HS/EMU/TST
|
||||
*/
|
||||
u32 get_device_type(void)
|
||||
{
|
||||
int mode;
|
||||
mode = readl(&cstat->statusreg) & (DEVICE_MASK);
|
||||
return mode >>= 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_sysboot_value(void) - return SYS_BOOT[4:0]
|
||||
*/
|
||||
u32 get_sysboot_value(void)
|
||||
{
|
||||
int mode;
|
||||
mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
|
||||
return mode;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
/**
|
||||
* Print CPU information
|
||||
*/
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
char *cpu_s, *sec_s;
|
||||
int arm_freq, ddr_freq;
|
||||
|
||||
switch (get_cpu_type()) {
|
||||
case AM335X:
|
||||
cpu_s = "AM335X";
|
||||
break;
|
||||
default:
|
||||
cpu_s = "Unknown cpu type";
|
||||
break;
|
||||
}
|
||||
|
||||
switch (get_device_type()) {
|
||||
case TST_DEVICE:
|
||||
sec_s = "TST";
|
||||
break;
|
||||
case EMU_DEVICE:
|
||||
sec_s = "EMU";
|
||||
break;
|
||||
case HS_DEVICE:
|
||||
sec_s = "HS";
|
||||
break;
|
||||
case GP_DEVICE:
|
||||
sec_s = "GP";
|
||||
break;
|
||||
default:
|
||||
sec_s = "?";
|
||||
}
|
||||
|
||||
printf("AM%s-%s rev %d\n",
|
||||
cpu_s, sec_s, get_cpu_rev());
|
||||
|
||||
/* TODO: Print ARM and DDR frequencies */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DISPLAY_CPUINFO */
|
218
arch/arm/include/asm/arch-am33xx/cpu.h
Normal file
218
arch/arm/include/asm/arch-am33xx/cpu.h
Normal file
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* cpu.h
|
||||
*
|
||||
* AM33xx specific header file
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _AM33XX_CPU_H
|
||||
#define _AM33XX_CPU_H
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define BIT(x) (1 << x)
|
||||
#define CL_BIT(x) (0 << x)
|
||||
|
||||
/* Timer register bits */
|
||||
#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
|
||||
#define TCLR_AR BIT(1) /* Auto reload */
|
||||
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
|
||||
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
|
||||
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
|
||||
|
||||
/* device type */
|
||||
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
|
||||
#define TST_DEVICE 0x0
|
||||
#define EMU_DEVICE 0x1
|
||||
#define HS_DEVICE 0x2
|
||||
#define GP_DEVICE 0x3
|
||||
|
||||
/* cpu-id for AM33XX family */
|
||||
#define AM335X 0xB944
|
||||
#define DEVICE_ID 0x44E10600
|
||||
|
||||
/* This gives the status of the boot mode pins on the evm */
|
||||
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
|
||||
| BIT(3) | BIT(4))
|
||||
|
||||
/* Reset control */
|
||||
#ifdef CONFIG_AM335X
|
||||
#define PRM_RSTCTRL 0x44E00F00
|
||||
#endif
|
||||
#define PRM_RSTCTRL_RESET 0x01
|
||||
|
||||
#ifndef __KERNEL_STRICT_NAMES
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Encapsulating core pll registers */
|
||||
struct cm_wkuppll {
|
||||
unsigned int wkclkstctrl; /* offset 0x00 */
|
||||
unsigned int wkctrlclkctrl; /* offset 0x04 */
|
||||
unsigned int resv1[1];
|
||||
unsigned int wkl4wkclkctrl; /* offset 0x0c */
|
||||
unsigned int resv2[4];
|
||||
unsigned int idlestdpllmpu; /* offset 0x20 */
|
||||
unsigned int resv3[2];
|
||||
unsigned int clkseldpllmpu; /* offset 0x2c */
|
||||
unsigned int resv4[1];
|
||||
unsigned int idlestdpllddr; /* offset 0x34 */
|
||||
unsigned int resv5[2];
|
||||
unsigned int clkseldpllddr; /* offset 0x40 */
|
||||
unsigned int resv6[4];
|
||||
unsigned int clkseldplldisp; /* offset 0x54 */
|
||||
unsigned int resv7[1];
|
||||
unsigned int idlestdpllcore; /* offset 0x5c */
|
||||
unsigned int resv8[2];
|
||||
unsigned int clkseldpllcore; /* offset 0x68 */
|
||||
unsigned int resv9[1];
|
||||
unsigned int idlestdpllper; /* offset 0x70 */
|
||||
unsigned int resv10[3];
|
||||
unsigned int divm4dpllcore; /* offset 0x80 */
|
||||
unsigned int divm5dpllcore; /* offset 0x84 */
|
||||
unsigned int clkmoddpllmpu; /* offset 0x88 */
|
||||
unsigned int clkmoddpllper; /* offset 0x8c */
|
||||
unsigned int clkmoddpllcore; /* offset 0x90 */
|
||||
unsigned int clkmoddpllddr; /* offset 0x94 */
|
||||
unsigned int clkmoddplldisp; /* offset 0x98 */
|
||||
unsigned int clkseldpllper; /* offset 0x9c */
|
||||
unsigned int divm2dpllddr; /* offset 0xA0 */
|
||||
unsigned int divm2dplldisp; /* offset 0xA4 */
|
||||
unsigned int divm2dpllmpu; /* offset 0xA8 */
|
||||
unsigned int divm2dpllper; /* offset 0xAC */
|
||||
unsigned int resv11[1];
|
||||
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
|
||||
unsigned int resv12[8];
|
||||
unsigned int divm6dpllcore; /* offset 0xD8 */
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulating peripheral functional clocks
|
||||
* pll registers
|
||||
*/
|
||||
struct cm_perpll {
|
||||
unsigned int l4lsclkstctrl; /* offset 0x00 */
|
||||
unsigned int l3sclkstctrl; /* offset 0x04 */
|
||||
unsigned int l4fwclkstctrl; /* offset 0x08 */
|
||||
unsigned int l3clkstctrl; /* offset 0x0c */
|
||||
unsigned int resv1[6];
|
||||
unsigned int emifclkctrl; /* offset 0x28 */
|
||||
unsigned int ocmcramclkctrl; /* offset 0x2c */
|
||||
unsigned int resv2[12];
|
||||
unsigned int l4lsclkctrl; /* offset 0x60 */
|
||||
unsigned int l4fwclkctrl; /* offset 0x64 */
|
||||
unsigned int resv3[6];
|
||||
unsigned int timer2clkctrl; /* offset 0x80 */
|
||||
unsigned int resv4[19];
|
||||
unsigned int emiffwclkctrl; /* offset 0xD0 */
|
||||
unsigned int resv5[2];
|
||||
unsigned int l3instrclkctrl; /* offset 0xDC */
|
||||
unsigned int l3clkctrl; /* Offset 0xE0 */
|
||||
unsigned int resv6[14];
|
||||
unsigned int l4hsclkstctrl; /* offset 0x11C */
|
||||
unsigned int l4hsclkctrl; /* offset 0x120 */
|
||||
};
|
||||
|
||||
/* Encapsulating Display pll registers */
|
||||
struct cm_dpll {
|
||||
unsigned int resv1[2];
|
||||
unsigned int clktimer2clk; /* offset 0x08 */
|
||||
};
|
||||
|
||||
/* Watchdog timer registers */
|
||||
struct wd_timer {
|
||||
unsigned int resv1[4];
|
||||
unsigned int wdtwdsc; /* offset 0x010 */
|
||||
unsigned int wdtwdst; /* offset 0x014 */
|
||||
unsigned int wdtwisr; /* offset 0x018 */
|
||||
unsigned int wdtwier; /* offset 0x01C */
|
||||
unsigned int wdtwwer; /* offset 0x020 */
|
||||
unsigned int wdtwclr; /* offset 0x024 */
|
||||
unsigned int wdtwcrr; /* offset 0x028 */
|
||||
unsigned int wdtwldr; /* offset 0x02C */
|
||||
unsigned int wdtwtgr; /* offset 0x030 */
|
||||
unsigned int wdtwwps; /* offset 0x034 */
|
||||
unsigned int resv2[3];
|
||||
unsigned int wdtwdly; /* offset 0x044 */
|
||||
unsigned int wdtwspr; /* offset 0x048 */
|
||||
unsigned int resv3[1];
|
||||
unsigned int wdtwqeoi; /* offset 0x050 */
|
||||
unsigned int wdtwqstar; /* offset 0x054 */
|
||||
unsigned int wdtwqsta; /* offset 0x058 */
|
||||
unsigned int wdtwqens; /* offset 0x05C */
|
||||
unsigned int wdtwqenc; /* offset 0x060 */
|
||||
unsigned int resv4[39];
|
||||
unsigned int wdt_unfr; /* offset 0x100 */
|
||||
};
|
||||
|
||||
/* Timer Registers */
|
||||
struct timer_reg {
|
||||
unsigned int resv1[4];
|
||||
unsigned int tiocpcfgreg; /* offset 0x10 */
|
||||
unsigned int resv2[9];
|
||||
unsigned int tclrreg; /* offset 0x38 */
|
||||
unsigned int tcrrreg; /* offset 0x3C */
|
||||
unsigned int tldrreg; /* offset 0x40 */
|
||||
unsigned int resv3[4];
|
||||
unsigned int tsicrreg; /* offset 0x54 */
|
||||
};
|
||||
|
||||
/* Timer 32 bit registers */
|
||||
struct gptimer {
|
||||
unsigned int tidr; /* offset 0x00 */
|
||||
unsigned int res1[0xc];
|
||||
unsigned int tiocp_cfg; /* offset 0x10 */
|
||||
unsigned int res2[0xc];
|
||||
unsigned int tier; /* offset 0x20 */
|
||||
unsigned int tistatr; /* offset 0x24 */
|
||||
unsigned int tistat; /* offset 0x28 */
|
||||
unsigned int tisr; /* offset 0x2c */
|
||||
unsigned int tcicr; /* offset 0x30 */
|
||||
unsigned int twer; /* offset 0x34 */
|
||||
unsigned int tclr; /* offset 0x38 */
|
||||
unsigned int tcrr; /* offset 0x3c */
|
||||
unsigned int tldr; /* offset 0x40 */
|
||||
unsigned int ttgr; /* offset 0x44 */
|
||||
unsigned int twpc; /* offset 0x48 */
|
||||
unsigned int tmar; /* offset 0x4c */
|
||||
unsigned int tcar1; /* offset 0x50 */
|
||||
unsigned int tscir; /* offset 0x54 */
|
||||
unsigned int tcar2; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* UART Registers */
|
||||
struct uart_sys {
|
||||
unsigned int resv1[21];
|
||||
unsigned int uartsyscfg; /* offset 0x54 */
|
||||
unsigned int uartsyssts; /* offset 0x58 */
|
||||
};
|
||||
|
||||
/* VTP Registers */
|
||||
struct vtp_reg {
|
||||
unsigned int vtp0ctrlreg;
|
||||
};
|
||||
|
||||
/* Control Status Register */
|
||||
struct ctrl_stat {
|
||||
unsigned int resv1[16];
|
||||
unsigned int statusreg; /* ofset 0x40 */
|
||||
};
|
||||
|
||||
void init_timer(void);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL_STRICT_NAMES */
|
||||
|
||||
#endif /* _AM33XX_CPU_H */
|
81
arch/arm/include/asm/arch-am33xx/hardware.h
Normal file
81
arch/arm/include/asm/arch-am33xx/hardware.h
Normal file
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* hardware.h
|
||||
*
|
||||
* hardware specific header
|
||||
*
|
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_H
|
||||
#define __AM33XX_HARDWARE_H
|
||||
|
||||
/* Module base addresses */
|
||||
#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
|
||||
#define UART0_BASE 0x44E09000
|
||||
|
||||
/* DM Timer base addresses */
|
||||
#define DM_TIMER0_BASE 0x4802C000
|
||||
#define DM_TIMER1_BASE 0x4802E000
|
||||
#define DM_TIMER2_BASE 0x48040000
|
||||
#define DM_TIMER3_BASE 0x48042000
|
||||
#define DM_TIMER4_BASE 0x48044000
|
||||
#define DM_TIMER5_BASE 0x48046000
|
||||
#define DM_TIMER6_BASE 0x48048000
|
||||
#define DM_TIMER7_BASE 0x4804A000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO0_BASE 0x48032000
|
||||
#define GPIO1_BASE 0x4804C000
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* BCH Error Location Module */
|
||||
#define ELM_BASE 0x48080000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44E00000
|
||||
|
||||
/* EMIF Base address */
|
||||
#define EMIF4_0_CFG_BASE 0x4C000000
|
||||
#define EMIF4_1_CFG_BASE 0x4D000000
|
||||
#define DMM_BASE 0x4E000000
|
||||
|
||||
/* PLL related registers */
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
#define CM_DPLL 0x44E00500
|
||||
#define CM_DEVICE 0x44E00700
|
||||
#define CM_CEFUSE 0x44E00A00
|
||||
#define PRM_DEVICE 0x44E00F00
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_CTRL_ADDR 0x44E10E04
|
||||
#define DDR_CONTROL_BASE_ADDR 0x44E11404
|
||||
#define DDR_PHY_BASE_ADDR 0x44E12000
|
||||
#define DDR_PHY_BASE_ADDR2 0x44E120A4
|
||||
|
||||
/* UART */
|
||||
#define DEFAULT_UART_BASE UART0_BASE
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_H */
|
Loading…
Add table
Reference in a new issue