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tegra: Correct PLL access in ap20.c and clock.c
Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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00a55add04
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3 changed files with 9 additions and 6 deletions
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@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void)
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void init_pllx(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll_simple *pll =
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&clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
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u32 reg;
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/* If PLLX is already enabled, just return */
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@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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assert(clock_id_isvalid(clkid));
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assert(clock_id_is_pll(clkid));
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return &clkrst->crc_pll[clkid];
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}
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@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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assert(clkid != CLOCK_ID_USB);
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/* Safety check, adds to code size but is small */
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if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
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if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
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return -1;
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data = readl(&pll->pll_base);
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*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
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@ -186,8 +186,9 @@ enum periph_id {
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/* Mask value for a clock (within PERIPH_REG(id)) */
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#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
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/* return 1 if a PLL ID is in range */
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#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
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/* return 1 if a PLL ID is in range, and not a simple PLL */
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#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
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(id) < CLOCK_ID_FIRST_SIMPLE)
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/* PLL stabilization delay in usec */
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#define CLOCK_PLL_STABLE_DELAY_US 300
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