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mx5 clocks: Fix MXC_FEC_CLK
The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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1 changed files with 2 additions and 3 deletions
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@ -474,7 +474,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
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case MXC_CSPI_CLK:
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return imx_get_cspiclk();
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case MXC_FEC_CLK:
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return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
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return get_ipg_clk();
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case MXC_SATA_CLK:
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return get_ahb_clk();
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case MXC_DDR_CLK:
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@ -490,10 +490,9 @@ u32 imx_get_uartclk(void)
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return get_uart_clk();
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}
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u32 imx_get_fecclk(void)
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{
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return mxc_get_clock(MXC_IPG_CLK);
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return get_ipg_clk();
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}
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static int gcd(int m, int n)
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