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Merge branch 'master' of git://git.denx.de/u-boot-arm

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* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2012-07-08 19:26:33 +02:00
commit 50cd93b250
258 changed files with 11050 additions and 1797 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
MAINTAINERS
View file

@ -742,6 +742,9 @@ Sergey Lapin <slapin@ossfans.org>
Valentin Longchamp <valentin.longchamp@keymile.com>
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)
mgcoge3un ARM926EJS (Kirkwood SoC)
kmcoge5un ARM926EJS (Kirkwood SoC)
portl2 ARM926EJS (Kirkwood SoC)
Nishanth Menon <nm@ti.com>
@ -847,12 +850,12 @@ Steve Sakoman <sakoman@gmail.com>
Jens Scharsig <esw@bus-elektronik.de>
eb_cpux9k2 ARM920T (AT91RM9200 SoC)
vl_ma2sc ARM926EJS (AT91SAM9263 SoC)
Heiko Schocher <hs@denx.de>
enbw_cmc ARM926EJS (AM1808 SoC)
magnesium i.MX27
mgcoge3un ARM926EJS (Kirkwood SoC)
Michael Schwingen <michael@schwingen.org>
@ -906,6 +909,11 @@ Prafulla Wadaskar <prafulla@marvell.com>
rd6281a ARM926EJS (Kirkwood SoC)
sheevaplug ARM926EJS (Kirkwood SoC)
Michael Walle <michael@walle.cc>
lschlv2 ARM926EJS (Kirkwood SoC)
lsxhl ARM926EJS (Kirkwood SoC)
Tom Warren <twarren@nvidia.com>
harmony Tegra2 (ARM7 & A9 Dual Core)
@ -916,6 +924,8 @@ Stephen Warren <swarren@nvidia.com>
ventana Tegra2 (ARM7 & A9 Dual Core)
paz00 Tegra2 (ARM7 & A9 Dual Core)
trimslice Tegra2 (ARM7 & A9 Dual Core)
whistler Tegra2 (ARM7 & A9 Dual Core)
Thomas Weber <weber@corscience.de>

17
Makefile
View file

@ -456,6 +456,22 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
# bootloader can check its integrity. Padding needs to be done to the
# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
# The resulting image containing both U-Boot images is called u-boot.spr
$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \
-d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img
tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null
dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \
conv=notrunc 2>/dev/null
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@ -775,6 +791,7 @@ clobber: tidy
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
@rm -f $(obj)u-boot.spr
@rm -f $(obj)tools/inca-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c

7
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
View file

@ -523,9 +523,8 @@ VTPLock:
ldr r6, DDRVTPR
ldr r7, [r6]
and r7, r7, $0x1f
and r8, r7, $0x3e0
orr r8, r7, r8
mov r8, r7, LSL #32-10
mov r8, r8, LSR #32-10 /* grab low 10 bits */
ldr r7, VTP_RECAL
orr r8, r7, r8
ldr r7, VTP_EN
@ -644,7 +643,7 @@ VTP_LOCK_COUNT:
VTP_MASK:
.word 0xffffdfff
VTP_RECAL:
.word 0x40000
.word 0x08000
VTP_EN:
.word 0x02000
CFGTEST:

10
arch/arm/cpu/arm926ejs/kirkwood/mpp.c
View file

@ -31,7 +31,7 @@ static u32 kirkwood_variant(void)
#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
#define MPP_NR_REGS (1 + MPP_MAX/8)
void kirkwood_mpp_conf(u32 *mpp_list)
void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
@ -52,6 +52,7 @@ void kirkwood_mpp_conf(u32 *mpp_list)
while (*mpp_list) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
unsigned int sel_save;
int shift;
if (num > MPP_MAX) {
@ -66,6 +67,13 @@ void kirkwood_mpp_conf(u32 *mpp_list)
}
shift = (num & 7) << 2;
if (mpp_save) {
sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
*mpp_save = num | (sel_save << 8) | variant_mask;
mpp_save++;
}
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;

2
arch/arm/cpu/arm926ejs/mx28/mx28.c
View file

@ -153,7 +153,6 @@ int arch_misc_init(void)
}
#endif
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
@ -187,7 +186,6 @@ int arch_cpu_init(void)
return 0;
}
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)

8
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
View file

@ -82,10 +82,18 @@ uint32_t dram_vals[] = {
0x00000000, 0x00010001
};
void __mx28_adjust_memory_params(uint32_t *dram_vals)
{
}
void mx28_adjust_memory_params(uint32_t *dram_vals)
__attribute__((weak, alias("__mx28_adjust_memory_params")));
void init_m28_200mhz_ddr2(void)
{
int i;
mx28_adjust_memory_params(dram_vals);
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}

25
arch/arm/cpu/arm926ejs/spear/Makefile
View file

@ -25,16 +25,27 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS := reset.o \
COBJS-y := cpu.o \
reset.o \
timer.o
SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
ifdef CONFIG_SPL_BUILD
COBJS-y += spl.o spl_boot.o
COBJS-$(CONFIG_SPEAR600) += spear600.o
COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
endif
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
SRCS := $(START:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################

87
arch/arm/cpu/arm926ejs/spear/cpu.c Normal file
View file

@ -0,0 +1,87 @@
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_misc.h>
int arch_cpu_init(void)
{
struct misc_regs *const misc_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 periph1_clken, periph_clk_cfg;
periph1_clken = readl(&misc_p->periph1_clken);
#if defined(CONFIG_SPEAR3XX)
periph1_clken |= MISC_GPT2ENB;
#elif defined(CONFIG_SPEAR600)
periph1_clken |= MISC_GPT3ENB;
#endif
#if defined(CONFIG_PL011_SERIAL)
periph1_clken |= MISC_UART0ENB;
periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
periph_clk_cfg |= CONFIG_SPEAR_UART48M;
writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
#endif
#if defined(CONFIG_DESIGNWARE_ETH)
periph1_clken |= MISC_ETHENB;
#endif
#if defined(CONFIG_DW_UDC)
periph1_clken |= MISC_USBDENB;
#endif
#if defined(CONFIG_DW_I2C)
periph1_clken |= MISC_I2CENB;
#endif
#if defined(CONFIG_ST_SMI)
periph1_clken |= MISC_SMIENB;
#endif
#if defined(CONFIG_NAND_FSMC)
periph1_clken |= MISC_FSMCENB;
#endif
writel(periph1_clken, &misc_p->periph1_clken);
return 0;
}
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
#ifdef CONFIG_SPEAR300
printf("CPU: SPEAr300\n");
#elif defined(CONFIG_SPEAR310)
printf("CPU: SPEAr310\n");
#elif defined(CONFIG_SPEAR320)
printf("CPU: SPEAr320\n");
#elif defined(CONFIG_SPEAR600)
printf("CPU: SPEAr600\n");
#else
#error CPU not supported in spear platform
#endif
return 0;
}
#endif

236
arch/arm/cpu/arm926ejs/spear/spear600.c Normal file
View file

@ -0,0 +1,236 @@
/*
* (C) Copyright 2000-2009
* Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_defs.h>
#define FALSE 0
#define TRUE (!FALSE)
static void sel_1v8(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 ddr1v8, ddr2v5;
ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
ddr2v5 &= 0x8080ffc0;
ddr2v5 |= 0x78000003;
writel(ddr2v5, &misc_p->ddr_2v5_compensation);
ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
ddr1v8 &= 0x8080ffc0;
ddr1v8 |= 0x78000010;
writel(ddr1v8, &misc_p->ddr_1v8_compensation);
while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
;
}
static void sel_2v5(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 ddr1v8, ddr2v5;
ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
ddr1v8 &= 0x8080ffc0;
ddr1v8 |= 0x78000003;
writel(ddr1v8, &misc_p->ddr_1v8_compensation);
ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
ddr2v5 &= 0x8080ffc0;
ddr2v5 |= 0x78000010;
writel(ddr2v5, &misc_p->ddr_2v5_compensation);
while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
;
}
/*
* plat_ddr_init:
*/
void plat_ddr_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 ddrpad;
u32 core3v3, ddr1v8, ddr2v5;
/* DDR pad register configurations */
ddrpad = readl(&misc_p->ddr_pad);
ddrpad &= ~DDR_PAD_CNF_MSK;
#if (CONFIG_DDR_HCLK)
ddrpad |= 0xEAAB;
#elif (CONFIG_DDR_2HCLK)
ddrpad |= 0xEAAD;
#elif (CONFIG_DDR_PLL2)
ddrpad |= 0xEAAD;
#endif
writel(ddrpad, &misc_p->ddr_pad);
/* Compensation register configurations */
core3v3 = readl(&misc_p->core_3v3_compensation);
core3v3 &= 0x8080ffe0;
core3v3 |= 0x78000002;
writel(core3v3, &misc_p->core_3v3_compensation);
ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
ddr1v8 &= 0x8080ffc0;
ddr1v8 |= 0x78000004;
writel(ddr1v8, &misc_p->ddr_1v8_compensation);
ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
ddr2v5 &= 0x8080ffc0;
ddr2v5 |= 0x78000004;
writel(ddr2v5, &misc_p->ddr_2v5_compensation);
if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
/* Software memory configuration */
if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
sel_1v8();
else
sel_2v5();
} else {
/* Hardware memory configuration */
if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
sel_1v8();
else
sel_2v5();
}
}
/*
* soc_init:
*/
void soc_init(void)
{
/* Nothing to be done for SPEAr600 */
}
/*
* xxx_boot_selected:
*
* return TRUE if the particular booting option is selected
* return FALSE otherwise
*/
static u32 read_bootstrap(void)
{
return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
& CONFIG_SPEAR_BOOTSTRAPMASK;
}
int snor_boot_selected(void)
{
u32 bootstrap = read_bootstrap();
if (SNOR_BOOT_SUPPORTED) {
/* Check whether SNOR boot is selected */
if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
CONFIG_SPEAR_ONLYSNORBOOT)
return TRUE;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
return TRUE;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
return TRUE;
}
return FALSE;
}
int nand_boot_selected(void)
{
u32 bootstrap = read_bootstrap();
if (NAND_BOOT_SUPPORTED) {
/* Check whether NAND boot is selected */
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
return TRUE;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
return TRUE;
}
return FALSE;
}
int pnor_boot_selected(void)
{
/* Parallel NOR boot is not selected in any SPEAr600 revision */
return FALSE;
}
int usb_boot_selected(void)
{
u32 bootstrap = read_bootstrap();
if (USB_BOOT_SUPPORTED) {
/* Check whether USB boot is selected */
if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
return TRUE;
}
return FALSE;
}
int tftp_boot_selected(void)
{
/* TFTP boot is not selected in any SPEAr600 revision */
return FALSE;
}
int uart_boot_selected(void)
{
/* UART boot is not selected in any SPEAr600 revision */
return FALSE;
}
int spi_boot_selected(void)
{
/* SPI boot is not selected in any SPEAr600 revision */
return FALSE;
}
int i2c_boot_selected(void)
{
/* I2C boot is not selected in any SPEAr600 revision */
return FALSE;
}
int mmc_boot_selected(void)
{
return FALSE;
}
void plat_late_init(void)
{
spear_late_init();
}

282
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/*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_syscntl.h>
inline void hang(void)
{
serial_puts("### ERROR ### Please RESET the board ###\n");
for (;;)
;
}
static void ddr_clock_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 clkenb, ddrpll;
clkenb = readl(&misc_p->periph1_clken);
clkenb &= ~PERIPH_MPMCMSK;
clkenb |= PERIPH_MPMC_WE;
/* Intentionally done twice */
writel(clkenb, &misc_p->periph1_clken);
writel(clkenb, &misc_p->periph1_clken);
ddrpll = readl(&misc_p->pll_ctr_reg);
ddrpll &= ~MEM_CLK_SEL_MSK;
#if (CONFIG_DDR_HCLK)
ddrpll |= MEM_CLK_HCLK;
#elif (CONFIG_DDR_2HCLK)
ddrpll |= MEM_CLK_2HCLK;
#elif (CONFIG_DDR_PLL2)
ddrpll |= MEM_CLK_PLL2;
#else
#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
#endif
writel(ddrpll, &misc_p->pll_ctr_reg);
writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
&misc_p->periph1_clken);
}
static void mpmc_init_values(void)
{
u32 i;
u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
u32 *mpmc_val_p = &mpmc_conf_vals[0];
for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
writel(*mpmc_val_p, mpmc_reg_p);
mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
/*
* MPMC controller start
* MPMC waiting for DLLLOCKREG high
*/
writel(0x01000100, &mpmc_reg_p[7]);
while (!(readl(&mpmc_reg_p[3]) & 0x10000))
;
}
static void mpmc_init(void)
{
/* Clock related settings for DDR */
ddr_clock_init();
/*
* DDR pad register bits are different for different SoCs
* Compensation values are also handled separately
*/
plat_ddr_init();
/* Initialize mpmc register values */
mpmc_init_values();
}
static void pll_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
/* Initialize PLLs */
writel(FREQ_332, &misc_p->pll1_frq);
writel(0x1C0A, &misc_p->pll1_cntl);
writel(0x1C0E, &misc_p->pll1_cntl);
writel(0x1C06, &misc_p->pll1_cntl);
writel(0x1C0E, &misc_p->pll1_cntl);
writel(FREQ_332, &misc_p->pll2_frq);
writel(0x1C0A, &misc_p->pll2_cntl);
writel(0x1C0E, &misc_p->pll2_cntl);
writel(0x1C06, &misc_p->pll2_cntl);
writel(0x1C0E, &misc_p->pll2_cntl);
/* wait for pll locks */
while (!(readl(&misc_p->pll1_cntl) & 0x1))
;
while (!(readl(&misc_p->pll2_cntl) & 0x1))
;
}
static void mac_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
&misc_p->periph1_clken);
writel(SYNTH23, &misc_p->gmac_synth_clk);
switch (get_socrev()) {
case SOC_SPEAR600_AA:
case SOC_SPEAR600_AB:
case SOC_SPEAR600_BA:
case SOC_SPEAR600_BB:
case SOC_SPEAR600_BC:
case SOC_SPEAR600_BD:
writel(0x0, &misc_p->gmac_ctr_reg);
break;
case SOC_SPEAR300:
case SOC_SPEAR310:
case SOC_SPEAR320:
writel(0x4, &misc_p->gmac_ctr_reg);
break;
}
writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
&misc_p->periph1_clken);
writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
&misc_p->periph1_rst);
writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
&misc_p->periph1_rst);
}
static void sys_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
struct syscntl_regs *syscntl_p =
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
/* Set system state to SLOW */
writel(SLOW, &syscntl_p->scctrl);
writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
/* Initialize PLLs */
pll_init();
/*
* Ethernet configuration
* To be done only if the tftp boot is not selected already
* Boot code ensures the correct configuration in tftp booting
*/
if (!tftp_boot_selected())
mac_init();
writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
writel(0x555, &misc_p->amba_clk_cfg);
writel(NORMAL, &syscntl_p->scctrl);
/* Wait for system to switch to normal mode */
while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
!= NORMAL)
;
}
/*
* get_socrev
*
* Get SoC Revision.
* @return SOC_SPEARXXX
*/
int get_socrev(void)
{
#if defined(CONFIG_SPEAR600)
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 soc_id = readl(&misc_p->soc_core_id);
u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
if ((pri_socid == 'B') && (sec_socid == 'B'))
return SOC_SPEAR600_BB;
else if ((pri_socid == 'B') && (sec_socid == 'C'))
return SOC_SPEAR600_BC;
else if ((pri_socid == 'B') && (sec_socid == 'D'))
return SOC_SPEAR600_BD;
else if (soc_id == 0)
return SOC_SPEAR600_BA;
else
return SOC_SPEAR_NA;
#elif defined(CONFIG_SPEAR300)
return SOC_SPEAR300;
#elif defined(CONFIG_SPEAR310)
return SOC_SPEAR310;
#elif defined(CONFIG_SPEAR320)
return SOC_SPEAR320;
#endif
}
void lowlevel_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
const char *u_boot_rev = U_BOOT_VERSION;
/* Initialize PLLs */
sys_init();
/* Initialize UART */
serial_init();
/* Print U-Boot SPL version string */
serial_puts("\nU-Boot SPL ");
/* Avoid a second "U-Boot" coming from this string */
u_boot_rev = &u_boot_rev[7];
serial_puts(u_boot_rev);
serial_puts(" (");
serial_puts(U_BOOT_DATE);
serial_puts(" - ");
serial_puts(U_BOOT_TIME);
serial_puts(")\n");
#if defined(CONFIG_OS_BOOT)
writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
&misc_p->periph1_clken);
#endif
/* Enable IPs (release reset) */
writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
/* Initialize MPMC */
serial_puts("Configure DDR\n");
mpmc_init();
/* SoC specific initialization */
soc_init();
}
void spear_late_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
writel(0x80000007, &misc_p->arb_icm_ml1);
writel(0x80000007, &misc_p->arb_icm_ml2);
writel(0x80000007, &misc_p->arb_icm_ml3);
writel(0x80000007, &misc_p->arb_icm_ml4);
writel(0x80000007, &misc_p->arb_icm_ml5);
writel(0x80000007, &misc_p->arb_icm_ml6);
writel(0x80000007, &misc_p->arb_icm_ml7);
writel(0x80000007, &misc_p->arb_icm_ml8);
writel(0x80000007, &misc_p->arb_icm_ml9);
}

197
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/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <image.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/spr_defs.h>
#include <linux/mtd/st_smi.h>
static const char kernel_name[] = "Linux";
static const char loader_name[] = "U-Boot";
int image_check_header(image_header_t *hdr, const char *name)
{
if (image_check_magic(hdr) &&
(!strncmp(image_get_name(hdr), name, strlen(name))) &&
image_check_hcrc(hdr)) {
return 1;
}
return 0;
}
int image_check_data(image_header_t *hdr)
{
if (image_check_dcrc(hdr))
return 1;
return 0;
}
/*
* SNOR (Serial NOR flash) related functions
*/
void snor_init(void)
{
struct smi_regs *const smicntl =
(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
&smicntl->smi_cr1);
}
static int snor_image_load(u8 *load_addr, void (**image_p)(void),
const char *image_name)
{
image_header_t *header;
/*
* Since calculating the crc in the SNOR flash does not
* work, we copy the image to the destination address
* minus the header size. And point the header to this
* new destination. This will not work for address 0
* of course.
*/
header = (image_header_t *)load_addr;
memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
(const ulong *)load_addr,
image_get_data_size(header) + sizeof(image_header_t));
header = (image_header_t *)(image_get_load(header) -
sizeof(image_header_t));
if (image_check_header(header, image_name)) {
if (image_check_data(header)) {
/* Jump to boot image */
*image_p = (void *)image_get_load(header);
return 1;
}
}
return 0;
}
static void boot_image(void (*image)(void))
{
void (*funcp)(void) __noreturn = (void *)image;
(*funcp)();
}
/*
* spl_boot:
*
* All supported booting types of all supported SoCs are listed here.
* Generic readback APIs are provided for each supported booting type
* eg. nand_read_skip_bad
*/
u32 spl_boot(void)
{
void (*image)(void);
#ifdef CONFIG_SPEAR_USBTTY
plat_late_init();
return 1;
#endif
/*
* All the supported booting devices are listed here. Each of
* the booting type supported by the platform would define the
* macro xxx_BOOT_SUPPORTED to TRUE.
*/
if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
/* SNOR-SMI initialization */
snor_init();
serial_puts("Booting via SNOR\n");
/* Serial NOR booting */
if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
&image, loader_name)) {
/* Platform related late initialasations */
plat_late_init();
/* Jump to boot image */
serial_puts("Jumping to U-Boot\n");
boot_image(image);
return 1;
}
}
if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
/* NAND booting */
/* Not ported from XLoader to SPL yet */
return 0;
}
if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
/* PNOR booting */
/* Not ported from XLoader to SPL yet */
return 0;
}
if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
/* MMC booting */
/* Not ported from XLoader to SPL yet */
return 0;
}
if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
/* SPI booting */
/* Not supported for any platform as of now */
return 0;
}
if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
/* I2C booting */
/* Not supported for any platform as of now */
return 0;
}
/*
* All booting types without memory are listed as below
* Control has to be returned to BootROM in case of all
* the following booting scenarios
*/
if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
plat_late_init();
return 1;
}
if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
plat_late_init();
return 1;
}
if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
plat_late_init();
return 1;
}
/* Ideally, the control should not reach here. */
hang();
}

130
arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c Normal file
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/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_DDR_PLL2)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
0x00000001,
0x00000000,
0x01000000,
0x00000101,
0x00000001,
0x01000000,
0x00010001,
0x00000100,
0x00010001,
0x00000003,
0x01000201,
0x06000202,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
0x02010106,
0x03000404,
0x02030202,
0x03000204,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x08080a01,
0x0000023f,
0x00040800,
0x00000000,
0x00000f02,
0x00001b1b,
0x7f000000,
0x005f0000,
0x1c040b6a,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x000007ff,
0x00000000,
0x47ec00c8,
0x00c8001f,
0x00000000,
0x0000cd98,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00270000,
0x00250027,
0x00300000,
0x008900b7,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif

135
arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c Normal file
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/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
#if (CONFIG_DDR_PLL2)
0x00000001,
0x00000000,
#elif (CONFIG_DDR_2HCLK)
0x02020201,
0x02020202,
#endif
0x01000000,
0x00000101,
0x00000101,
0x01000000,
0x00010001,
0x00000100,
0x01010001,
0x00000201,
0x01000101,
0x06000002,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
0x02010106,
0x03000405,
0x03040202,
0x04000305,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x0a0a0a01,
0x0000023f,
0x00050a00,
0x11000000,
0x00001302,
0x00000A0A,
0x72000000,
0x00550000,
0x2b050e86,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00000a24,
0x43C20000,
0x5b1c00c8,
0x00c8002e,
0x00000000,
0x0001046b,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00210000,
0x00010021,
0x00200000,
0x006c0090,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif

130
arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c Normal file
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/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_DDR_HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
0x03030301,
0x03030303,
0x01000000,
0x00000101,
0x00000001,
0x01000000,
0x00010001,
0x00000100,
0x00010001,
0x00000003,
0x01000201,
0x06000202,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
0x02010106,
0x03000404,
0x02020202,
0x03000203,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x08080a01,
0x0000023f,
0x00030600,
0x00000000,
0x00000a02,
0x00001c1c,
0x7f000000,
0x005f0000,
0x12030743,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x0000050e,
0x00000000,
0x2d8900c8,
0x00c80014,
0x00000000,
0x00008236,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00400000,
0x003a0040,
0x00680000,
0x00d80120,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif

144
arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c Normal file
View file

@ -0,0 +1,144 @@
/*
* (C) Copyright 2000-2009
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
#if (CONFIG_DDR_PLL2)
0x00000001,
0x00000000,
#elif (CONFIG_DDR_2HCLK)
0x02020201,
0x02020202,
#endif
0x01000000,
0x00000101,
0x00000101,
0x01000000,
0x00010001,
0x00000100,
0x01010001,
0x00000201,
0x01000101,
0x06000002,
0x06060106,
0x03050502,
0x03040404,
0x02020503,
#ifdef CONFIG_X600
0x02030206,
#else
0x02010106,
#endif
0x03000405,
0x03040202,
0x04000305,
0x0707073f,
0x07070707,
0x06060607,
0x06060606,
0x05050506,
0x05050505,
0x04040405,
0x04040404,
0x03030304,
0x03030303,
0x02020203,
0x02020202,
0x01010102,
0x01010101,
0x0a0a0a01,
0x0000023f,
0x00050a00,
0x11000000,
0x00001302,
0x00000A0A,
#ifdef CONFIG_X600
0x7f000000,
0x005c0000,
#else
0x72000000,
0x00550000,
#endif
0x2b050e86,
0x00640064,
0x00640064,
0x00640064,
0x00000064,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00200020,
0x00000a24,
0x43C20000,
0x5b1c00c8,
0x00c8002e,
0x00000000,
0x0001046b,
0x00000000,
0x03030100,
0x03030303,
0x03030303,
0x03030303,
0x00210000,
0x00010021,
0x00200000,
0x006c0090,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x003fffff,
0x003fffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};
#endif

122
arch/arm/cpu/arm926ejs/spear/start.S Normal file
View file

@ -0,0 +1,122 @@
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
.globl _start
_start:
b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
_software_interrupt:
_prefetch_abort:
_data_abort:
_not_used:
_irq:
_fiq:
.word infinite_loop
infinite_loop:
b infinite_loop
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* Below are the critical initializations already taken place in BootROM.
* So, these are not taken care in Xloader
* 1. Relocation to RAM
* 2. Initializing stacks
*
*************************************************************************
*/
/*
* the actual reset code
*/
reset:
/*
* Xloader has to return back to BootROM in a few cases.
* eg. Ethernet boot, UART boot, USB boot
* Saving registers for returning back
*/
stmdb sp!, {r0-r12,r14}
bl cpu_init_crit
/*
* Clearing bss area is not done in Xloader.
* BSS area lies in the DDR location which is not yet initialized
* bss is assumed to be uninitialized.
*/
bl spl_boot
ldmia sp!, {r0-r12,pc}
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* enable instruction cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
/*
* Go setup Memory and board specific bits prior to relocation.
*/
stmdb sp!, {lr}
bl lowlevel_init /* go setup pll,mux,memory */
ldmia sp!, {pc}

87
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds Normal file
View file

@ -0,0 +1,87 @@
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
arch/arm/cpu/arm926ejs/spear/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data)
}
. = ALIGN(4);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.dynsym : {
__dynsym_start = .;
*(.dynsym)
}
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end__ = .;
}
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynsym*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.hash*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

30
arch/arm/cpu/armv7/am33xx/board.c
View file

@ -40,6 +40,22 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#endif
#ifdef CONFIG_SPL_BUILD
/* Initialize timer */
static void init_timer(void)
{
/* Reset the Timer */
writel(0x2, (&timer_base->tscir));
/* Wait until the reset is done */
while (readl(&timer_base->tiocp_cfg) & 1)
;
/* Start the Timer */
writel(0x1, (&timer_base->tclr));
}
#endif
/*
* early system init of muxing and clocks.
*/
@ -88,20 +104,6 @@ void s_init(void)
enable_mmc0_pin_mux();
}
/* Initialize timer */
void init_timer(void)
{
/* Reset the Timer */
writel(0x2, (&timer_base->tscir));
/* Wait until the reset is done */
while (readl(&timer_base->tiocp_cfg) & 1)
;
/* Start the Timer */
writel(0x1, (&timer_base->tclr));
}
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{

8
arch/arm/cpu/armv7/cpu.c
View file

@ -36,9 +36,15 @@
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <linux/compiler.h>
void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
void __naked save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
{
/*
* Stack pointer is not yet initialized
* Don't save anything to stack even if compiled with -O0
*/
asm("bx lr");
}
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)

2
arch/arm/cpu/armv7/exynos/Makefile
View file

@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS += clock.o power.o soc.o system.o
COBJS += clock.o power.o soc.o system.o pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

220
arch/arm/cpu/armv7/exynos/pinmux.c Normal file
View file

@ -0,0 +1,220 @@
/*
* Copyright (c) 2012 Samsung Electronics.
* Abhilash Kesavan <a.kesavan@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
static void exynos5_uart_config(int peripheral)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
count = 2;
break;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
int i;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
break;
case PERIPH_ID_SDMMC1:
bank = &gpio1->c1;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio1->c2;
bank_ext = &gpio1->c3;
break;
case PERIPH_ID_SDMMC3:
bank = &gpio1->c3;
bank_ext = NULL;
break;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
return 0;
}
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
/*
* SROM:CS1 and EBI
*
* GPY0[0] SROM_CSn[0]
* GPY0[1] SROM_CSn[1](2)
* GPY0[2] SROM_CSn[2]
* GPY0[3] SROM_CSn[3]
* GPY0[4] EBI_OEn(2)
* GPY0[5] EBI_EEn(2)
*
* GPY1[0] EBI_BEn[0](2)
* GPY1[1] EBI_BEn[1](2)
* GPY1[2] SROM_WAIT(2)
* GPY1[3] EBI_DATA_RDn(2)
*/
s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
for (i = 0; i < 4; i++)
s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
*
* GPY3[0] EBI_ADDR[0](2)
* GPY3[1] EBI_ADDR[1](2)
* GPY3[2] EBI_ADDR[2](2)
* GPY3[3] EBI_ADDR[3](2)
* GPY3[4] EBI_ADDR[4](2)
* GPY3[5] EBI_ADDR[5](2)
* GPY3[6] EBI_ADDR[6](2)
* GPY3[7] EBI_ADDR[7](2)
*
* EBI: 16 Data Lines
*
* GPY5[0] EBI_DATA[0](2)
* GPY5[1] EBI_DATA[1](2)
* GPY5[2] EBI_DATA[2](2)
* GPY5[3] EBI_DATA[3](2)
* GPY5[4] EBI_DATA[4](2)
* GPY5[5] EBI_DATA[5](2)
* GPY5[6] EBI_DATA[6](2)
* GPY5[7] EBI_DATA[7](2)
*
* GPY6[0] EBI_DATA[8](2)
* GPY6[1] EBI_DATA[9](2)
* GPY6[2] EBI_DATA[10](2)
* GPY6[3] EBI_DATA[11](2)
* GPY6[4] EBI_DATA[12](2)
* GPY6[5] EBI_DATA[13](2)
* GPY6[6] EBI_DATA[14](2)
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
}
}
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
exynos5_uart_config(peripheral);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
return exynos5_mmc_config(peripheral, flags);
case PERIPH_ID_SROMC:
exynos5_sromc_config(flags);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
return 0;
}
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5())
return exynos5_pinmux_config(peripheral, flags);
else {
debug("pinmux functionality not supported\n");
return -1;
}
}

4
arch/arm/cpu/armv7/imx-common/speed.c
View file

@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_USDHC
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#else
gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
#endif
#endif
return 0;
}

2
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -843,7 +843,7 @@ void mxc_set_sata_internal_clock(void)
set_usb_phy1_clk();
writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
}
#endif

2
arch/arm/cpu/armv7/mx6/soc.c
View file

@ -43,7 +43,6 @@ u32 get_cpu_rev(void)
return system_rev;
}
#ifdef CONFIG_ARCH_CPU_INIT
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
@ -113,7 +112,6 @@ int arch_cpu_init(void)
return 0;
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)

8
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -299,8 +299,12 @@ static void setup_dplls(void)
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
"core");
if (omap_revision() != OMAP5432_ES1_0)
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |

189
arch/arm/cpu/armv7/omap-common/emif-common.c
View file

@ -31,6 +31,28 @@
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
#include <linux/compiler.h>
void set_lpmode_selfrefresh(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 reg;
reg = readl(&emif->emif_pwr_mgmt_ctrl);
reg &= ~EMIF_REG_LP_MODE_MASK;
reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
reg &= ~EMIF_REG_SR_TIM_MASK;
writel(reg, &emif->emif_pwr_mgmt_ctrl);
/* dummy read for the new SR_TIM to be loaded */
readl(&emif->emif_pwr_mgmt_ctrl);
}
void force_emif_self_refresh()
{
set_lpmode_selfrefresh(EMIF1_BASE);
set_lpmode_selfrefresh(EMIF2_BASE);
}
inline u32 emif_num(u32 base)
{
@ -56,7 +78,12 @@ static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
mr = readl(&emif->emif_lpddr2_mode_reg_data);
debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
cs, mr_addr, mr);
return mr;
if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
((mr & 0xff000000) >> 24) == (mr & 0xff))
return mr & 0xff;
else
return mr;
}
static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
@ -114,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs)
static void lpddr2_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
u32 i = 0;
/* Not NVM */
clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@ -134,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
if (omap_revision() >= OMAP5430_ES1_0) {
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
*/
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
}
}
do_ext_phy_settings(base, regs);
do_lpddr2_init(base, CS0);
if (regs->sdram_config & EMIF_REG_EBANK_MASK)
@ -168,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
/* Enable refresh now */
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
}
__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
}
void emif_update_timings(u32 base, const struct emif_regs *regs)
@ -190,7 +196,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
if (omap_revision() == OMAP5430_ES1_0) {
if (omap_revision() >= OMAP5430_ES1_0) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
&emif->emif_l3_config);
} else if (omap_revision() >= OMAP4460_ES1_0) {
@ -202,6 +208,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
}
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
/* keep sdram in self-refresh */
writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
__udelay(130);
/*
* Set invert_clkout (if activated)--DDR_PHYCTRL_1
* Invert clock adds an additional half cycle delay on the command
* interface. The additional half cycle, is usually meant to enable
* leveling in the situation that DQS is later than CK on the board.It
* also helps provide some additional margin for leveling.
*/
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
__udelay(130);
writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
/* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Launch Incremental leveling */
writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
__udelay(130);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
/* Update timing registers */
writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
*/
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ddr3_ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ddr3_ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
}
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
@ -826,7 +927,7 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
}
mr = get_mr(base, cs, LPDDR2_MR5);
if (mr >= 0xFF) {
if (mr > 0xFF) {
/* Mode register value bigger than 8 bit */
return 0;
}
@ -895,7 +996,7 @@ struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
return NULL;
/* Do the minimum init for mode register accesses */
if (!running_from_sdram()) {
if (!(running_from_sdram() || warm_reset())) {
phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
writel(phy, &emif->emif_ddr_phy_ctrl_1);
}
@ -975,8 +1076,12 @@ static void do_sdram_init(u32 base)
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
if (!in_sdram)
lpddr2_init(base, regs);
if (!(in_sdram || warm_reset())) {
if (omap_revision() != OMAP5432_ES1_0)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
}
/* Write to the shadow registers */
emif_update_timings(base, regs);
@ -1133,6 +1238,7 @@ void dmm_init(u32 base)
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
u32 omap_rev = omap_revision();
debug(">>sdram_init()\n");
@ -1142,25 +1248,34 @@ void sdram_init(void)
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
if (!in_sdram)
bypass_dpll(&prcm->cm_clkmode_dpll_core);
if (!(in_sdram || warm_reset())) {
if (omap_rev != OMAP5432_ES1_0)
bypass_dpll(&prcm->cm_clkmode_dpll_core);
else
writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
}
do_sdram_init(EMIF1_BASE);
do_sdram_init(EMIF2_BASE);
if (!in_sdram) {
if (!in_sdram)
dmm_init(DMM_BASE);
if (!(in_sdram || warm_reset())) {
emif_post_init_config(EMIF1_BASE);
emif_post_init_config(EMIF2_BASE);
}
/* for the shadow registers to take effect */
freq_update_core();
if (omap_rev != OMAP5432_ES1_0)
freq_update_core();
/* Do some testing after the init */
if (!in_sdram) {
size_prog = omap_sdram_size();
size_prog = log_2_n_round_down(size_prog);
size_prog = (1 << size_prog);
size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
size_prog);
/* Compare with the size programmed */

24
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View file

@ -111,6 +111,10 @@ static void init_boot_params(void)
void s_init(void)
{
init_omap_revision();
#ifdef CONFIG_SPL_BUILD
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
force_emif_self_refresh();
#endif
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
@ -162,11 +166,16 @@ void watchdog_init(void)
*/
u32 omap_sdram_size(void)
{
u32 section, i, total_size = 0, size, addr;
u32 section, i, valid;
u64 sdram_start = 0, sdram_end = 0, addr,
size, total_size = 0, trap_size = 0;
for (i = 0; i < 4; i++) {
section = __raw_readl(DMM_BASE + i*4);
valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
(EMIF_SDRC_ADDRSPC_SHIFT);
addr = section & EMIF_SYS_ADDR_MASK;
/* See if the address is valid */
if ((addr >= DRAM_ADDR_SPACE_START) &&
(addr < DRAM_ADDR_SPACE_END)) {
@ -174,9 +183,20 @@ u32 omap_sdram_size(void)
EMIF_SYS_SIZE_SHIFT);
size = 1 << size;
size *= SZ_16M;
total_size += size;
if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
if (!sdram_start || (addr < sdram_start))
sdram_start = addr;
if (!sdram_end || ((addr + size) > sdram_end))
sdram_end = addr + size;
} else {
trap_size = size;
}
}
}
total_size = (sdram_end - sdram_start) - (trap_size);
return total_size;
}

5
arch/arm/cpu/armv7/omap-common/reset.c
View file

@ -34,3 +34,8 @@ void __weak reset_cpu(unsigned long ignored)
{
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
}
u32 __weak warm_reset(void)
{
return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
}

14
arch/arm/cpu/armv7/omap4/clocks.c
View file

@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
{291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
@ -354,6 +354,7 @@ void enable_basic_clocks(void)
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
@ -363,9 +364,6 @@ void enable_basic_clocks(void)
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_clksel_usb_60mhz,
&prcm->cm_l3init_hsusbtll_clkctrl,
0
};
@ -376,7 +374,6 @@ void enable_basic_clocks(void)
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
0
};
@ -413,6 +410,9 @@ void enable_basic_uboot_clocks(void)
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_clksel_usb_60mhz,
&prcm->cm_l3init_hsusbtll_clkctrl,
0
};
@ -422,6 +422,7 @@ void enable_basic_uboot_clocks(void)
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
0
};
@ -452,12 +453,10 @@ void enable_non_essential_clocks(void)
};
u32 *const clk_modules_hw_auto_non_essential[] = {
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
&prcm->cm_l3init_hsusbtll_clkctrl,
0
};
@ -497,7 +496,6 @@ void enable_non_essential_clocks(void)
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
0
};

5
arch/arm/cpu/armv7/omap4/hwinit.c
View file

@ -118,6 +118,11 @@ void do_io_settings(void)
}
#endif
/* dummy fuction for omap4 */
void config_data_eye_leveling_samples(u32 emif_base)
{
}
void init_omap_revision(void)
{
/*

2
arch/arm/cpu/armv7/omap4/sdram_elpida.c
View file

@ -91,7 +91,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
};
/* Dummy registers for OMAP44xx */
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,

35
arch/arm/cpu/armv7/omap5/clocks.c
View file

@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void)
*/
void scale_vcores(void)
{
u32 volt;
u32 volt_core, volt_mpu, volt_mm;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
/* Palmas settings */
volt = VDD_CORE;
do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
if (omap_revision() != OMAP5432_ES1_0) {
volt_core = VDD_CORE;
volt_mpu = VDD_MPU;
volt_mm = VDD_MM;
} else {
volt_core = VDD_CORE_5432;
volt_mpu = VDD_MPU_5432;
volt_mm = VDD_MM_5432;
}
volt = VDD_MPU;
do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
volt = VDD_MM;
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
if (omap_revision() == OMAP5432_ES1_0) {
/* Configure LDO SRAM "magic" bits */
writel(2, &prcm->prm_sldo_core_setup);
writel(2, &prcm->prm_sldo_mpu_setup);
writel(2, &prcm->prm_sldo_mm_setup);
}
}
u32 get_offset_code(u32 volt_offset)
@ -306,6 +317,7 @@ void enable_basic_clocks(void)
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
@ -382,6 +394,9 @@ void enable_basic_uboot_clocks(void)
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l3init_hsusbtll_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
&prcm->cm_l3init_fsusb_clkctrl,
0
};
@ -416,12 +431,10 @@ void enable_non_essential_clocks(void)
&prcm->cm_ivahd_ivahd_clkctrl,
&prcm->cm_ivahd_sl2_clkctrl,
&prcm->cm_dsp_dsp_clkctrl,
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
&prcm->cm_l3init_hsusbtll_clkctrl,
&prcm->cm_l4per_hdq1w_clkctrl,
0
};
@ -460,8 +473,6 @@ void enable_non_essential_clocks(void)
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
&prcm->cm_l3init_fsusb_clkctrl,
0
};

123
arch/arm/cpu/armv7/omap5/hwinit.c
View file

@ -35,6 +35,7 @@
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@ -52,6 +53,81 @@ static struct gpio_bank gpio_bank_54xx[6] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_1));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_1));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_1));
writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
&(ioregs_base->control_ddrio_0));
writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
&(ioregs_base->control_ddrio_1));
writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
&(ioregs_base->control_ddrio_2));
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddr3ch1_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch1_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch1_1));
writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddr3ch2_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch2_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch2_1));
writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_0));
writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_1));
writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_2));
/* omap5432 does not use lpddr2 */
writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
&(ioregs_base->control_emif1_sdram_config_ext));
writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
&(ioregs_base->control_emif2_sdram_config_ext));
/* Disable DLL select */
io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
& 0xFFEFFFFF);
writel(io_settings,
&(ioregs_base->control_port_emif1_sdram_config));
io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
& 0xFFEFFFFF);
writel(io_settings,
&(ioregs_base->control_port_emif2_sdram_config));
}
/*
* Some tuning of IOs for optimal power and performance
*/
@ -115,25 +191,10 @@ void do_io_settings(void)
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
/* LPDDR2 io settings */
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_1));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_1));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_1));
writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
&(ioregs_base->control_ddrio_0));
writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
&(ioregs_base->control_ddrio_1));
writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
&(ioregs_base->control_ddrio_2));
if (omap_revision() <= OMAP5430_ES1_0)
io_settings_lpddr2();
else
io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, &(ioregs_base->control_efuse_1));
@ -143,6 +204,20 @@ void do_io_settings(void)
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
&(ioregs_base->control_emif1_sdram_config_ext));
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
&(ioregs_base->control_emif2_sdram_config_ext));
}
void init_omap_revision(void)
{
/*
@ -154,7 +229,15 @@ void init_omap_revision(void)
switch (rev) {
case MIDR_CORTEX_A15_R0P0:
*omap_si_rev = OMAP5430_ES1_0;
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5430_ES1_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES1_0:
default:
*omap_si_rev = OMAP5432_ES1_0;
break;
}
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;

87
arch/arm/cpu/armv7/omap5/sdram.c
View file

@ -86,11 +86,34 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0020420A,
.emif_ddr_phy_ctlr_1 = 0x0024420A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
.emif_ddr_ext_phy_ctrl_5 = 0x04010040,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80740300
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100
};
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000077
};
const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000002,
0x0,
0x0,
0x0,
0x00000000,
0x00000000,
0x00000000,
0x00000057
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
*regs = &emif_regs_532_mhz_2cs;
if (omap_revision() == OMAP5432_ES1_0)
*regs = &emif_regs_ddr3_532_mhz_1cs;
else
*regs = &emif_regs_532_mhz_2cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
@ -156,6 +204,37 @@ void emif_get_device_details(u32 emif_nr,
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
u32 i = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
*/
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
}
}
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,

5
arch/arm/cpu/armv7/s5p-common/cpu_info.c
View file

@ -48,8 +48,9 @@ int print_cpuinfo(void)
{
char buf[32];
printf("CPU:\tS5P%X@%sMHz\n",
s5p_cpu_id, strmhz(buf, get_arm_clk()));
printf("CPU:\t%s%X@%sMHz\n",
s5p_get_cpu_name(), s5p_cpu_id,
strmhz(buf, get_arm_clk()));
return 0;
}

12
arch/arm/cpu/armv7/start.S
View file

@ -277,6 +277,18 @@ jump_2_ram:
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
#endif
/*
* Move vector table
*/
#if !defined(CONFIG_TEGRA2)
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
add r0, r0, r9
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
#endif /* !Tegra2 */
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1

28
arch/arm/cpu/armv7/tegra2/ap20.c
View file

@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void)
void init_pllx(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll_simple *pll =
&clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
u32 reg;
/* If PLLX is already enabled, just return */
@ -312,9 +314,28 @@ void enable_scu(void)
writel(reg, &scu->scu_ctrl);
}
static u32 get_odmdata(void)
{
/*
* ODMDATA is stored in the BCT in IRAM by the BootROM.
* The BCT start and size are stored in the BIT in IRAM.
* Read the data @ bct_start + (bct_size - 12). This works
* on T20 and T30 BCTs, which are locked down. If this changes
* in new chips (T114, etc.), we can revisit this algorithm.
*/
u32 bct_start, odmdata;
bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
}
void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
u32 odmdata;
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@ -322,7 +343,8 @@ void init_pmc_scratch(void)
writel(0, &pmc->pmc_scratch1+i);
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
odmdata = get_odmdata();
writel(odmdata, &pmc->pmc_scratch20);
#ifdef CONFIG_TEGRA2_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */

18
arch/arm/cpu/armv7/tegra2/board.c
View file

@ -101,6 +101,22 @@ int arch_cpu_init(void)
}
#endif
static int uart_configs[] = {
#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
#elif defined(CONFIG_TEGRA2_UARTA_GPU)
FUNCMUX_UART1_GPU,
#elif defined(CONFIG_TEGRA2_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
#else
FUNCMUX_UART1_IRRX_IRTX,
#endif
FUNCMUX_UART2_IRDA,
-1,
FUNCMUX_UART4_GMC,
-1,
};
/**
* Set up the specified uarts
*
@ -120,7 +136,7 @@ static void setup_uarts(int uart_ids)
if (uart_ids & (1 << i)) {
enum periph_id id = id_for_uart[i];
funcmux_select(id, FUNCMUX_DEFAULT);
funcmux_select(id, uart_configs[i]);
clock_ll_start_uart(id);
}
}

4
arch/arm/cpu/armv7/tegra2/clock.c
View file

@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
assert(clock_id_isvalid(clkid));
assert(clock_id_is_pll(clkid));
return &clkrst->crc_pll[clkid];
}
@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
assert(clkid != CLOCK_ID_USB);
/* Safety check, adds to code size but is small */
if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
return -1;
data = readl(&pll->pll_base);
*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;

7
arch/arm/cpu/armv7/tegra2/config.mk
View file

@ -24,10 +24,13 @@
# MA 02111-1307 USA
#
# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this
# file with compatible flags
# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these
# files with compatible flags
ifdef CONFIG_TEGRA2
CFLAGS_arch/arm/lib/board.o += -march=armv4t
CFLAGS_arch/arm/lib/memset.o += -march=armv4t
CFLAGS_lib/string.o += -march=armv4t
CFLAGS_common/cmd_nvedit.o += -march=armv4t
endif
USE_PRIVATE_LIBGCC = yes

30
arch/arm/cpu/armv7/tegra2/funcmux.c
View file

@ -31,11 +31,32 @@ int funcmux_select(enum periph_id id, int config)
switch (id) {
case PERIPH_ID_UART1:
if (config == FUNCMUX_UART1_IRRX_IRTX) {
switch (config) {
case FUNCMUX_UART1_IRRX_IRTX:
pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PINGRP_IRTX);
break;
case FUNCMUX_UART1_UAA_UAB:
pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_UAA);
pinmux_tristate_disable(PINGRP_UAB);
bad_config = 0;
break;
case FUNCMUX_UART1_GPU:
pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_GPU);
bad_config = 0;
break;
case FUNCMUX_UART1_SDIO1:
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_SDIO1);
bad_config = 0;
break;
}
if (!bad_config) {
/*
* Tegra appears to boot with function UARTA pre-
* selected on mux group SDB. If two mux groups are
@ -106,6 +127,13 @@ int funcmux_select(enum periph_id id, int config)
}
break;
case PERIPH_ID_SDMMC1:
if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_tristate_disable(PINGRP_SDIO1);
}
break;
case PERIPH_ID_SDMMC2:
if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);

10
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
View file

@ -19,16 +19,16 @@
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
#define OSC 24
#define OSC (V_OSCK/1000000)
/* MAIN PLL Fdll = 550 MHZ, */
#define MPUPLL_M 550
#define MPUPLL_N 23
#define MPUPLL_N (OSC-1)
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
#define COREPLL_N 23
#define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
@ -40,13 +40,13 @@
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
#define PERPLL_N 23
#define PERPLL_N (OSC-1)
#define PERPLL_M2 5
/* DDR Freq is 266 MHZ for now */
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#define DDRPLL_M 266
#define DDRPLL_N 23
#define DDRPLL_N (OSC-1)
#define DDRPLL_M2 1
extern void pll_init(void);

44
arch/arm/include/asm/arch-am33xx/cpu.h
View file

@ -53,8 +53,10 @@
/* Reset control */
#ifdef CONFIG_AM33XX
#define PRM_RSTCTRL 0x44E00F00
#define PRM_RSTST 0x44E00F08
#endif
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
@ -62,7 +64,7 @@
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
unsigned int wkctrlclkctrl; /* offset 0x04 */
unsigned int resv1[1];
unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
unsigned int resv2[4];
unsigned int idlestdpllmpu; /* offset 0x20 */
@ -111,34 +113,54 @@ struct cm_perpll {
unsigned int l3clkstctrl; /* offset 0x0c */
unsigned int resv1;
unsigned int cpgmac0clkctrl; /* offset 0x14 */
unsigned int resv2[4];
unsigned int lcdclkctrl; /* offset 0x18 */
unsigned int usb0clkctrl; /* offset 0x1C */
unsigned int resv2;
unsigned int tptc0clkctrl; /* offset 0x24 */
unsigned int emifclkctrl; /* offset 0x28 */
unsigned int ocmcramclkctrl; /* offset 0x2c */
unsigned int gpmcclkctrl; /* offset 0x30 */
unsigned int resv3[2];
unsigned int mcasp0clkctrl; /* offset 0x34 */
unsigned int uart5clkctrl; /* offset 0x38 */
unsigned int mmc0clkctrl; /* offset 0x3C */
unsigned int elmclkctrl; /* offset 0x40 */
unsigned int i2c2clkctrl; /* offset 0x44 */
unsigned int i2c1clkctrl; /* offset 0x48 */
unsigned int spi0clkctrl; /* offset 0x4C */
unsigned int spi1clkctrl; /* offset 0x50 */
unsigned int resv4[3];
unsigned int resv3[3];
unsigned int l4lsclkctrl; /* offset 0x60 */
unsigned int l4fwclkctrl; /* offset 0x64 */
unsigned int resv5[6];
unsigned int mcasp1clkctrl; /* offset 0x68 */
unsigned int uart1clkctrl; /* offset 0x6C */
unsigned int uart2clkctrl; /* offset 0x70 */
unsigned int uart3clkctrl; /* offset 0x74 */
unsigned int uart4clkctrl; /* offset 0x78 */
unsigned int timer7clkctrl; /* offset 0x7C */
unsigned int timer2clkctrl; /* offset 0x80 */
unsigned int resv6[11];
unsigned int timer3clkctrl; /* offset 0x84 */
unsigned int timer4clkctrl; /* offset 0x88 */
unsigned int resv4[8];
unsigned int gpio1clkctrl; /* offset 0xAC */
unsigned int gpio2clkctrl; /* offset 0xB0 */
unsigned int resv7[7];
unsigned int gpio3clkctrl; /* offset 0xB4 */
unsigned int resv5;
unsigned int tpccclkctrl; /* offset 0xBC */
unsigned int dcan0clkctrl; /* offset 0xC0 */
unsigned int dcan1clkctrl; /* offset 0xC4 */
unsigned int resv6[2];
unsigned int emiffwclkctrl; /* offset 0xD0 */
unsigned int resv8[2];
unsigned int resv7[2];
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
unsigned int resv9[14];
unsigned int resv8[4];
unsigned int mmc1clkctrl; /* offset 0xF4 */
unsigned int mmc2clkctrl; /* offset 0xF8 */
unsigned int resv9[8];
unsigned int l4hsclkstctrl; /* offset 0x11C */
unsigned int l4hsclkctrl; /* offset 0x120 */
unsigned int resv10[8];
unsigned int cpswclkctrl; /* offset 0x144 */
unsigned int cpswclkstctrl; /* offset 0x144 */
};
/* Encapsulating Display pll registers */
@ -213,8 +235,6 @@ struct ctrl_stat {
unsigned int resv1[16];
unsigned int statusreg; /* ofset 0x40 */
};
void init_timer(void);
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

8
arch/arm/include/asm/arch-am33xx/i2c.h
View file

@ -34,9 +34,9 @@ struct i2c {
unsigned short revnb_lo; /* 0x00 */
unsigned short res1;
unsigned short revnb_hi; /* 0x04 */
unsigned short res2[13];
unsigned short sysc; /* 0x20 */
unsigned short res3;
unsigned short res2[5];
unsigned short sysc; /* 0x10 */
unsigned short res3[9];
unsigned short irqstatus_raw; /* 0x24 */
unsigned short res4;
unsigned short stat; /* 0x28 */
@ -76,6 +76,6 @@ struct i2c {
};
#define I2C_IP_CLK 48000000
#define I2C_INTERNAL_SAMLPING_CLK 12000000
#define I2C_INTERNAL_SAMPLING_CLK 12000000
#endif /* _I2C_H_ */

45
arch/arm/include/asm/arch-at91/at91_pio.h
View file

@ -66,14 +66,50 @@ typedef struct at91_port {
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
#if defined(CPU_HAS_PIO3)
u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
u32 reserved5[2];
u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
u32 ppder; /* 0x94 Pad Pull-down Enable Register */
u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
u32 reserved6; /* */
#else
u32 asr; /* 0x70 Select A Register */
u32 bsr; /* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
#endif
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
u32 owsr; /* OxA8 utput Write Status Register */
u32 owsr; /* OxA8 Output Write Status Register */
#if defined(CPU_HAS_PIO3)
u32 reserved7; /* */
u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */
u32 reserved8; /* */
u32 esr; /* 0xC0 Edge Select Register */
u32 lsr; /* 0xC4 Level Select Register */
u32 elsr; /* 0xC8 Edge/Level Status Register */
u32 reserved9; /* 0xCC */
u32 fellsr; /* 0xD0 Falling /Low Level Select Register */
u32 rehlsr; /* 0xD4 Rising /High Level Select Register */
u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
u32 reserved10; /* */
u32 locksr; /* 0xE0 Lock Status */
u32 wpmr; /* 0xE4 Write Protect Mode Register */
u32 wpsr; /* 0xE8 Write Protect Status Register */
u32 reserved11[5]; /* */
u32 schmitt; /* 0x100 Schmitt Trigger Register */
u32 reserved12[63];
#else
u32 reserved6[85];
#endif
} at91_port_t;
typedef union at91_pio {
@ -94,6 +130,13 @@ typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
#if defined(CPU_HAS_PIO3)
int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);

40
arch/arm/include/asm/arch-exynos/cpu.h
View file

@ -24,6 +24,7 @@
#define DEVICE_NOT_AVAILABLE 0
#define EXYNOS_CPU_NAME "Exynos"
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 */
@ -93,29 +94,42 @@ static inline int s5p_get_cpu_rev(void)
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(EXYNOS4_PRO_ID);
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
/*
* 0xC200: EXYNOS4210 EVT0
* 0xC210: EXYNOS4210 EVT1
*/
if (s5p_cpu_id == 0xC200) {
s5p_cpu_id |= 0x10;
switch (pro_id) {
case 0x200:
/* Exynos4210 EVT0 */
s5p_cpu_id = 0x4210;
s5p_cpu_rev = 0;
} else if (s5p_cpu_id == 0xC210) {
s5p_cpu_rev = 1;
break;
case 0x210:
/* Exynos4210 EVT1 */
s5p_cpu_id = 0x4210;
break;
case 0x412:
/* Exynos4412 */
s5p_cpu_id = 0x4412;
break;
case 0x520:
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
}
}
static inline char *s5p_get_cpu_name(void)
{
return EXYNOS_CPU_NAME;
}
#define IS_SAMSUNG_TYPE(type, id) \
static inline int cpu_is_##type(void) \
{ \
return s5p_cpu_id == id ? 1 : 0; \
return (s5p_cpu_id >> 12) == id; \
}
IS_SAMSUNG_TYPE(exynos4, 0xc210)
IS_SAMSUNG_TYPE(exynos5, 0xc520)
IS_SAMSUNG_TYPE(exynos4, 0x4)
IS_SAMSUNG_TYPE(exynos5, 0x5)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \

47
arch/arm/include/asm/arch-exynos/periph.h Normal file
View file

@ -0,0 +1,47 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_PERIPH_H
#define __ASM_ARM_ARCH_PERIPH_H
/*
* Peripherals requiring clock/pinmux configuration. List will
* grow with support for more devices getting added.
*
*/
enum periph_id {
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
PERIPH_ID_SROMC,
PERIPH_ID_UART0,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */

58
arch/arm/include/asm/arch-exynos/pinmux.h Normal file
View file

@ -0,0 +1,58 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Abhilash Kesavan <a.kesavan@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_PINMUX_H
#define __ASM_ARM_ARCH_PINMUX_H
#include "periph.h"
/*
* Flags for setting specific configarations of peripherals.
* List will grow with support for more devices getting added.
*/
enum {
PINMUX_FLAG_NONE = 0x00000000,
/* Flags for eMMC */
PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
/* Flags for SROM controller */
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
};
/**
* Configures the pinmux for a particular peripheral.
*
* Each gpio can be configured in many different ways (4 bits on exynos)
* such as "input", "output", "special function", "external interrupt"
* etc. This function will configure the peripheral pinmux along with
* pull-up/down and drive strength.
*
* @param peripheral peripheral to be configured
* @param flags configure flags
* @return 0 if ok, -1 on error (e.g. unsupported peripheral)
*/
int exynos_pinmux_config(int peripheral, int flags);
#endif

12
arch/arm/include/asm/arch-kirkwood/config.h
View file

@ -82,9 +82,15 @@
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS 0
#endif
#ifndef CONFIG_ENV_SPI_CS
# define CONFIG_ENV_SPI_CS 0
#endif
#ifndef CONFIG_ENV_SPI_MAX_HZ
# define CONFIG_ENV_SPI_MAX_HZ 50000000
#endif
#endif
/*

2
arch/arm/include/asm/arch-kirkwood/mpp.h
View file

@ -312,6 +312,6 @@
#define MPP_MAX 49
void kirkwood_mpp_conf(unsigned int *mpp_list);
void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
#endif

11
arch/arm/include/asm/arch-kirkwood/spi.h
View file

@ -37,6 +37,17 @@ struct kwspi_registers {
u32 irq_mask; /* 0x10614 */
};
/* They are used to define CONFIG_SYS_KW_SPI_MPP
* each of the below #defines selects which mpp is
* configured for each SPI signal in spi_claim_bus
* bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
* bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
* bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
*/
#define MOSI_MPP6 (1 << 0)
#define SCK_MPP10 (1 << 1)
#define MISO_MPP11 (1 << 2)
#define KWSPI_CLKPRESCL_MASK 0x1f
#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */

2
arch/arm/include/asm/arch-mx28/regs-common.h
View file

@ -70,7 +70,7 @@ struct mx28_register_32 {
#define mx28_reg_8(name) \
union { \
struct { __mx28_reg_8(name) }; \
struct mx28_register_32 name##_reg; \
struct mx28_register_8 name##_reg; \
};
#define mx28_reg_32(name) \

4
arch/arm/include/asm/arch-mx6/mx6x_pins.h
View file

@ -48,8 +48,8 @@
#define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
#define NO_MUX_I 0x3FF
#define NO_PAD_I 0x7FF
#define NO_MUX_I 0
#define NO_PAD_I 0
enum {
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),

2
arch/arm/include/asm/arch-omap3/cpu.h
View file

@ -479,6 +479,8 @@ struct prm {
#define PRM_RSTCTRL 0x48307250
#define PRM_RSTCTRL_RESET 0x04
#define PRM_RSTST 0x48307258
#define PRM_RSTST_WARM_RESET_MASK 0x7D2
#define SYSCLKDIV_1 (0x1 << 6)
#define SYSCLKDIV_2 (0x1 << 7)

1
arch/arm/include/asm/arch-omap3/sys_proto.h
View file

@ -74,4 +74,5 @@ void power_init_r(void);
void dieid_num_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
u32 warm_reset(void);
#endif

5
arch/arm/include/asm/arch-omap4/clocks.h
View file

@ -525,6 +525,11 @@ struct omap4_scrm_regs {
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE 0
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)

2
arch/arm/include/asm/arch-omap4/cpu.h
View file

@ -178,5 +178,7 @@ struct watchdog {
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
#define PRM_RSTST_WARM_RESET_MASK 0x07EA
#endif /* _CPU_H */

2
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -112,7 +112,7 @@
#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
#define LPDDR2IO_GR10_WD_MASK (3 << 17)
#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000

2
arch/arm/include/asm/arch-omap4/sys_proto.h
View file

@ -57,6 +57,8 @@ void init_omap_revision(void);
void do_io_settings(void);
void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
/*
* This is used to verify if the configuration header
* was executed by Romcode prior to control of transfer

15
arch/arm/include/asm/arch-omap5/clocks.h
View file

@ -480,6 +480,13 @@ struct omap5_prcm_regs {
u32 pad217[4];
u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
u32 pad218[2];
u32 prm_sldo_core_setup; /* 4ae07bc4 */
u32 prm_sldo_core_ctrl; /* 4ae07bc8 */
u32 prm_sldo_mpu_setup; /* 4ae07bcc */
u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */
u32 prm_sldo_mm_setup; /* 4ae07bd4 */
u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */
};
/* DPLL register offsets */
@ -490,6 +497,11 @@ struct omap5_prcm_regs {
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE 0
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
@ -641,6 +653,9 @@ struct omap5_prcm_regs {
#define VDD_MPU 1000
#define VDD_MM 1000
#define VDD_CORE 1040
#define VDD_MPU_5432 1150
#define VDD_MM_5432 1150
#define VDD_CORE_5432 1150
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000

2
arch/arm/include/asm/arch-omap5/cpu.h
View file

@ -182,5 +182,7 @@ struct watchdog {
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
#define PRM_RSTST_WARM_RESET_MASK 0x7FEA
#endif /* _CPU_H */

20
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -40,7 +40,7 @@
#define OMAP54XX_L4_PER_BASE 0x48000000
#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
@ -56,7 +56,8 @@
#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */
#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
@ -178,7 +179,14 @@ struct omap_sys_ctrl_regs {
u32 control_srcomp_east_side; /*0x4A002E7C*/
u32 control_srcomp_west_side; /*0x4A002E80*/
u32 control_srcomp_code_latch; /*0x4A002E84*/
u32 pad4[3680198];
u32 pad4[3679394];
u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
u32 pad5[10];
u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
u32 pad6[789];
u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
u32 control_padconf_mode; /* 0x4AE0CDA8 */
@ -233,6 +241,12 @@ struct omap_sys_ctrl_regs {
#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100

2
arch/arm/include/asm/arch-omap5/sys_proto.h
View file

@ -57,6 +57,8 @@ void init_omap_revision(void);
void do_io_settings(void);
void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
/*
* This is used to verify if the configuration header

6
arch/arm/include/asm/arch-s5pc1xx/cpu.h
View file

@ -23,6 +23,7 @@
#ifndef _S5PC1XX_CPU_H
#define _S5PC1XX_CPU_H
#define S5P_CPU_NAME "S5P"
#define S5PC1XX_ADDR_BASE 0xE0000000
/* S5PC100 */
@ -71,6 +72,11 @@ static inline void s5p_set_cpu_id(void)
s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
}
static inline char *s5p_get_cpu_name(void)
{
return S5P_CPU_NAME;
}
#define IS_SAMSUNG_TYPE(type, id) \
static inline int cpu_is_##type(void) \
{ \

27
arch/arm/include/asm/arch-spear/clk.h Normal file
View file

@ -0,0 +1,27 @@
/*
* (C) Copyright 2010
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return 83000000;
}

40
arch/arm/include/asm/arch-spear/gpio.h Normal file
View file

@ -0,0 +1,40 @@
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SPEAR_GPIO_H
#define __ASM_ARCH_SPEAR_GPIO_H
enum gpio_direction {
GPIO_DIRECTION_IN,
GPIO_DIRECTION_OUT,
};
struct gpio_regs {
u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */
u32 gpiodir; /* 0x400 */
};
#define SPEAR_GPIO_COUNT 8
#define DATA_REG_ADDR(gpio) (1 << (gpio + 2))
#endif /* __ASM_ARCH_SPEAR_GPIO_H */

63
arch/arm/include/asm/arch-spear/hardware.h
View file

@ -24,43 +24,68 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define CONFIG_SYS_USBD_BASE (0xE1100000)
#define CONFIG_SYS_PLUG_BASE (0xE1200000)
#define CONFIG_SYS_FIFO_BASE (0xE1000800)
#define CONFIG_SYS_SMI_BASE (0xFC000000)
#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000)
#define CONFIG_SPEAR_TIMERBASE (0xFC800000)
#define CONFIG_SPEAR_MISCBASE (0xFCA80000)
#define CONFIG_SYS_USBD_BASE 0xE1100000
#define CONFIG_SYS_PLUG_BASE 0xE1200000
#define CONFIG_SYS_FIFO_BASE 0xE1000800
#define CONFIG_SYS_SMI_BASE 0xFC000000
#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
#define CONFIG_SPEAR_TIMERBASE 0xFC800000
#define CONFIG_SPEAR_MISCBASE 0xFCA80000
#define CONFIG_SPEAR_ETHBASE 0xE0800000
#define CONFIG_SPEAR_MPMCBASE 0xFC600000
#define CONFIG_SSP1_BASE 0xD0100000
#define CONFIG_SSP2_BASE 0xD0180000
#define CONFIG_SSP3_BASE 0xD8180000
#define CONFIG_GPIO_BASE 0xD8100000
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE (0xD0200000)
#define CONFIG_SPEAR_FSMCBASE (0xD1800000)
#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_FSMC_BASE 0xD1800000
#define CONFIG_FSMC_NAND_BASE 0xD2000000
#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000
#define CONFIG_SPEAR_BOOTSTRAPSHFT 16
#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB
#define CONFIG_SPEAR_ONLYSNORBOOT 0xA
#define CONFIG_SPEAR_NORNANDBOOT 0xB
#define CONFIG_SPEAR_NORNAND8BOOT 0x8
#define CONFIG_SPEAR_NORNAND16BOOT 0x9
#define CONFIG_SPEAR_USBBOOT 0x8
#define CONFIG_SPEAR_MPMCREGS 100
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_I2C_BASE (0xD0180000)
#define CONFIG_SPEAR_FSMCBASE (0x94000000)
#define CONFIG_SYS_I2C_BASE 0xD0180000
#define CONFIG_SYS_FSMC_BASE 0x94000000
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_I2C_BASE (0xD0180000)
#define CONFIG_SPEAR_FSMCBASE (0x44000000)
#define CONFIG_SYS_I2C_BASE 0xD0180000
#define CONFIG_SYS_FSMC_BASE 0x44000000
#undef CONFIG_SYS_NAND_CLE
#undef CONFIG_SYS_NAND_ALE
#define CONFIG_SYS_NAND_CLE (1 << 17)
#define CONFIG_SYS_NAND_ALE (1 << 16)
#define CONFIG_SPEAR_EMIBASE (0x4F000000)
#define CONFIG_SPEAR_RASBASE (0xB4000000)
#define CONFIG_SPEAR_EMIBASE 0x4F000000
#define CONFIG_SPEAR_RASBASE 0xB4000000
#define CONFIG_SYS_MACB0_BASE 0xB0000000
#define CONFIG_SYS_MACB1_BASE 0xB0800000
#define CONFIG_SYS_MACB2_BASE 0xB1000000
#define CONFIG_SYS_MACB3_BASE 0xB1800000
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_I2C_BASE (0xD0180000)
#define CONFIG_SPEAR_FSMCBASE (0x4C000000)
#define CONFIG_SYS_I2C_BASE 0xD0180000
#define CONFIG_SYS_FSMC_BASE 0x4C000000
#define CONFIG_SPEAR_EMIBASE (0x40000000)
#define CONFIG_SPEAR_RASBASE (0xB3000000)
#define CONFIG_SPEAR_EMIBASE 0x40000000
#define CONFIG_SPEAR_RASBASE 0xB3000000
#define CONFIG_SYS_MACB0_BASE 0xAA000000
#endif
#endif /* _ASM_ARCH_HARDWARE_H */

23
arch/arm/include/asm/arch-spear/spr_defs.h
View file

@ -28,6 +28,23 @@ extern int spear_board_init(ulong);
extern void setfreq(unsigned int, unsigned int);
extern unsigned int setfreq_sz;
void plat_ddr_init(void);
void soc_init(void);
void spear_late_init(void);
void plat_late_init(void);
int snor_boot_selected(void);
int nand_boot_selected(void);
int pnor_boot_selected(void);
int usb_boot_selected(void);
int uart_boot_selected(void);
int tftp_boot_selected(void);
int i2c_boot_selected(void);
int spi_boot_selected(void);
int mmc_boot_selected(void);
extern u32 mpmc_conf_vals[];
struct chip_data {
int cpufreq;
int dramfreq;
@ -43,4 +60,10 @@ struct chip_data {
#define MAC_OFF 0x2
#define MAC_LEN 0x6
#define PNOR_WIDTH_8 0
#define PNOR_WIDTH_16 1
#define PNOR_WIDTH_32 2
#define PNOR_WIDTH_NUM 3
#define PNOR_WIDTH_SEARCH 0xff
#endif

4
arch/arm/include/asm/arch-spear/spr_gpt.h
View file

@ -79,7 +79,7 @@ struct gpt_regs {
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
#define CONFIG_SPEAR_HZ (1000)
#define CONFIG_SPEAR_HZ_CLOCK (8300000)
#define CONFIG_SPEAR_HZ 1000
#define CONFIG_SPEAR_HZ_CLOCK 8300000
#endif

147
arch/arm/include/asm/arch-spear/spr_misc.h
View file

@ -37,7 +37,7 @@ struct misc_regs {
u32 amba_clk_cfg; /* 0x24 */
u32 periph_clk_cfg; /* 0x28 */
u32 periph1_clken; /* 0x2C */
u32 periph2_clken; /* 0x30 */
u32 soc_core_id; /* 0x30 */
u32 ras_clken; /* 0x34 */
u32 periph1_rst; /* 0x38 */
u32 periph2_rst; /* 0x3C */
@ -46,7 +46,7 @@ struct misc_regs {
u32 prsc2_clk_cfg; /* 0x48 */
u32 prsc3_clk_cfg; /* 0x4C */
u32 amem_cfg_ctrl; /* 0x50 */
u32 port_cfg_ctrl; /* 0x54 */
u32 expi_clk_cfg; /* 0x54 */
u32 reserved_1; /* 0x58 */
u32 clcd_synth_clk; /* 0x5C */
u32 irda_synth_clk; /* 0x60 */
@ -101,6 +101,37 @@ struct misc_regs {
u32 ras_gpp2_out; /* 0x800C */
};
/* SYNTH_CLK value*/
#define SYNTH23 0x00020003
/* PLLx_FRQ value */
#if defined(CONFIG_SPEAR3XX)
#define FREQ_332 0xA600010C
#define FREQ_266 0x8500010C
#elif defined(CONFIG_SPEAR600)
#define FREQ_332 0xA600010F
#define FREQ_266 0x8500010F
#endif
/* PLL_CTR_REG */
#define MEM_CLK_SEL_MSK 0x70000000
#define MEM_CLK_HCLK 0x00000000
#define MEM_CLK_2HCLK 0x10000000
#define MEM_CLK_PLL2 0x30000000
#define EXPI_CLK_CFG_LOW_COMPR 0x2000
#define EXPI_CLK_CFG_CLK_EN 0x0400
#define EXPI_CLK_CFG_RST 0x0200
#define EXPI_CLK_SYNT_EN 0x0010
#define EXPI_CLK_CFG_SEL_PLL2 0x0004
#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
#define PLL2_CNTL_6UA 0x1c00
#define PLL2_CNTL_SAMPLE 0x0008
#define PLL2_CNTL_ENABLE 0x0004
#define PLL2_CNTL_RESETN 0x0002
#define PLL2_CNTL_LOCK 0x0001
/* AUTO_CFG_REG value */
#define MISC_SOCCFGMSK 0x0000003F
#define MISC_SOCCFG30 0x0000000C
@ -110,6 +141,8 @@ struct misc_regs {
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
#define CONFIG_SPEAR_UART48M 0
#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
/* PRSC_CLK_CFG value */
/*
@ -126,5 +159,115 @@ struct misc_regs {
/* PERIPH1_CLKEN, PERIPH1_RST value */
#define MISC_USBDENB 0x01000000
#define MISC_ETHENB 0x00800000
#define MISC_SMIENB 0x00200000
#define MISC_GPT3ENB 0x00010000
#define MISC_GPIO4ENB 0x00002000
#define MISC_GPT2ENB 0x00000800
#define MISC_FSMCENB 0x00000200
#define MISC_I2CENB 0x00000080
#define MISC_SSP2ENB 0x00000070
#define MISC_UART0ENB 0x00000008
/* PERIPH_CLK_CFG */
#define XTALTIMEEN 0x00000001
#define PLLTIMEEN 0x00000002
#define CLCDCLK_SYNTH 0x00000000
#define CLCDCLK_48MHZ 0x00000004
#define CLCDCLK_EXT 0x00000008
#define UARTCLK_MASK (0x1 << 4)
#define UARTCLK_48MHZ 0x00000000
#define UARTCLK_SYNTH 0x00000010
#define IRDACLK_48MHZ 0x00000000
#define IRDACLK_SYNTH 0x00000020
#define IRDACLK_EXT 0x00000040
#define RTC_DISABLE 0x00000080
#define GPT1CLK_48MHZ 0x00000000
#define GPT1CLK_SYNTH 0x00000100
#define GPT2CLK_48MHZ 0x00000000
#define GPT2CLK_SYNTH 0x00000200
#define GPT3CLK_48MHZ 0x00000000
#define GPT3CLK_SYNTH 0x00000400
#define GPT4CLK_48MHZ 0x00000000
#define GPT4CLK_SYNTH 0x00000800
#define GPT5CLK_48MHZ 0x00000000
#define GPT5CLK_SYNTH 0x00001000
#define GPT1_FREEZE 0x00002000
#define GPT2_FREEZE 0x00004000
#define GPT3_FREEZE 0x00008000
#define GPT4_FREEZE 0x00010000
#define GPT5_FREEZE 0x00020000
/* PERIPH1_CLKEN bits */
#define PERIPH_ARM1_WE 0x00000001
#define PERIPH_ARM1 0x00000002
#define PERIPH_ARM2 0x00000004
#define PERIPH_UART1 0x00000008
#define PERIPH_UART2 0x00000010
#define PERIPH_SSP1 0x00000020
#define PERIPH_SSP2 0x00000040
#define PERIPH_I2C 0x00000080
#define PERIPH_JPEG 0x00000100
#define PERIPH_FSMC 0x00000200
#define PERIPH_FIRDA 0x00000400
#define PERIPH_GPT4 0x00000800
#define PERIPH_GPT5 0x00001000
#define PERIPH_GPIO4 0x00002000
#define PERIPH_SSP3 0x00004000
#define PERIPH_ADC 0x00008000
#define PERIPH_GPT3 0x00010000
#define PERIPH_RTC 0x00020000
#define PERIPH_GPIO3 0x00040000
#define PERIPH_DMA 0x00080000
#define PERIPH_ROM 0x00100000
#define PERIPH_SMI 0x00200000
#define PERIPH_CLCD 0x00400000
#define PERIPH_GMAC 0x00800000
#define PERIPH_USBD 0x01000000
#define PERIPH_USBH1 0x02000000
#define PERIPH_USBH2 0x04000000
#define PERIPH_MPMC 0x08000000
#define PERIPH_RAMW 0x10000000
#define PERIPH_MPMC_EN 0x20000000
#define PERIPH_MPMC_WE 0x40000000
#define PERIPH_MPMCMSK 0x60000000
#define PERIPH_CLK_ALL 0x0FFFFFF8
#define PERIPH_RST_ALL 0x00000004
/* DDR_PAD values */
#define DDR_PAD_CNF_MSK 0x0000ffff
#define DDR_PAD_SW_CONF 0x00060000
#define DDR_PAD_SSTL_SEL 0x00000001
#define DDR_PAD_DRAM_TYPE 0x00008000
/* DDR_COMP values */
#define DDR_COMP_ACCURATE 0x00000010
/* SoC revision stuff */
#define SOC_PRI_SHFT 16
#define SOC_SEC_SHFT 8
/* Revision definitions */
#define SOC_SPEAR_NA 0
/*
* The definitons have started from
* 101 for SPEAr6xx
* 201 for SPEAr3xx
* 301 for SPEAr13xx
*/
#define SOC_SPEAR600_AA 101
#define SOC_SPEAR600_AB 102
#define SOC_SPEAR600_BA 103
#define SOC_SPEAR600_BB 104
#define SOC_SPEAR600_BC 105
#define SOC_SPEAR600_BD 106
#define SOC_SPEAR300 201
#define SOC_SPEAR310 202
#define SOC_SPEAR320 203
extern int get_socrev(void);
#endif

57
arch/arm/include/asm/arch-spear/spr_nand.h
View file

@ -1,57 +0,0 @@
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SPR_NAND_H__
#define __SPR_NAND_H__
struct fsmc_regs {
u32 reserved_1[0x10];
u32 genmemctrl_pc;
u32 reserved_2;
u32 genmemctrl_comm;
u32 genmemctrl_attrib;
u32 reserved_3;
u32 genmemctrl_ecc;
};
/* genmemctrl_pc register definitions */
#define FSMC_RESET (1 << 0)
#define FSMC_WAITON (1 << 1)
#define FSMC_ENABLE (1 << 2)
#define FSMC_DEVTYPE_NAND (1 << 3)
#define FSMC_DEVWID_8 (0 << 4)
#define FSMC_DEVWID_16 (1 << 4)
#define FSMC_ECCEN (1 << 6)
#define FSMC_ECCPLEN_512 (0 << 7)
#define FSMC_ECCPLEN_256 (1 << 7)
#define FSMC_TCLR_1 (1 << 9)
#define FSMC_TAR_1 (1 << 13)
/* genmemctrl_comm register definitions */
#define FSMC_TSET_0 (0 << 0)
#define FSMC_TWAIT_6 (6 << 8)
#define FSMC_THOLD_4 (4 << 16)
#define FSMC_THIZ_1 (1 << 24)
extern int spear_nand_init(struct nand_chip *nand);
#endif

45
arch/arm/include/asm/arch-spear/spr_ssp.h Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPR_SSP_H
#define _SPR_SSP_H
struct ssp_regs {
u32 sspcr0;
u32 sspcr1;
u32 sspdr;
u32 sspsr;
u32 sspcpsr;
u32 sspimsc;
u32 sspicr;
u32 sspdmacr;
};
#define SSPCR0_FRF_MOT_SPI 0x0000
#define SSPCR0_DSS_16BITS 0x000f
#define SSPCR1_SSE 0x0002
#define SSPSR_TNF 0x2
#define SSPSR_TFE 0x1
#endif

14
arch/arm/include/asm/arch-spear/spr_syscntl.h
View file

@ -21,6 +21,9 @@
* MA 02111-1307 USA
*/
#ifndef __SYSCTRL_H
#define __SYSCTRL_H
struct syscntl_regs {
u32 scctrl;
u32 scsysstat;
@ -36,3 +39,14 @@ struct syscntl_regs {
const u32 scperclken;
const u32 scperstat;
};
#define MODE_SHIFT 0x00000003
#define NORMAL 0x00000004
#define SLOW 0x00000002
#define DOZE 0x00000001
#define SLEEP 0x00000000
#define PLL_TIM 0x01FFFFFF
#endif

67
arch/arm/include/asm/arch-spear/spr_xloader_table.h
View file

@ -1,67 +0,0 @@
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPR_XLOADER_TABLE_H
#define _SPR_XLOADER_TABLE_H
#define XLOADER_TABLE_VERSION_1_1 2
#define XLOADER_TABLE_VERSION_1_2 3
#define XLOADER_TABLE_ADDRESS 0xD2801FF0
#define DDRMOBILE 1
#define DDR2 2
#define REV_BA 1
#define REV_AA 2
#define REV_AB 3
struct xloader_table_1_1 {
unsigned short ddrfreq;
unsigned char ddrsize;
unsigned char ddrtype;
unsigned char soc_rev;
} __attribute__ ((packed));
struct xloader_table_1_2 {
unsigned const char *version;
unsigned short ddrfreq;
unsigned char ddrsize;
unsigned char ddrtype;
unsigned char soc_rev;
} __attribute__ ((packed));
union table_contents {
struct xloader_table_1_1 table_1_1;
struct xloader_table_1_2 table_1_2;
};
struct xloader_table {
unsigned char table_version;
union table_contents table;
} __attribute__ ((packed));
#endif

5
arch/arm/include/asm/arch-tegra2/clock.h
View file

@ -186,8 +186,9 @@ enum periph_id {
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
/* return 1 if a PLL ID is in range */
#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
/* return 1 if a PLL ID is in range, and not a simple PLL */
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
(id) < CLOCK_ID_FIRST_SIMPLE)
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300

4
arch/arm/include/asm/arch-tegra2/funcmux.h
View file

@ -30,6 +30,9 @@ enum {
/* UART configs */
FUNCMUX_UART1_IRRX_IRTX = 0,
FUNCMUX_UART1_UAA_UAB,
FUNCMUX_UART1_GPU,
FUNCMUX_UART1_SDIO1,
FUNCMUX_UART2_IRDA = 0,
FUNCMUX_UART4_GMC = 0,
@ -41,6 +44,7 @@ enum {
FUNCMUX_I2C3_DTF = 0,
/* SDMMC configs */
FUNCMUX_SDMMC1_SDIO1_4BIT = 0,
FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0,
FUNCMUX_SDMMC3_SDB_4BIT = 0,
FUNCMUX_SDMMC3_SDB_SLXA_8BIT,

7
arch/arm/include/asm/arch-tegra2/gpio.h
View file

@ -2,6 +2,7 @@
* Copyright (c) 2011, Google Inc. All rights reserved.
* See file CREDITS for list of people who contributed to this
* project.
* Portions Copyright 2011-2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -19,8 +20,8 @@
* MA 02111-1307 USA
*/
#ifndef _TEGRA2_GPIO_H_
#define _TEGRA2_GPIO_H_
#ifndef _TEGRA_GPIO_H_
#define _TEGRA_GPIO_H_
/*
* The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
@ -286,4 +287,4 @@ enum gpio_pin {
void gpio_info(void);
#define gpio_status() gpio_info()
#endif /* TEGRA2_GPIO_H_ */
#endif /* TEGRA_GPIO_H_ */

2
arch/arm/include/asm/arch-tegra2/pinmux.h
View file

@ -67,7 +67,7 @@ enum pmux_pingrp {
PINGRP_KBCF,
PINGRP_GMA,
PINGRP_GMC,
PINGRP_SDMMC1,
PINGRP_SDIO1,
PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */

4
arch/arm/include/asm/arch-tegra2/tegra2.h
View file

@ -60,6 +60,10 @@ struct timerus {
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
#define AP20_WB_RUN_ADDRESS 0x40020000
#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
/* These are the available SKUs (product types) for Tegra */
enum {
SKU_ID_T20 = 0x8,

9
arch/arm/include/asm/arch-tegra2/tegra2_spi.h → arch/arm/include/asm/arch-tegra2/tegra_spi.h
View file

@ -1,7 +1,7 @@
/*
* NVIDIA Tegra2 SPI-FLASH controller
*
* Copyright 2010-2011 NVIDIA Corporation
* Copyright 2010-2012 NVIDIA Corporation
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
@ -22,8 +22,8 @@
* MA 02111-1307 USA
*/
#ifndef _TEGRA2_SPI_H_
#define _TEGRA2_SPI_H_
#ifndef _TEGRA_SPI_H_
#define _TEGRA_SPI_H_
#include <asm/types.h>
@ -72,5 +72,4 @@ struct spi_tegra {
#define SPI_TIMEOUT 1000
#define TEGRA2_SPI_MAX_FREQ 52000000
#endif /* _TEGRA2_SPI_H_ */
#endif /* _TEGRA_SPI_H_ */

4
arch/arm/include/asm/arch-tegra2/uart-spi-switch.h
View file

@ -29,7 +29,7 @@
* time! If the board file provides this, the board config will declare it.
* Let this be a lesson for others.
*/
void pinmux_select_uart(NS16550_t regs);
void pinmux_select_uart(void);
/*
* Signal that we are about the use the SPI bus.
@ -38,7 +38,7 @@ void pinmux_select_spi(void);
#else /* not CONFIG_SPI_UART_SWITCH */
static inline void pinmux_select_uart(NS16550_t regs) {}
static inline void pinmux_select_uart(void) {}
static inline void pinmux_select_spi(void) {}
#endif

52
arch/arm/include/asm/emif.h
View file

@ -471,6 +471,49 @@
#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
/*EMIF_READ_WRITE_LEVELING_CONTROL*/
#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31
#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31)
#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24
#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24)
#define EMIF_REG_RDLVLINC_INT_SHIFT 16
#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16)
#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8
#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8)
#define EMIF_REG_WRLVLINC_INT_SHIFT 0
#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0)
/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
#define EMIF_REG_RDWRLVL_EN_SHIFT 31
#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31)
#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24
#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24)
#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16
#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16)
#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8
#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8)
#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0
#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0)
/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
/*Leveling Fields */
#define DDR3_WR_LVL_INT 0x73
#define DDR3_RD_LVL_INT 0x33
#define DDR3_RD_LVL_GATE_INT 0x59
#define RD_RW_LVL_INC_PRE 0x0
#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
| (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
| (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \
| (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
/* DMM */
#define DMM_BASE 0x4E000040
@ -650,6 +693,7 @@ struct dmm_lisa_map_regs {
};
extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
#define CS0 0
#define CS1 1
@ -1073,6 +1117,10 @@ struct emif_regs {
u32 emif_ddr_ext_phy_ctrl_3;
u32 emif_ddr_ext_phy_ctrl_4;
u32 emif_ddr_ext_phy_ctrl_5;
u32 emif_rd_wr_lvl_rmp_win;
u32 emif_rd_wr_lvl_rmp_ctl;
u32 emif_rd_wr_lvl_ctl;
u32 emif_rd_wr_exec_thresh;
};
/* assert macros */
@ -1093,11 +1141,13 @@ void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs1_device_timings);
#endif
void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;
extern u32 *const T_den;
extern u32 *const emif_sizes;
#endif
void config_data_eye_leveling_samples(u32 emif_base);
#endif

1
arch/arm/include/asm/omap_common.h
View file

@ -136,4 +136,5 @@ static inline u32 omap_revision(void)
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100
#define OMAP5432_ES1_0 0x54320100
#endif /* _OMAP_COMMON_H_ */

1
arch/arm/include/asm/u-boot-arm.h
View file

@ -52,6 +52,7 @@ void cpu_init_cp15(void);
/* cpu/.../arch/cpu.c */
int arch_cpu_init(void);
int arch_misc_init(void);
int arch_early_init_r(void);
/* board/.../... */
int board_init(void);

4
arch/arm/lib/board.c
View file

@ -500,6 +500,10 @@ void board_init_r(gd_t *id, ulong dest_addr)
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r();
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");

6
arch/arm/lib/cache-cp15.c
View file

@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit)
{
uint32_t reg;
reg = get_cr();
cp_delay();
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
reg = get_cr();
if ((reg & CR_C) != CR_C)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
flush_dcache_all();
}
reg = get_cr();
cp_delay();
set_cr(reg & ~cache_bit);
}
#endif

3
arch/arm/lib/eabi_compat.c
View file

@ -13,7 +13,8 @@
int raise (int signum)
{
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
/* Even if printf() is available, it's large. Punt it for SPL builds */
#if !defined(CONFIG_SPL_BUILD)
printf("raise: Signal # %d caught\n", signum);
#endif
return 0;

44
board/spear/spear310/config.mk → board/BuS/vl_ma2sc/Makefile
View file

@ -1,6 +1,10 @@
#
# (C) Copyright 2009
# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2009-2012
# Jens Scharsig <esw@bus-elekronik.de>
# BuS Elektronik GmbH & Co. KG
#
# See file CREDITS for list of people who contributed to this
# project.
@ -12,7 +16,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@ -21,24 +25,24 @@
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS += vl_ma2sc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
CONFIG_SYS_TEXT_BASE = 0x00700000
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
ALL-y += $(obj)u-boot.img
sinclude $(obj).depend
# Environment variables in NAND
ifeq ($(ENV),NAND)
PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
else
PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
endif
# Support parallel flash
ifeq ($(FLASH),PNOR)
PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
endif
ifeq ($(CONSOLE),USB)
PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
endif
#########################################################################

551
board/BuS/vl_ma2sc/vl_ma2sc.c Normal file
View file

@ -0,0 +1,551 @@
/*
* (C) Copyright 2009-2012
* Jens Scharsig <esw@bus-elekronik.de>
* BuS Elektronik GmbH & Co. KG
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_common.h>
#include <lcd.h>
#include <i2c.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void vl_ma2sc_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
/* Enable CS3 */
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
&pmc->pcer);
/* Configure RDY/BSY */
#ifdef CONFIG_SYS_NAND_READY_PIN
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void vl_ma2sc_macb_hw_init(void)
{
unsigned long erstl;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_macb_hw_init();
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 240,
.vl_clk = 6500000,
.vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVVD_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
.vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
.vl_tft = 1,
.vl_hsync_len = 5, /* Horiz Sync Pulse Width */
.vl_left_margin = 68, /* horiz back porch */
.vl_right_margin = 20, /* horiz front porch */
.vl_vsync_len = 2, /* vert Sync Pulse Width */
.vl_upper_margin = 18, /* vert back porch */
.vl_lower_margin = 4, /* vert front porch */
.mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
{
}
void lcd_disable(void)
{
}
static void vl_ma2sc_lcd_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
gd->fb_base = ATMEL_BASE_SRAM0;
}
#endif /* Config LCD */
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable clocks for all PIOs */
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
(1 << ATMEL_ID_PIOCDE),
&pmc->pcer);
at91_seriald_hw_init();
return 0;
}
#endif
int board_init(void)
{
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u32 pin;
pin = 0x1F000001;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
writel(pin, &pio->pioa.oer);
writel(pin, &pio->pioa.sodr);
writel((1 << 25), &pio->pioa.codr);
pin = 0x1F000100;
writel(pin, &pio->piob.idr);
writel(pin, &pio->piob.pudr);
writel(pin, &pio->piob.per);
writel(pin, &pio->piob.oer);
writel(pin, &pio->piob.codr);
writel((1 << 24), &pio->piob.sodr);
pin = 0x40000000; /* Pullup DRxD enbable */
writel(pin, &pio->pioc.puer);
pin = 0x0000000F; /* HWversion als Input */
writel(pin, &pio->piod.idr);
writel(pin, &pio->piod.puer);
writel(pin, &pio->piod.per);
writel(pin, &pio->piod.odr);
writel(pin, &pio->piod.owdr);
/* Enable Ctrlc */
console_init_f();
gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
#ifdef CONFIG_CMD_NAND
vl_ma2sc_nand_hw_init();
#endif
#ifdef CONFIG_MACB
vl_ma2sc_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
vl_ma2sc_lcd_hw_init();
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uchar buffer[8];
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u32 pin;
buffer[0] = 0x04;
buffer[1] = 0x00;
if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
puts("error reseting rtc clock\n\0");
/* read hardware version */
pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
printf("Board: revision %c\n", pin);
buffer[0] = pin;
buffer[1] = 0;
setenv("revision", (char *) buffer);
pin = 0x40000000; /* Pullup DRxD enbable */
writel(pin, &pio->pioc.puer);
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
#endif
return rc;
}
#ifdef CONFIG_SOFT_I2C
void i2c_init_board(void)
{
u32 pin;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u8 sda = (1<<4);
u8 scl = (1<<5);
writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
pin = sda | scl;
writel(pin, &pio->piob.idr); /* Disable Interupt */
writel(pin, &pio->piob.pudr);
writel(pin, &pio->piob.per);
writel(pin, &pio->piob.oer);
writel(pin, &pio->piob.sodr);
}
#endif
void watchdog_reset(void)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u32 pin = 0x1; /* PA0 */
if ((readl(&pio->pioa.odsr) & pin) > 0)
writel(pin, &pio->pioa.codr);
else
writel(pin, &pio->pioa.sodr);
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
/*---------------------------------------------------------------------------*/
int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 1;
int row;
int col;
u32 pinz;
u32 pins;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
pins = 0x1F000000;
writel(pins, &pio->pioa.idr);
writel(pins, &pio->pioa.pudr);
writel(pins, &pio->pioa.per);
writel(pins, &pio->pioa.oer);
writel(pins, &pio->pioa.sodr);
pinz = 0x1F000000;
writel(pinz, &pio->piob.idr);
writel(pinz, &pio->piob.pudr);
writel(pinz, &pio->piob.per);
writel(pinz, &pio->piob.oer);
writel(pinz, &pio->piob.sodr);
for (row = 0; row < 5; row++) {
for (col = 0; col < 5; col++) {
writel((0x01000000 << col), &pio->piob.sodr);
writel((0x01000000 << row), &pio->pioa.codr);
printf("LED Test %d x %d\n", row, col);
udelay(1000000);
writel(pinz, &pio->piob.codr);
writel(pins, &pio->pioa.sodr);
}
}
return rcode;
}
void poweroff(void)
{
watchdog_reset();
at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
udelay(100);
at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
udelay(100);
at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
udelay(100);
while (1)
watchdog_reset();
}
int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 1;
poweroff();
return rcode;
}
int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
u32 freq;
u32 durate;
int rcode = 1;
freq = 1000;
durate = 2;
switch (argc) {
case 3:
durate = simple_strtoul(argv[2], NULL, 10);
case 2:
freq = simple_strtoul(argv[1], NULL, 10);
case 1:
break;
default:
cmd_usage(cmdtp);
rcode = 1;
break;
}
durate = durate * freq;
freq = 500000 / freq;
for (i = 0; i < durate; i++) {
at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
udelay(freq);
at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
udelay(freq);
}
at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
return rcode;
}
int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 1;
int row;
u32 col;
u32 pinz;
u32 pins;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
pins = 0x001F0000;
writel(pins, &pio->pioa.idr);
writel(pins, &pio->pioa.pudr);
writel(pins, &pio->pioa.per);
writel(pins, &pio->pioa.odr);
pinz = 0x000F0000;
writel(pinz, &pio->piob.idr);
writel(pinz, &pio->piob.pudr);
writel(pinz, &pio->piob.per);
writel(pinz, &pio->piob.oer);
writel(pinz, &pio->piob.codr);
while (1) {
col = 0;
for (row = 0; row < 4; row++) {
writel((0x00010000 << row), &pio->piob.sodr);
udelay(10000);
col <<= 4;
col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
writel(pinz, &pio->piob.codr);
}
printf("Matix: ");
for (row = 0; row < 16; row++) {
printf("%1.1d", col & 1);
col >>= 1;
}
printf(" SP %d\r ",
1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
/* SHUTDOWN */
row = 0;
while (row < 1000) {
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
row++;
udelay(100);
}
udelay(100000);
row = 0;
while (row < 1000) {
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
row++;
udelay(1000);
}
}
poweroff();
while (1)
;
}
}
return rcode;
}
/*****************************************************************************/
U_BOOT_CMD(
ledtest, 1, 0, do_ledtest,
"test ledmatrix",
"\n"
);
U_BOOT_CMD(
keytest, 1, 0, do_keytest,
"test keymatix and special keys, poweroff on pressing ON key",
"\n"
);
U_BOOT_CMD(
poweroff, 1, 0, do_poweroff,
"power off",
"\n"
);
U_BOOT_CMD(
beep, 3, 0, do_beep,
"[freq [duration]]",
"freq frequence of beep\nduration duration of beep\n"
);
/*****************************************************************************/

23
board/LaCie/common/common.c
View file

@ -20,34 +20,25 @@
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
void mv_phy_88e1116_init(const char *name)
void mv_phy_88e1116_init(const char *name, u16 phyaddr)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..(%s) could not read PHY dev address\n", __func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
if (miiphy_reset(name, phyaddr) == 0)
printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */

2
board/LaCie/common/common.h
View file

@ -11,7 +11,7 @@
#define _LACIE_COMMON_H
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
void mv_phy_88e1116_init(const char *name);
void mv_phy_88e1116_init(const char *name, u16 phyaddr);
#endif
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
int lacie_read_mac_address(uchar *mac);

2
board/LaCie/edminiv2/edminiv2.c
View file

@ -96,6 +96,6 @@ int board_init(void)
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
mv_phy_88e1116_init("egiga0");
mv_phy_88e1116_init("egiga0", 8);
}
#endif /* CONFIG_RESET_PHY_R */

4
board/LaCie/net2big_v2/net2big_v2.c
View file

@ -75,7 +75,7 @@ int board_early_init_f(void)
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
@ -109,7 +109,7 @@ int misc_init_r(void)
/* Configure and initialize PHY */
void reset_phy(void)
{
mv_phy_88e1116_init("egiga0");
mv_phy_88e1116_init("egiga0", 8);
}
#endif

4
board/LaCie/netspace_v2/netspace_v2.c
View file

@ -73,7 +73,7 @@ int board_early_init_f(void)
MPP33_GPIO, /* Fan speed (bit 2) */
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
@ -107,7 +107,7 @@ int misc_init_r(void)
/* Configure and initialize PHY */
void reset_phy(void)
{
mv_phy_88e1116_init("egiga0");
mv_phy_88e1116_init("egiga0", 8);
}
#endif

2
board/Marvell/dreamplug/dreamplug.c
View file

@ -99,7 +99,7 @@ int board_early_init_f(void)
MPP49_GPIO, /* Wifi AP LED */
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}

2
board/Marvell/guruplug/guruplug.c
View file

@ -96,7 +96,7 @@ int board_early_init_f(void)
MPP49_GPIO, /* B_GLED */
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}

2
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
View file

@ -98,7 +98,7 @@ int board_early_init_f(void)
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}

2
board/Marvell/openrd/openrd.c
View file

@ -102,7 +102,7 @@ int board_early_init_f(void)
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}

2
board/Marvell/rd6281a/rd6281a.c
View file

@ -97,7 +97,7 @@ int board_early_init_f(void)
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}

2
board/Marvell/sheevaplug/sheevaplug.c
View file

@ -96,7 +96,7 @@ int board_early_init_f(void)
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}

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