mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
commit
6acc7c3cbc
99 changed files with 5749 additions and 656 deletions
12
MAINTAINERS
12
MAINTAINERS
|
@ -565,6 +565,10 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
|
|||
|
||||
edminiv2 ARM926EJS (Orion5x SoC)
|
||||
|
||||
Raphael Assenat <raph@8d.com>
|
||||
|
||||
eco5pk ARM ARMV7 (AM35x SoC)
|
||||
|
||||
Stefano Babic <sbabic@denx.de>
|
||||
|
||||
ea20 davinci
|
||||
|
@ -896,6 +900,10 @@ Michal Simek <monstr@monstr.eu>
|
|||
|
||||
zynq ARM ARMV7 (Zynq SoC)
|
||||
|
||||
Lucas Stach <dev@lynxeye.de>
|
||||
|
||||
colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)
|
||||
|
||||
Nick Thompson <nick.thompson@gefanuc.com>
|
||||
|
||||
da830evm ARM926EJS (DA830/OMAP-L137)
|
||||
|
@ -1005,6 +1013,10 @@ Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
|||
|
||||
armadillo-800eva R8A7740 (RMOBILE SoC)
|
||||
|
||||
Pali Rohár <pali.rohar@gmail.com>
|
||||
|
||||
nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Unknown / orphaned boards:
|
||||
|
|
17
Makefile
17
Makefile
|
@ -516,16 +516,17 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
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|||
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||||
ifeq ($(SOC),tegra20)
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||||
ifeq ($(CONFIG_OF_SEPARATE),y)
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||||
$(obj)u-boot-dtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)u-boot.dtb
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
|
||||
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(obj)u-boot.dtb > $@
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||||
rm $(obj)spl/u-boot-spl-pad.bin
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||||
nodtb=dtb
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||||
dtbfile=$(obj)u-boot.dtb
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||||
else
|
||||
$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
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||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
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||||
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
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||||
rm $(obj)spl/u-boot-spl-pad.bin
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||||
nodtb=nodtb
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||||
dtbfile=
|
||||
endif
|
||||
|
||||
$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
|
||||
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
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||||
rm $(obj)spl/u-boot-spl-pad.bin
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SANDBOX),y)
|
||||
|
|
4
README
4
README
|
@ -661,6 +661,10 @@ The following options need to be configured:
|
|||
additional board info beside
|
||||
the logo
|
||||
|
||||
When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
|
||||
a limited number of ANSI escape sequences (cursor control,
|
||||
erase functions and limited graphics rendition control).
|
||||
|
||||
When CONFIG_CFB_CONSOLE is defined, video console is
|
||||
default i/o. Serial console can be forced with
|
||||
environment 'console=serial'.
|
||||
|
|
|
@ -361,8 +361,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
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|||
return get_ipg_per_clk();
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||||
case MXC_UART_CLK:
|
||||
return imx_get_uartclk();
|
||||
case MXC_ESDHC_CLK:
|
||||
case MXC_ESDHC1_CLK:
|
||||
return mxc_get_peri_clock(ESDHC1_CLK);
|
||||
case MXC_ESDHC2_CLK:
|
||||
return mxc_get_peri_clock(ESDHC2_CLK);
|
||||
case MXC_ESDHC3_CLK:
|
||||
return mxc_get_peri_clock(ESDHC3_CLK);
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||||
case MXC_USB_CLK:
|
||||
return mxc_get_main_clock(USB_CLK);
|
||||
case MXC_FEC_CLK:
|
||||
|
@ -472,7 +476,13 @@ int cpu_mmc_init(bd_t *bis)
|
|||
int get_clocks(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
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||||
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
|
||||
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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||||
#else
|
||||
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
|
||||
#endif
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -26,6 +26,8 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
void do_irq (struct pt_regs *pt_regs)
|
||||
{
|
||||
|
|
|
@ -23,105 +23,42 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
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||||
#include <asm/u-boot.h>
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||||
#include <asm/utils.h>
|
||||
#include <nand.h>
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||||
#include <mmc.h>
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||||
#include <fat.h>
|
||||
#include <version.h>
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||||
#include <i2c.h>
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||||
#include <image.h>
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||||
#include <malloc.h>
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||||
#include <linux/compiler.h>
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#include "cpu.h"
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pinmux.h>
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||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/board.h>
|
||||
#include <asm/arch-tegra/clk_rst.h>
|
||||
#include <asm/arch-tegra/pmc.h>
|
||||
#include <asm/arch-tegra/scu.h>
|
||||
#include <asm/arch-tegra/sys_proto.h>
|
||||
#include <asm/arch/spl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Define global data structure pointer to it*/
|
||||
static gd_t gdata __attribute__ ((section(".data")));
|
||||
static bd_t bdata __attribute__ ((section(".data")));
|
||||
|
||||
inline void hang(void)
|
||||
{
|
||||
puts("### ERROR ### Please RESET the board ###\n");
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
board_init_uart_f();
|
||||
|
||||
/* Initialize periph GPIOs */
|
||||
gpio_early_init_uart();
|
||||
|
||||
/*
|
||||
* We call relocate_code() with relocation target same as the
|
||||
* CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
|
||||
* skipped. Instead, only .bss initialization will happen. That's
|
||||
* all we need
|
||||
*/
|
||||
debug(">>board_init_f()\n");
|
||||
relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
|
||||
}
|
||||
|
||||
/* This requires UART clocks to be enabled */
|
||||
static void preloader_console_init(void)
|
||||
{
|
||||
const char *u_boot_rev = U_BOOT_VERSION;
|
||||
|
||||
gd = &gdata;
|
||||
gd->bd = &bdata;
|
||||
gd->flags |= GD_FLG_RELOC;
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
|
||||
serial_init(); /* serial communications setup */
|
||||
|
||||
gd->have_console = 1;
|
||||
|
||||
/* Avoid a second "U-Boot" coming from this string */
|
||||
u_boot_rev = &u_boot_rev[7];
|
||||
|
||||
printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
|
||||
U_BOOT_TIME);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *id, ulong dummy)
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
|
||||
/* enable JTAG */
|
||||
writel(0xC0, &pmt->pmt_cfg_ctl);
|
||||
|
||||
debug(">>spl:board_init_r()\n");
|
||||
board_init_uart_f();
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||||
|
||||
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE);
|
||||
|
||||
#ifdef CONFIG_SPL_BOARD_INIT
|
||||
spl_board_init();
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||||
#endif
|
||||
/* Initialize periph GPIOs */
|
||||
gpio_early_init_uart();
|
||||
|
||||
clock_early_init();
|
||||
serial_init();
|
||||
preloader_console_init();
|
||||
|
||||
start_cpu((u32)CONFIG_SYS_TEXT_BASE);
|
||||
halt_avp();
|
||||
/* not reached */
|
||||
}
|
||||
|
||||
int board_usb_init(const void *blob)
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return 0;
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
|
||||
{
|
||||
debug("image entry point: 0x%X\n", spl_image->entry_point);
|
||||
|
||||
start_cpu((u32)spl_image->entry_point);
|
||||
halt_avp();
|
||||
}
|
||||
|
|
|
@ -115,6 +115,41 @@ static void enable_per_clocks(void)
|
|||
while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
|
||||
/* UART1 */
|
||||
#ifdef CONFIG_SERIAL2
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||||
writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
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||||
while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
#endif /* CONFIG_SERIAL2 */
|
||||
|
||||
/* UART2 */
|
||||
#ifdef CONFIG_SERIAL3
|
||||
writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
|
||||
while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
#endif /* CONFIG_SERIAL3 */
|
||||
|
||||
/* UART3 */
|
||||
#ifdef CONFIG_SERIAL4
|
||||
writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
|
||||
while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
#endif /* CONFIG_SERIAL4 */
|
||||
|
||||
/* UART4 */
|
||||
#ifdef CONFIG_SERIAL5
|
||||
writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
|
||||
while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
#endif /* CONFIG_SERIAL5 */
|
||||
|
||||
/* UART5 */
|
||||
#ifdef CONFIG_SERIAL6
|
||||
writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
|
||||
while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
|
||||
;
|
||||
#endif /* CONFIG_SERIAL6 */
|
||||
|
||||
/* MMC0*/
|
||||
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
|
||||
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
|
||||
|
|
|
@ -338,7 +338,7 @@ static u32 get_ipg_per_clk(void)
|
|||
/* Get the output clock rate of a standard PLL MUX for peripherals. */
|
||||
static u32 get_standard_pll_sel_clk(u32 clk_sel)
|
||||
{
|
||||
u32 freq;
|
||||
u32 freq = 0;
|
||||
|
||||
switch (clk_sel & 0x3) {
|
||||
case 0:
|
||||
|
|
|
@ -26,6 +26,13 @@
|
|||
|
||||
.section ".text.init", "x"
|
||||
|
||||
.macro init_arm_erratum
|
||||
/* ARM erratum ID #468414 */
|
||||
mrc 15, 0, r1, c1, c0, 1
|
||||
orr r1, r1, #(1 << 5) /* enable L1NEON bit */
|
||||
mcr 15, 0, r1, c1, c0, 1
|
||||
.endm
|
||||
|
||||
/*
|
||||
* L2CC Cache setup/invalidation/disable
|
||||
*/
|
||||
|
@ -162,9 +169,9 @@ setup_pll_func:
|
|||
.endm
|
||||
|
||||
.macro init_clock
|
||||
#if defined (CONFIG_MX51)
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
|
||||
#if defined(CONFIG_MX51)
|
||||
/* Gate of clocks to the peripherals first */
|
||||
ldr r1, =0x3FFFFFFF
|
||||
str r1, [r0, #CLKCTL_CCGR0]
|
||||
|
@ -190,21 +197,6 @@ setup_pll_func:
|
|||
1: ldr r1, [r0, #CLKCTL_CDHIPR]
|
||||
cmp r1, #0x0
|
||||
bne 1b
|
||||
#else
|
||||
ldr r1, =0x3FFFFFFF
|
||||
str r1, [r0, #CLKCTL_CCGR0]
|
||||
str r4, [r0, #CLKCTL_CCGR1]
|
||||
str r4, [r0, #CLKCTL_CCGR2]
|
||||
str r4, [r0, #CLKCTL_CCGR3]
|
||||
str r4, [r0, #CLKCTL_CCGR7]
|
||||
|
||||
ldr r1, =0x00030000
|
||||
str r1, [r0, #CLKCTL_CCGR4]
|
||||
ldr r1, =0x00FFF030
|
||||
str r1, [r0, #CLKCTL_CCGR5]
|
||||
ldr r1, =0x0F00030F
|
||||
str r1, [r0, #CLKCTL_CCGR6]
|
||||
#endif
|
||||
|
||||
/* Switch ARM to step clock */
|
||||
mov r1, #0x4
|
||||
|
@ -217,7 +209,6 @@ setup_pll_func:
|
|||
setup_pll PLL1_BASE_ADDR, 800
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX51)
|
||||
setup_pll PLL3_BASE_ADDR, 665
|
||||
|
||||
/* Switch peripheral to PLL 3 */
|
||||
|
@ -234,7 +225,7 @@ setup_pll_func:
|
|||
str r1, [r0, #CLKCTL_CBCDR]
|
||||
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
|
||||
str r1, [r0, #CLKCTL_CBCMR]
|
||||
#endif
|
||||
|
||||
setup_pll PLL3_BASE_ADDR, 216
|
||||
|
||||
/* Set the platform clock dividers */
|
||||
|
@ -244,21 +235,17 @@ setup_pll_func:
|
|||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
|
||||
#if defined(CONFIG_MX51)
|
||||
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
|
||||
ldr r3, [r4, #ROM_SI_REV]
|
||||
cmp r3, #0x10
|
||||
movls r1, #0x1
|
||||
movhi r1, #0
|
||||
#else
|
||||
mov r1, #0
|
||||
#endif
|
||||
|
||||
str r1, [r0, #CLKCTL_CACRR]
|
||||
|
||||
/* Switch ARM back to PLL 1 */
|
||||
str r4, [r0, #CLKCTL_CCSR]
|
||||
|
||||
#if defined(CONFIG_MX51)
|
||||
/* setup the rest */
|
||||
/* Use lp_apm (24MHz) source for perclk */
|
||||
ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
|
||||
|
@ -266,7 +253,6 @@ setup_pll_func:
|
|||
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
|
||||
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
|
||||
str r1, [r0, #CLKCTL_CBCDR]
|
||||
#endif
|
||||
|
||||
/* Restore the default values in the Gate registers */
|
||||
ldr r1, =0xFFFFFFFF
|
||||
|
@ -277,36 +263,12 @@ setup_pll_func:
|
|||
str r1, [r0, #CLKCTL_CCGR4]
|
||||
str r1, [r0, #CLKCTL_CCGR5]
|
||||
str r1, [r0, #CLKCTL_CCGR6]
|
||||
#if defined(CONFIG_MX53)
|
||||
str r1, [r0, #CLKCTL_CCGR7]
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX51)
|
||||
/* Use PLL 2 for UART's, get 66.5MHz from it */
|
||||
ldr r1, =0xA5A2A020
|
||||
str r1, [r0, #CLKCTL_CSCMR1]
|
||||
ldr r1, =0x00C30321
|
||||
str r1, [r0, #CLKCTL_CSCDR1]
|
||||
#elif defined(CONFIG_MX53)
|
||||
/* Switch peripheral to PLL2 */
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0x00808145
|
||||
orr r1, r1, #2 << 10
|
||||
orr r1, r1, #1 << 19
|
||||
str r1, [r0, #CLKCTL_CBCDR]
|
||||
|
||||
ldr r1, =0x00016154
|
||||
str r1, [r0, #CLKCTL_CBCMR]
|
||||
/* Change uart clk parent to pll2*/
|
||||
ldr r1, [r0, #CLKCTL_CSCMR1]
|
||||
and r1, r1, #0xfcffffff
|
||||
orr r1, r1, #0x01000000
|
||||
str r1, [r0, #CLKCTL_CSCMR1]
|
||||
ldr r1, [r0, #CLKCTL_CSCDR1]
|
||||
and r1, r1, #0xffffffc0
|
||||
orr r1, r1, #0x0a
|
||||
str r1, [r0, #CLKCTL_CSCDR1]
|
||||
#endif
|
||||
/* make sure divider effective */
|
||||
1: ldr r1, [r0, #CLKCTL_CDHIPR]
|
||||
cmp r1, #0x0
|
||||
|
@ -318,6 +280,110 @@ setup_pll_func:
|
|||
mov r1, #0x000A0000
|
||||
add r1, r1, #0x00000F0
|
||||
str r1, [r0, #CLKCTL_CCOSR]
|
||||
#else /* CONFIG_MX53 */
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
|
||||
/* Gate of clocks to the peripherals first */
|
||||
ldr r1, =0x3FFFFFFF
|
||||
str r1, [r0, #CLKCTL_CCGR0]
|
||||
str r4, [r0, #CLKCTL_CCGR1]
|
||||
str r4, [r0, #CLKCTL_CCGR2]
|
||||
str r4, [r0, #CLKCTL_CCGR3]
|
||||
str r4, [r0, #CLKCTL_CCGR7]
|
||||
ldr r1, =0x00030000
|
||||
str r1, [r0, #CLKCTL_CCGR4]
|
||||
ldr r1, =0x00FFF030
|
||||
str r1, [r0, #CLKCTL_CCGR5]
|
||||
ldr r1, =0x0F00030F
|
||||
str r1, [r0, #CLKCTL_CCGR6]
|
||||
|
||||
/* Switch ARM to step clock */
|
||||
mov r1, #0x4
|
||||
str r1, [r0, #CLKCTL_CCSR]
|
||||
|
||||
setup_pll PLL1_BASE_ADDR, 800
|
||||
|
||||
setup_pll PLL3_BASE_ADDR, 400
|
||||
|
||||
/* Switch peripheral to PLL3 */
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0x00015154
|
||||
str r1, [r0, #CLKCTL_CBCMR]
|
||||
ldr r1, =0x02888945
|
||||
orr r1, r1, #(1 << 16)
|
||||
str r1, [r0, #CLKCTL_CBCDR]
|
||||
/* make sure change is effective */
|
||||
1: ldr r1, [r0, #CLKCTL_CDHIPR]
|
||||
cmp r1, #0x0
|
||||
bne 1b
|
||||
|
||||
setup_pll PLL2_BASE_ADDR, 400
|
||||
|
||||
/* Switch peripheral to PLL2 */
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0x00808145
|
||||
orr r1, r1, #(2 << 10)
|
||||
orr r1, r1, #(0 << 16)
|
||||
orr r1, r1, #(1 << 19)
|
||||
str r1, [r0, #CLKCTL_CBCDR]
|
||||
|
||||
ldr r1, =0x00016154
|
||||
str r1, [r0, #CLKCTL_CBCMR]
|
||||
|
||||
/*change uart clk parent to pll2*/
|
||||
ldr r1, [r0, #CLKCTL_CSCMR1]
|
||||
and r1, r1, #0xfcffffff
|
||||
orr r1, r1, #0x01000000
|
||||
str r1, [r0, #CLKCTL_CSCMR1]
|
||||
|
||||
/* make sure change is effective */
|
||||
1: ldr r1, [r0, #CLKCTL_CDHIPR]
|
||||
cmp r1, #0x0
|
||||
bne 1b
|
||||
|
||||
setup_pll PLL3_BASE_ADDR, 216
|
||||
|
||||
setup_pll PLL4_BASE_ADDR, 455
|
||||
|
||||
/* Set the platform clock dividers */
|
||||
ldr r0, =ARM_BASE_ADDR
|
||||
ldr r1, =0x00000124
|
||||
str r1, [r0, #0x14]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0
|
||||
str r1, [r0, #CLKCTL_CACRR]
|
||||
|
||||
/* Switch ARM back to PLL 1. */
|
||||
mov r1, #0x0
|
||||
str r1, [r0, #CLKCTL_CCSR]
|
||||
|
||||
/* make uart div=6 */
|
||||
ldr r1, [r0, #CLKCTL_CSCDR1]
|
||||
and r1, r1, #0xffffffc0
|
||||
orr r1, r1, #0x0a
|
||||
str r1, [r0, #CLKCTL_CSCDR1]
|
||||
|
||||
/* Restore the default values in the Gate registers */
|
||||
ldr r1, =0xFFFFFFFF
|
||||
str r1, [r0, #CLKCTL_CCGR0]
|
||||
str r1, [r0, #CLKCTL_CCGR1]
|
||||
str r1, [r0, #CLKCTL_CCGR2]
|
||||
str r1, [r0, #CLKCTL_CCGR3]
|
||||
str r1, [r0, #CLKCTL_CCGR4]
|
||||
str r1, [r0, #CLKCTL_CCGR5]
|
||||
str r1, [r0, #CLKCTL_CCGR6]
|
||||
str r1, [r0, #CLKCTL_CCGR7]
|
||||
|
||||
mov r1, #0x00000
|
||||
str r1, [r0, #CLKCTL_CCDR]
|
||||
|
||||
/* for cko - for ARM div by 8 */
|
||||
mov r1, #0x000A0000
|
||||
add r1, r1, #0x00000F0
|
||||
str r1, [r0, #CLKCTL_CCOSR]
|
||||
|
||||
#endif /* CONFIG_MX53 */
|
||||
.endm
|
||||
|
||||
.macro setup_wdog
|
||||
|
@ -340,6 +406,8 @@ ENTRY(lowlevel_init)
|
|||
str r1, [r0, #0x4]
|
||||
#endif
|
||||
|
||||
init_arm_erratum
|
||||
|
||||
init_l2cc
|
||||
|
||||
init_aips
|
||||
|
@ -370,3 +438,9 @@ W_DP_665: .word DP_OP_665
|
|||
W_DP_216: .word DP_OP_216
|
||||
.word DP_MFD_216
|
||||
.word DP_MFN_216
|
||||
W_DP_400: .word DP_OP_400
|
||||
.word DP_MFD_400
|
||||
.word DP_MFN_400
|
||||
W_DP_455: .word DP_OP_455
|
||||
.word DP_MFD_455
|
||||
.word DP_MFN_455
|
||||
|
|
|
@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
/* Declarations */
|
||||
extern omap3_sysinfo sysinfo;
|
||||
static void omap3_setup_aux_cr(void);
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
static void omap3_invalidate_l2_cache_secure(void);
|
||||
#endif
|
||||
|
||||
static const struct gpio_bank gpio_bank_34xx[6] = {
|
||||
{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
|
||||
|
@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
|
|||
}
|
||||
}
|
||||
|
||||
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
|
||||
{
|
||||
u32 acr;
|
||||
|
||||
/* Read ACR */
|
||||
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
|
||||
acr &= ~clear_bits;
|
||||
acr |= set_bits;
|
||||
|
||||
/* Write ACR - affects non-secure banked bits */
|
||||
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
|
||||
}
|
||||
|
||||
static void omap3_setup_aux_cr(void)
|
||||
{
|
||||
/* Workaround for Cortex-A8 errata: #454179 #430973
|
||||
|
@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
|
|||
}
|
||||
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
|
||||
{
|
||||
u32 acr;
|
||||
|
||||
/* Read ACR */
|
||||
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
|
||||
acr &= ~clear_bits;
|
||||
acr |= set_bits;
|
||||
|
||||
/* Write ACR - affects non-secure banked bits */
|
||||
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
|
||||
}
|
||||
|
||||
/* Invalidate the entire L2 cache from secure mode */
|
||||
static void omap3_invalidate_l2_cache_secure(void)
|
||||
{
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <asm/utils.h>
|
||||
#include <version.h>
|
||||
#include <image.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/arch/reset_manager.h>
|
||||
#include <spl.h>
|
||||
|
||||
|
@ -37,9 +36,6 @@ u32 spl_boot_device(void)
|
|||
*/
|
||||
void spl_board_init(void)
|
||||
{
|
||||
/* init timer for enabling delay function */
|
||||
timer_init();
|
||||
|
||||
/* de-assert reset for peripherals and bridges based on handoff */
|
||||
reset_deassert_peripherals_handoff();
|
||||
|
||||
|
|
|
@ -257,7 +257,7 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
|
|||
int tegra_set_emc(const void *blob, unsigned rate)
|
||||
{
|
||||
struct emc_ctlr *emc;
|
||||
const u32 *table;
|
||||
const u32 *table = NULL;
|
||||
int err, i;
|
||||
|
||||
err = decode_emc(blob, rate, &emc, &table);
|
||||
|
|
|
@ -94,3 +94,7 @@ SECTIONS
|
|||
/DISCARD/ : { *(.interp*) }
|
||||
/DISCARD/ : { *(.gnu*) }
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
|
||||
ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
|
||||
#endif
|
||||
|
|
|
@ -54,9 +54,10 @@ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
|
||||
unsigned count)
|
||||
{
|
||||
iomux_v3_cfg_t *p = pad_list;
|
||||
iomux_v3_cfg_t const *p = pad_list;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* Copyright (C) 2009, DENX Software Engineering
|
||||
* Author: John Rigby <jcrigby@gmail.com
|
||||
*
|
||||
* Based on arch-mx31/mx31-regs.h
|
||||
* Based on arch-mx31/imx-regs.h
|
||||
* Copyright (C) 2009 Ilya Yanok,
|
||||
* Emcraft Systems <yanok@emcraft.com>
|
||||
* and arch-mx27/imx-regs.h
|
||||
|
@ -33,8 +33,7 @@
|
|||
#ifndef _IMX_REGS_H
|
||||
#define _IMX_REGS_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
|
@ -254,6 +253,7 @@ struct aips_regs {
|
|||
|
||||
/* 128K Internal Static RAM */
|
||||
#define IMX_RAM_BASE (0x78000000)
|
||||
#define IMX_RAM_SIZE (128 * 1024)
|
||||
|
||||
/* SDRAM BANKS */
|
||||
#define IMX_SDRAM_BANK0_BASE (0x80000000)
|
||||
|
|
|
@ -44,7 +44,9 @@ enum mxc_clock {
|
|||
MXC_IPG_CLK,
|
||||
MXC_IPG_PERCLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_ESDHC1_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_ESDHC3_CLK,
|
||||
MXC_USB_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_FEC_CLK,
|
||||
|
|
|
@ -19,122 +19,121 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
/*
|
||||
* AIPS setup - Only setup MPROTx registers.
|
||||
* The PACR default values are good.
|
||||
*
|
||||
* Default argument values:
|
||||
* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
|
||||
* user-mode.
|
||||
* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
|
||||
* SDMA to access them.
|
||||
*/
|
||||
.macro init_aips
|
||||
/*
|
||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||
* not forced to user-mode.
|
||||
*/
|
||||
ldr r0, =AIPS1_BASE_ADDR
|
||||
ldr r1, =AIPS_MPR_CONFIG
|
||||
str r1, [r0, #0x00]
|
||||
str r1, [r0, #0x04]
|
||||
ldr r0, =AIPS2_BASE_ADDR
|
||||
str r1, [r0, #0x00]
|
||||
str r1, [r0, #0x04]
|
||||
.macro init_aips mpr=0x77777777, opacr=0x00000000
|
||||
ldr r0, =AIPS1_BASE_ADDR
|
||||
ldr r1, =\mpr
|
||||
str r1, [r0, #AIPS_MPR_0_7]
|
||||
str r1, [r0, #AIPS_MPR_8_15]
|
||||
ldr r2, =AIPS2_BASE_ADDR
|
||||
str r1, [r2, #AIPS_MPR_0_7]
|
||||
str r1, [r2, #AIPS_MPR_8_15]
|
||||
|
||||
/*
|
||||
* Clear the on and off peripheral modules Supervisor Protect bit
|
||||
* for SDMA to access them. Did not change the AIPS control registers
|
||||
* (offset 0x20) access type
|
||||
*/
|
||||
ldr r0, =AIPS1_BASE_ADDR
|
||||
ldr r1, =AIPS_OPACR_CONFIG
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4C]
|
||||
str r1, [r0, #0x50]
|
||||
ldr r0, =AIPS2_BASE_ADDR
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4C]
|
||||
str r1, [r0, #0x50]
|
||||
/* Did not change the AIPS control registers access type. */
|
||||
ldr r1, =\opacr
|
||||
str r1, [r0, #AIPS_OPACR_0_7]
|
||||
str r1, [r0, #AIPS_OPACR_8_15]
|
||||
str r1, [r0, #AIPS_OPACR_16_23]
|
||||
str r1, [r0, #AIPS_OPACR_24_31]
|
||||
str r1, [r0, #AIPS_OPACR_32_39]
|
||||
str r1, [r2, #AIPS_OPACR_0_7]
|
||||
str r1, [r2, #AIPS_OPACR_8_15]
|
||||
str r1, [r2, #AIPS_OPACR_16_23]
|
||||
str r1, [r2, #AIPS_OPACR_24_31]
|
||||
str r1, [r2, #AIPS_OPACR_32_39]
|
||||
.endm
|
||||
|
||||
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
|
||||
.macro init_max
|
||||
ldr r0, =MAX_BASE_ADDR
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
ldr r1, =MAX_MPR_CONFIG
|
||||
str r1, [r0, #0x000] /* for S0 */
|
||||
str r1, [r0, #0x100] /* for S1 */
|
||||
str r1, [r0, #0x200] /* for S2 */
|
||||
str r1, [r0, #0x300] /* for S3 */
|
||||
str r1, [r0, #0x400] /* for S4 */
|
||||
/* SGPCR - always park on last master */
|
||||
ldr r1, =MAX_SGPCR_CONFIG
|
||||
str r1, [r0, #0x010] /* for S0 */
|
||||
str r1, [r0, #0x110] /* for S1 */
|
||||
str r1, [r0, #0x210] /* for S2 */
|
||||
str r1, [r0, #0x310] /* for S3 */
|
||||
str r1, [r0, #0x410] /* for S4 */
|
||||
/* MGPCR - restore default values */
|
||||
ldr r1, =MAX_MGPCR_CONFIG
|
||||
str r1, [r0, #0x800] /* for M0 */
|
||||
str r1, [r0, #0x900] /* for M1 */
|
||||
str r1, [r0, #0xA00] /* for M2 */
|
||||
str r1, [r0, #0xB00] /* for M3 */
|
||||
str r1, [r0, #0xC00] /* for M4 */
|
||||
str r1, [r0, #0xD00] /* for M5 */
|
||||
/*
|
||||
* MAX (Multi-Layer AHB Crossbar Switch) setup
|
||||
*
|
||||
* Default argument values:
|
||||
* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
|
||||
* - SGPCR: always park on last master
|
||||
* - MGPCR: restore default values
|
||||
*/
|
||||
.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
|
||||
ldr r0, =MAX_BASE_ADDR
|
||||
ldr r1, =\mpr
|
||||
str r1, [r0, #MAX_MPR0] /* for S0 */
|
||||
str r1, [r0, #MAX_MPR1] /* for S1 */
|
||||
str r1, [r0, #MAX_MPR2] /* for S2 */
|
||||
str r1, [r0, #MAX_MPR3] /* for S3 */
|
||||
str r1, [r0, #MAX_MPR4] /* for S4 */
|
||||
ldr r1, =\sgpcr
|
||||
str r1, [r0, #MAX_SGPCR0] /* for S0 */
|
||||
str r1, [r0, #MAX_SGPCR1] /* for S1 */
|
||||
str r1, [r0, #MAX_SGPCR2] /* for S2 */
|
||||
str r1, [r0, #MAX_SGPCR3] /* for S3 */
|
||||
str r1, [r0, #MAX_SGPCR4] /* for S4 */
|
||||
ldr r1, =\mgpcr
|
||||
str r1, [r0, #MAX_MGPCR0] /* for M0 */
|
||||
str r1, [r0, #MAX_MGPCR1] /* for M1 */
|
||||
str r1, [r0, #MAX_MGPCR2] /* for M2 */
|
||||
str r1, [r0, #MAX_MGPCR3] /* for M3 */
|
||||
str r1, [r0, #MAX_MGPCR4] /* for M4 */
|
||||
str r1, [r0, #MAX_MGPCR5] /* for M5 */
|
||||
.endm
|
||||
|
||||
/* M3IF setup */
|
||||
.macro init_m3if
|
||||
/* Configure M3IF registers */
|
||||
ldr r1, =M3IF_BASE_ADDR
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
ldr r0, =M3IF_CONFIG
|
||||
str r0, [r1] /* M3IF control reg */
|
||||
/*
|
||||
* M3IF setup
|
||||
*
|
||||
* Default argument values:
|
||||
* - CTL:
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
.macro init_m3if ctl=0x00000040
|
||||
/* M3IF Control Register (M3IFCTL) */
|
||||
write32 M3IF_BASE_ADDR, \ctl
|
||||
.endm
|
||||
|
||||
.macro core_init
|
||||
mrc 15, 0, r1, c1, c0, 0
|
||||
|
||||
mrc 15, 0, r0, c1, c0, 1
|
||||
orr r0, r0, #7
|
||||
mcr 15, 0, r0, c1, c0, 1
|
||||
orr r1, r1, #(1<<11)
|
||||
|
||||
/* Set unaligned access enable */
|
||||
orr r1, r1, #(1<<22)
|
||||
|
||||
/* Set low int latency enable */
|
||||
orr r1, r1, #(1<<21)
|
||||
|
||||
mcr 15, 0, r1, c1, c0, 0
|
||||
|
||||
mov r0, #0
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
|
||||
/* Set branch prediction enable */
|
||||
mcr 15, 0, r0, c15, c2, 4
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
orr r0, r0, #7
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
orr r1, r1, #1 << 11
|
||||
|
||||
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
|
||||
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
|
||||
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
|
||||
/* Set unaligned access enable */
|
||||
orr r1, r1, #1 << 22
|
||||
|
||||
/*
|
||||
* initializes very early AIPS
|
||||
* Then it also initializes Multi-Layer AHB Crossbar Switch,
|
||||
* M3IF
|
||||
* Also setup the Peripheral Port Remap register inside the core
|
||||
*/
|
||||
ldr r0, =0x40000015 /* start from AIPS 2GB region */
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
/* Set low int latency enable */
|
||||
orr r1, r1, #1 << 21
|
||||
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
|
||||
mov r0, #0
|
||||
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
|
||||
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
|
||||
mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
|
||||
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
|
||||
|
||||
/* Setup the Peripheral Port Memory Remap Register */
|
||||
ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
.endm
|
||||
|
|
|
@ -308,6 +308,10 @@
|
|||
#define DP_MFD_400 (3 - 1)
|
||||
#define DP_MFN_400 1
|
||||
|
||||
#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
|
||||
#define DP_MFD_455 (48 - 1)
|
||||
#define DP_MFN_455 23
|
||||
|
||||
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
|
||||
#define DP_MFD_216 (4 - 1)
|
||||
#define DP_MFN_216 3
|
||||
|
|
|
@ -200,6 +200,12 @@ struct src {
|
|||
u32 gpr10;
|
||||
};
|
||||
|
||||
/* OCOTP Registers */
|
||||
struct ocotp_regs {
|
||||
u32 reserved[0x198];
|
||||
u32 gp1; /* 0x660 */
|
||||
};
|
||||
|
||||
/* GPR3 bitfields */
|
||||
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
|
||||
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
|
||||
|
|
|
@ -530,20 +530,20 @@ enum {
|
|||
MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
|
||||
|
@ -551,7 +551,7 @@ enum {
|
|||
MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
|
||||
|
@ -564,17 +564,17 @@ enum {
|
|||
MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
|
||||
|
@ -582,7 +582,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
|
||||
|
@ -590,7 +590,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
|
||||
|
@ -598,7 +598,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
|
||||
|
@ -606,7 +606,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
|
||||
|
@ -614,7 +614,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
|
||||
|
@ -622,7 +622,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
|
||||
|
@ -630,7 +630,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
|
||||
|
@ -638,7 +638,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
|
||||
|
@ -646,41 +646,41 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
|
||||
|
@ -688,7 +688,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
|
||||
|
@ -696,7 +696,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
|
||||
|
@ -704,7 +704,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
|
||||
|
@ -712,7 +712,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
|
||||
|
@ -720,7 +720,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
|
||||
|
@ -728,7 +728,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
|
||||
|
@ -736,7 +736,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
|
||||
|
@ -744,7 +744,7 @@ enum {
|
|||
MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
|
||||
MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
|
||||
MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
|
||||
|
|
1053
arch/arm/include/asm/arch-mx6/mxc_hdmi.h
Normal file
1053
arch/arm/include/asm/arch-mx6/mxc_hdmi.h
Normal file
File diff suppressed because it is too large
Load diff
28
arch/arm/include/asm/arch-tegra20/spl.h
Normal file
28
arch/arm/include/asm/arch-tegra20/spl.h
Normal file
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif
|
|
@ -98,6 +98,7 @@ typedef u64 iomux_v3_cfg_t;
|
|||
#define MUX_CONFIG_SION (0x1 << 4)
|
||||
|
||||
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
|
||||
unsigned count);
|
||||
|
||||
#endif /* __MACH_IOMUX_V3_H__*/
|
||||
|
|
|
@ -267,3 +267,8 @@ struct meminfo {
|
|||
extern struct meminfo meminfo;
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Board specified tags
|
||||
*/
|
||||
void setup_board_tags(struct tag **in_params);
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/bootm.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -269,6 +270,8 @@ static int create_fdt(bootm_headers_t *images)
|
|||
}
|
||||
#endif
|
||||
|
||||
__weak void setup_board_tags(struct tag **in_params) {}
|
||||
|
||||
/* Subcommand: PREP */
|
||||
static void boot_prep_linux(bootm_headers_t *images)
|
||||
{
|
||||
|
@ -310,6 +313,7 @@ static void boot_prep_linux(bootm_headers_t *images)
|
|||
setup_initrd_tag(gd->bd, images->rd_start,
|
||||
images->rd_end);
|
||||
#endif
|
||||
setup_board_tags(¶ms);
|
||||
setup_end_tag(gd->bd);
|
||||
#else /* all tags */
|
||||
printf("FDT and ATAGS support not compiled in - hanging\n");
|
||||
|
|
43
board/8dtech/eco5pk/Makefile
Normal file
43
board/8dtech/eco5pk/Makefile
Normal file
|
@ -0,0 +1,43 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Adapted from ti/evm/Makefile
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := eco5pk.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
61
board/8dtech/eco5pk/eco5pk.c
Normal file
61
board/8dtech/eco5pk/eco5pk.c
Normal file
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
|
||||
*
|
||||
* Based on am3517evm.c
|
||||
*
|
||||
* Copyright (C) 2011-2012 8D Technologies inc.
|
||||
* Copyright (C) 2009 Texas Instruments Incorporated
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
#include <crc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "eco5pk.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
gpio_request(30, "RESOUT");
|
||||
gpio_direction_output(30, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_ECO5_PK();
|
||||
}
|
404
board/8dtech/eco5pk/eco5pk.h
Normal file
404
board/8dtech/eco5pk/eco5pk.h
Normal file
|
@ -0,0 +1,404 @@
|
|||
/*
|
||||
* eco5.h - Header file for the 8D Technologies ECO5 board.
|
||||
*
|
||||
* Based on am3517evm.h
|
||||
* Based on ti/evm/evm.h
|
||||
*
|
||||
* Copyright (C) 2011 8D Technologies inc.
|
||||
* Copyright (C) 2009 Texas Instruments Incorporated
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef _ECO5PK_H__
|
||||
#define _ECO5PK_H__
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
DDR_DISCRETE,
|
||||
"ECO5 Board",
|
||||
"NAND",
|
||||
};
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_ECO5_PK() \
|
||||
/* SDRC */\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SDRC_CKE0), (M0)) \
|
||||
MUX_VAL(CP(SDRC_CKE1), (M0)) \
|
||||
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
|
||||
/* GPMC */\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
|
||||
/* - ETH_nRESET*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
|
||||
/* DSS */\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
|
||||
/* CAMERA */\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
|
||||
/* - CAM_RESET*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
|
||||
/* MMC */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
|
||||
/* McBSP */\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
|
||||
/* - LCD_INI*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
|
||||
/* - LCD_ENVDD */\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
|
||||
/* - LCD_QVGA/nVGA */\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
|
||||
/* - LCD_RESB */\
|
||||
/* UART */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
/* I2C */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
/* McSPI */\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
|
||||
/* - LAN_INTR*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
|
||||
/* LCD_EN_BACKLIGHT */\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \
|
||||
/* CCDC */\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
/* RMII */\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
|
||||
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
|
||||
/* HECC */\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
|
||||
/* HSUSB */\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
|
||||
/* HDQ */\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
|
||||
/* SYS_nRESWARM */\
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
|
||||
/* - GPIO30 */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
|
||||
/* - PEN_IRQ */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\
|
||||
/* - VIO_1V8*/\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
|
||||
/* JTAG */\
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
|
||||
/* ETK (ES2 onwards) */\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
|
||||
/* Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))
|
||||
|
||||
#endif
|
|
@ -22,47 +22,6 @@
|
|||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm-offsets.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
|
||||
/*
|
||||
* Configuration for the flea3 board.
|
||||
* These defines are used by the included macros and must
|
||||
* be defined first
|
||||
*/
|
||||
#define AIPS_MPR_CONFIG 0x77777777
|
||||
#define AIPS_OPACR_CONFIG 0x00000000
|
||||
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
#define MAX_MPR_CONFIG 0x00302154
|
||||
|
||||
/* SGPCR - always park on last master */
|
||||
#define MAX_SGPCR_CONFIG 0x00000010
|
||||
|
||||
/* MGPCR - restore default values */
|
||||
#define MAX_MGPCR_CONFIG 0x00000000
|
||||
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
#define M3IF_CONFIG 0x00000040
|
||||
|
||||
#define CCM_PDR0_CONFIG 0x00801000
|
||||
|
||||
/*
|
||||
* includes MX35 utility macros
|
||||
*/
|
||||
#include <asm/arch/lowlevel_macro.S>
|
||||
|
||||
.globl lowlevel_init
|
||||
|
|
|
@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
|||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := ../../nvidia/common/board.o
|
||||
COBJS += ../common/tamonten.o
|
||||
COBJS-y := ../common/tamonten.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
|
|
|
@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
|||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := ../../nvidia/common/board.o
|
||||
COBJS += ../common/tamonten.o
|
||||
COBJS-y := ../common/tamonten.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
|
|
|
@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
|||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := ../../nvidia/common/board.o
|
||||
COBJS += ../common/tamonten.o
|
||||
COBJS-y := ../common/tamonten.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
|
|
|
@ -20,9 +20,11 @@ $(shell mkdir -p $(obj)../../nvidia/common)
|
|||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
COBJS += ../../nvidia/common/board.o
|
||||
COBJS-y := $(BOARD).o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
|
|
|
@ -28,9 +28,11 @@ $(shell mkdir -p $(obj)../../nvidia/common)
|
|||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
COBJS += ../../nvidia/common/board.o
|
||||
COBJS-y := $(BOARD).o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
|
|
|
@ -217,6 +217,7 @@ int board_mmc_init(bd_t *bis)
|
|||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||
|
||||
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <asm/arch/imx-regs.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
#include "mx35pdk.h"
|
||||
#include <asm/arch/lowlevel_macro.S>
|
||||
|
||||
/*
|
||||
* return soc version
|
||||
|
@ -40,91 +41,6 @@
|
|||
addne \ret, \ret, #0x10
|
||||
.endm
|
||||
|
||||
/*
|
||||
* AIPS setup - Only setup MPROTx registers.
|
||||
* The PACR default values are good.
|
||||
*/
|
||||
.macro init_aips
|
||||
/*
|
||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||
* not forced to user-mode.
|
||||
*/
|
||||
ldr r0, =AIPS1_BASE_ADDR
|
||||
ldr r1, =AIPS_MPR_CONFIG
|
||||
str r1, [r0, #0x00]
|
||||
str r1, [r0, #0x04]
|
||||
ldr r0, =AIPS2_BASE_ADDR
|
||||
str r1, [r0, #0x00]
|
||||
str r1, [r0, #0x04]
|
||||
|
||||
/*
|
||||
* Clear the on and off peripheral modules Supervisor Protect bit
|
||||
* for SDMA to access them. Did not change the AIPS control registers
|
||||
* (offset 0x20) access type
|
||||
*/
|
||||
ldr r0, =AIPS1_BASE_ADDR
|
||||
ldr r1, =AIPS_OPACR_CONFIG
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4C]
|
||||
str r1, [r0, #0x50]
|
||||
ldr r0, =AIPS2_BASE_ADDR
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4C]
|
||||
str r1, [r0, #0x50]
|
||||
.endm
|
||||
|
||||
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
|
||||
.macro init_max
|
||||
ldr r0, =MAX_BASE_ADDR
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
ldr r1, =MAX_MPR_CONFIG
|
||||
str r1, [r0, #0x000] /* for S0 */
|
||||
str r1, [r0, #0x100] /* for S1 */
|
||||
str r1, [r0, #0x200] /* for S2 */
|
||||
str r1, [r0, #0x300] /* for S3 */
|
||||
str r1, [r0, #0x400] /* for S4 */
|
||||
/* SGPCR - always park on last master */
|
||||
ldr r1, =MAX_SGPCR_CONFIG
|
||||
str r1, [r0, #0x010] /* for S0 */
|
||||
str r1, [r0, #0x110] /* for S1 */
|
||||
str r1, [r0, #0x210] /* for S2 */
|
||||
str r1, [r0, #0x310] /* for S3 */
|
||||
str r1, [r0, #0x410] /* for S4 */
|
||||
/* MGPCR - restore default values */
|
||||
ldr r1, =MAX_MGPCR_CONFIG
|
||||
str r1, [r0, #0x800] /* for M0 */
|
||||
str r1, [r0, #0x900] /* for M1 */
|
||||
str r1, [r0, #0xA00] /* for M2 */
|
||||
str r1, [r0, #0xB00] /* for M3 */
|
||||
str r1, [r0, #0xC00] /* for M4 */
|
||||
str r1, [r0, #0xD00] /* for M5 */
|
||||
.endm
|
||||
|
||||
/* M3IF setup */
|
||||
.macro init_m3if
|
||||
/* Configure M3IF registers */
|
||||
ldr r1, =M3IF_BASE_ADDR
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
ldr r0, =M3IF_CONFIG
|
||||
str r0, [r1] /* M3IF control reg */
|
||||
.endm
|
||||
|
||||
/* CPLD on CS5 setup */
|
||||
.macro init_debug_board
|
||||
ldr r0, =DBG_BASE_ADDR
|
||||
|
@ -210,38 +126,7 @@
|
|||
lowlevel_init:
|
||||
mov r10, lr
|
||||
|
||||
mrc 15, 0, r1, c1, c0, 0
|
||||
|
||||
mrc 15, 0, r0, c1, c0, 1
|
||||
orr r0, r0, #7
|
||||
mcr 15, 0, r0, c1, c0, 1
|
||||
orr r1, r1, #(1<<11)
|
||||
|
||||
/* Set unaligned access enable */
|
||||
orr r1, r1, #(1<<22)
|
||||
|
||||
/* Set low int latency enable */
|
||||
orr r1, r1, #(1<<21)
|
||||
|
||||
mcr 15, 0, r1, c1, c0, 0
|
||||
|
||||
mov r0, #0
|
||||
|
||||
/* Set branch prediction enable */
|
||||
mcr 15, 0, r0, c15, c2, 4
|
||||
|
||||
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
|
||||
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
|
||||
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
|
||||
|
||||
/*
|
||||
* initializes very early AIPS
|
||||
* Then it also initializes Multi-Layer AHB Crossbar Switch,
|
||||
* M3IF
|
||||
* Also setup the Peripheral Port Remap register inside the core
|
||||
*/
|
||||
ldr r0, =0x40000015 /* start from AIPS 2GB region */
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
core_init
|
||||
|
||||
init_aips
|
||||
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <asm/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mx35_pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <i2c.h>
|
||||
|
@ -292,6 +293,7 @@ int board_mmc_init(bd_t *bis)
|
|||
mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
|
||||
|
||||
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
|
||||
|
|
|
@ -26,31 +26,6 @@
|
|||
#ifndef __BOARD_MX35_3STACK_H
|
||||
#define __BOARD_MX35_3STACK_H
|
||||
|
||||
#define AIPS_MPR_CONFIG 0x77777777
|
||||
#define AIPS_OPACR_CONFIG 0x00000000
|
||||
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
#define MAX_MPR_CONFIG 0x00302154
|
||||
/* SGPCR - always park on last master */
|
||||
#define MAX_SGPCR_CONFIG 0x00000010
|
||||
/* MGPCR - restore default values */
|
||||
#define MAX_MGPCR_CONFIG 0x00000000
|
||||
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
#define M3IF_CONFIG 0x00000040
|
||||
|
||||
#define DBG_BASE_ADDR WEIM_CTRL_CS5
|
||||
#define DBG_CSCR_U_CONFIG 0x0000D843
|
||||
#define DBG_CSCR_L_CONFIG 0x22252521
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#include <asm/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
|
@ -358,6 +359,9 @@ int board_mmc_init(bd_t *bis)
|
|||
u32 index;
|
||||
s32 status = 0;
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
|
||||
index++) {
|
||||
switch (index) {
|
||||
|
@ -467,7 +471,7 @@ int board_mmc_init(bd_t *bis)
|
|||
}
|
||||
#endif
|
||||
|
||||
static struct fb_videomode claa_wvga = {
|
||||
static struct fb_videomode const claa_wvga = {
|
||||
.name = "CLAA07LC0ACW",
|
||||
.refresh = 57,
|
||||
.xres = 800,
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/errno.h>
|
||||
#include <netdev.h>
|
||||
|
@ -106,6 +107,9 @@ int board_mmc_init(bd_t *bis)
|
|||
u32 index;
|
||||
s32 status = 0;
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
|
@ -232,6 +233,9 @@ int board_mmc_init(bd_t *bis)
|
|||
u32 index;
|
||||
s32 status = 0;
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
|
|
|
@ -192,6 +192,9 @@ int board_mmc_init(bd_t *bis)
|
|||
u32 index;
|
||||
s32 status = 0;
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
|
@ -409,7 +412,7 @@ static void clock_1GHz(void)
|
|||
printf("CPU: Switch DDR clock to 400MHz failed\n");
|
||||
}
|
||||
|
||||
static struct fb_videomode claa_wvga = {
|
||||
static struct fb_videomode const claa_wvga = {
|
||||
.name = "CLAA07LC0ACW",
|
||||
.refresh = 57,
|
||||
.xres = 800,
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/errno.h>
|
||||
#include <netdev.h>
|
||||
|
@ -144,6 +145,8 @@ int board_mmc_init(bd_t *bis)
|
|||
u32 index;
|
||||
s32 status = 0;
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
@ -53,12 +54,12 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t uart4_pads[] = {
|
||||
iomux_v3_cfg_t const uart4_pads[] = {
|
||||
MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
@ -72,7 +73,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
|
|||
MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t usdhc4_pads[] = {
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
@ -85,7 +86,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
|
|||
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t enet_pads[] = {
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
@ -139,6 +140,9 @@ int board_mmc_init(bd_t *bis)
|
|||
s32 status = 0;
|
||||
u32 index = 0;
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
|
|
|
@ -30,6 +30,8 @@
|
|||
#include <fsl_esdhc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
|
@ -51,12 +53,12 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t uart4_pads[] = {
|
||||
iomux_v3_cfg_t const uart4_pads[] = {
|
||||
MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t enet_pads[] = {
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
@ -79,7 +81,7 @@ static void setup_iomux_enet(void)
|
|||
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
@ -114,6 +116,7 @@ int board_mmc_init(bd_t *bis)
|
|||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
|
@ -164,9 +167,38 @@ int board_eth_init(bd_t *bis)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#define BOARD_REV_B 0x200
|
||||
#define BOARD_REV_A 0x100
|
||||
|
||||
static int mx6sabre_rev(void)
|
||||
{
|
||||
/*
|
||||
* Get Board ID information from OCOTP_GP1[15:8]
|
||||
* i.MX6Q ARD RevA: 0x01
|
||||
* i.MX6Q ARD RevB: 0x02
|
||||
*/
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
int reg = readl(&ocotp->gp1);
|
||||
int ret;
|
||||
|
||||
switch (reg >> 8 & 0x0F) {
|
||||
case 0x02:
|
||||
ret = BOARD_REV_B;
|
||||
break;
|
||||
case 0x01:
|
||||
default:
|
||||
ret = BOARD_REV_A;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return 0x63000;
|
||||
int rev = mx6sabre_rev();
|
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | rev;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
|
@ -186,7 +218,20 @@ int board_init(void)
|
|||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6Q-Sabreauto\n");
|
||||
int rev = mx6sabre_rev();
|
||||
char *revname;
|
||||
|
||||
switch (rev) {
|
||||
case BOARD_REV_B:
|
||||
revname = "B";
|
||||
break;
|
||||
case BOARD_REV_A:
|
||||
default:
|
||||
revname = "A";
|
||||
break;
|
||||
}
|
||||
|
||||
printf("Board: MX6Q-Sabreauto rev%s\n", revname);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -36,6 +36,12 @@
|
|||
#include <micrel.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/fb.h>
|
||||
#include <ipu_pixfmt.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mxc_hdmi.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
|
@ -70,12 +76,12 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t uart1_pads[] = {
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t uart2_pads[] = {
|
||||
iomux_v3_cfg_t const uart2_pads[] = {
|
||||
MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
@ -124,7 +130,7 @@ struct i2c_pads_info i2c_pad_info2 = {
|
|||
}
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
@ -134,7 +140,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
|
|||
MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t usdhc4_pads[] = {
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
@ -144,7 +150,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
|
|||
MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t enet_pads1[] = {
|
||||
iomux_v3_cfg_t const enet_pads1[] = {
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
@ -170,7 +176,7 @@ iomux_v3_cfg_t enet_pads1[] = {
|
|||
MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t enet_pads2[] = {
|
||||
iomux_v3_cfg_t const enet_pads2[] = {
|
||||
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
@ -180,7 +186,7 @@ iomux_v3_cfg_t enet_pads2[] = {
|
|||
};
|
||||
|
||||
/* Button assignments for J14 */
|
||||
static iomux_v3_cfg_t button_pads[] = {
|
||||
static iomux_v3_cfg_t const button_pads[] = {
|
||||
/* Menu */
|
||||
MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Back */
|
||||
|
@ -213,7 +219,7 @@ static void setup_iomux_enet(void)
|
|||
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t usb_pads[] = {
|
||||
iomux_v3_cfg_t const usb_pads[] = {
|
||||
MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
@ -264,6 +270,9 @@ int board_mmc_init(bd_t *bis)
|
|||
s32 status = 0;
|
||||
u32 index = 0;
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
|
@ -294,7 +303,7 @@ u32 get_board_rev(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t ecspi1_pads[] = {
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
/* SS1 */
|
||||
MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
@ -372,14 +381,337 @@ int setup_sata(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = {
|
||||
/* Backlight on RGB connector: J15 */
|
||||
MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
|
||||
|
||||
/* Backlight on LVDS connector: J6 */
|
||||
MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const rgb_pads[] = {
|
||||
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
|
||||
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
|
||||
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
|
||||
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
|
||||
MX6Q_PAD_DI0_PIN4__GPIO_4_20,
|
||||
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
|
||||
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
|
||||
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
|
||||
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
|
||||
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
|
||||
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
|
||||
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
|
||||
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
|
||||
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
|
||||
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
|
||||
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
|
||||
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
|
||||
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
|
||||
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
|
||||
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
|
||||
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
|
||||
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
|
||||
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
|
||||
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
|
||||
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
|
||||
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
|
||||
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
|
||||
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
|
||||
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
|
||||
};
|
||||
|
||||
struct display_info_t {
|
||||
int bus;
|
||||
int addr;
|
||||
int pixfmt;
|
||||
int (*detect)(struct display_info_t const *dev);
|
||||
void (*enable)(struct display_info_t const *dev);
|
||||
struct fb_videomode mode;
|
||||
};
|
||||
|
||||
|
||||
static int detect_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
|
||||
}
|
||||
|
||||
static void enable_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
u8 reg;
|
||||
printf("%s: setup HDMI monitor\n", __func__);
|
||||
reg = __raw_readb(
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
reg |= HDMI_PHY_CONF0_PDZ_MASK;
|
||||
__raw_writeb(reg,
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
|
||||
__raw_writeb(reg,
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
|
||||
__raw_writeb(reg,
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
__raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
|
||||
HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
|
||||
}
|
||||
|
||||
static int detect_i2c(struct display_info_t const *dev)
|
||||
{
|
||||
return ((0 == i2c_set_bus_num(dev->bus))
|
||||
&&
|
||||
(0 == i2c_probe(dev->addr)));
|
||||
}
|
||||
|
||||
static void enable_lvds(struct display_info_t const *dev)
|
||||
{
|
||||
struct iomuxc *iomux = (struct iomuxc *)
|
||||
IOMUXC_BASE_ADDR;
|
||||
u32 reg = readl(&iomux->gpr[2]);
|
||||
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
|
||||
writel(reg, &iomux->gpr[2]);
|
||||
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
|
||||
}
|
||||
|
||||
static void enable_rgb(struct display_info_t const *dev)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
rgb_pads,
|
||||
ARRAY_SIZE(rgb_pads));
|
||||
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
|
||||
}
|
||||
|
||||
static struct display_info_t const displays[] = {{
|
||||
.bus = -1,
|
||||
.addr = 0,
|
||||
.pixfmt = IPU_PIX_FMT_RGB24,
|
||||
.detect = detect_hdmi,
|
||||
.enable = enable_hdmi,
|
||||
.mode = {
|
||||
.name = "HDMI",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = 2,
|
||||
.addr = 0x4,
|
||||
.pixfmt = IPU_PIX_FMT_LVDS666,
|
||||
.detect = detect_i2c,
|
||||
.enable = enable_lvds,
|
||||
.mode = {
|
||||
.name = "Hannstar-XGA",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = 2,
|
||||
.addr = 0x38,
|
||||
.pixfmt = IPU_PIX_FMT_LVDS666,
|
||||
.detect = detect_i2c,
|
||||
.enable = enable_lvds,
|
||||
.mode = {
|
||||
.name = "wsvga-lvds",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = 2,
|
||||
.addr = 0x48,
|
||||
.pixfmt = IPU_PIX_FMT_RGB666,
|
||||
.detect = detect_i2c,
|
||||
.enable = enable_rgb,
|
||||
.mode = {
|
||||
.name = "wvga-rgb",
|
||||
.refresh = 57,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 37037,
|
||||
.left_margin = 40,
|
||||
.right_margin = 60,
|
||||
.upper_margin = 10,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 20,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
|
||||
int board_video_skip(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
char const *panel = getenv("panel");
|
||||
if (!panel) {
|
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) {
|
||||
struct display_info_t const *dev = displays+i;
|
||||
if (dev->detect(dev)) {
|
||||
panel = dev->mode.name;
|
||||
printf("auto-detected panel %s\n", panel);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!panel) {
|
||||
panel = displays[0].mode.name;
|
||||
printf("No panel detected: default to %s\n", panel);
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) {
|
||||
if (!strcmp(panel, displays[i].mode.name))
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i < ARRAY_SIZE(displays)) {
|
||||
ret = ipuv3_fb_init(&displays[i].mode, 0,
|
||||
displays[i].pixfmt);
|
||||
if (!ret) {
|
||||
displays[i].enable(displays+i);
|
||||
printf("Display: %s (%ux%u)\n",
|
||||
displays[i].mode.name,
|
||||
displays[i].mode.xres,
|
||||
displays[i].mode.yres);
|
||||
} else
|
||||
printf("LCD %s cannot be configured: %d\n",
|
||||
displays[i].mode.name, ret);
|
||||
} else {
|
||||
printf("unsupported panel %s\n", panel);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
return (0 != ret);
|
||||
}
|
||||
|
||||
static void setup_display(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
|
||||
int reg;
|
||||
|
||||
/* Turn on LDB0,IPU,IPU DI0 clocks */
|
||||
reg = __raw_readl(&mxc_ccm->CCGR3);
|
||||
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
|
||||
|MXC_CCM_CCGR3_LDB_DI0_MASK;
|
||||
writel(reg, &mxc_ccm->CCGR3);
|
||||
|
||||
/* Turn on HDMI PHY clock */
|
||||
reg = __raw_readl(&mxc_ccm->CCGR2);
|
||||
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
|
||||
|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
|
||||
writel(reg, &mxc_ccm->CCGR2);
|
||||
|
||||
/* clear HDMI PHY reset */
|
||||
__raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
|
||||
HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
|
||||
|
||||
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
|
||||
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
|
||||
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
|
||||
|
||||
/* set LDB0, LDB1 clk select to 011/011 */
|
||||
reg = readl(&mxc_ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
||||
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
||||
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|
||||
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->cs2cdr);
|
||||
|
||||
reg = readl(&mxc_ccm->cscmr2);
|
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
|
||||
writel(reg, &mxc_ccm->cscmr2);
|
||||
|
||||
reg = readl(&mxc_ccm->chsccdr);
|
||||
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
|
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
|
||||
|(CHSCCDR_PODF_DIVIDE_BY_3
|
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|
||||
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
|
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->chsccdr);
|
||||
|
||||
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
||||
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|
||||
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
||||
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
||||
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
||||
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
||||
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
||||
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|
||||
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
|
||||
writel(reg, &iomux->gpr[2]);
|
||||
|
||||
reg = readl(&iomux->gpr[3]);
|
||||
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
|
||||
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
|
||||
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
|
||||
writel(reg, &iomux->gpr[3]);
|
||||
|
||||
/* backlights off until needed */
|
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads,
|
||||
ARRAY_SIZE(backlight_pads));
|
||||
gpio_direction_input(LVDS_BACKLIGHT_GP);
|
||||
gpio_direction_input(RGB_BACKLIGHT_GP);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
setup_buttons();
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
setup_display();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do not overwrite the console
|
||||
* Use always serial for U-Boot console
|
||||
*/
|
||||
int overwrite_console(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
|
|
|
@ -51,12 +51,12 @@ int dram_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t uart1_pads[] = {
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t enet_pads[] = {
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
@ -86,7 +86,7 @@ static void setup_iomux_enet(void)
|
|||
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
@ -120,6 +120,7 @@ int board_mmc_init(bd_t *bis)
|
|||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#include <asm/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
|
@ -93,7 +94,7 @@ static u32 get_mx_rev(void)
|
|||
return (~rev & 0x7) + 1;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t efikasb_revision_pads[] = {
|
||||
static iomux_v3_cfg_t const efikasb_revision_pads[] = {
|
||||
MX51_PAD_EIM_CS3__GPIO2_28,
|
||||
MX51_PAD_EIM_CS4__GPIO2_29,
|
||||
};
|
||||
|
@ -140,7 +141,7 @@ int dram_init(void)
|
|||
/*
|
||||
* UART configuration
|
||||
*/
|
||||
static iomux_v3_cfg_t efikamx_uart_pads[] = {
|
||||
static iomux_v3_cfg_t const efikamx_uart_pads[] = {
|
||||
MX51_PAD_UART1_RXD__UART1_RXD,
|
||||
MX51_PAD_UART1_TXD__UART1_TXD,
|
||||
MX51_PAD_UART1_RTS__UART1_RTS,
|
||||
|
@ -150,7 +151,7 @@ static iomux_v3_cfg_t efikamx_uart_pads[] = {
|
|||
/*
|
||||
* SPI configuration
|
||||
*/
|
||||
static iomux_v3_cfg_t efikamx_spi_pads[] = {
|
||||
static iomux_v3_cfg_t const efikamx_spi_pads[] = {
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
|
||||
|
@ -272,7 +273,7 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = {
|
|||
{MMC_SDHC2_BASE_ADDR},
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
|
||||
static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
|
||||
MX51_PAD_SD1_CMD__SD1_CMD,
|
||||
MX51_PAD_SD1_CLK__SD1_CLK,
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0,
|
||||
|
@ -284,7 +285,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
|
|||
|
||||
#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
|
||||
|
||||
static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
|
||||
static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
|
||||
MX51_PAD_GPIO1_0__SD1_CD,
|
||||
MX51_PAD_EIM_CS2__SD1_CD,
|
||||
};
|
||||
|
@ -292,7 +293,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
|
|||
#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
|
||||
#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
|
||||
|
||||
static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
|
||||
static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
|
||||
MX51_PAD_SD2_CMD__SD2_CMD,
|
||||
MX51_PAD_SD2_CLK__SD2_CLK,
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0,
|
||||
|
@ -349,6 +350,9 @@ int board_mmc_init(bd_t *bis)
|
|||
gpio_direction_input(EFIKASB_SDHC1_CD);
|
||||
}
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
|
||||
if (machine_is_efikasb()) {
|
||||
|
@ -368,7 +372,7 @@ int board_mmc_init(bd_t *bis)
|
|||
/*
|
||||
* PATA
|
||||
*/
|
||||
static iomux_v3_cfg_t efikamx_pata_pads[] = {
|
||||
static iomux_v3_cfg_t const efikamx_pata_pads[] = {
|
||||
MX51_PAD_NANDF_WE_B__PATA_DIOW,
|
||||
MX51_PAD_NANDF_RE_B__PATA_DIOR,
|
||||
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
|
||||
|
@ -419,7 +423,7 @@ static inline void setup_iomux_usb(void) { }
|
|||
#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
|
||||
#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
|
||||
|
||||
static iomux_v3_cfg_t efikasb_led_pads[] = {
|
||||
static iomux_v3_cfg_t const efikasb_led_pads[] = {
|
||||
MX51_PAD_GPIO1_3__GPIO1_3,
|
||||
MX51_PAD_EIM_CS0__GPIO2_25,
|
||||
};
|
||||
|
|
46
board/nokia/rx51/Makefile
Normal file
46
board/nokia/rx51/Makefile
Normal file
|
@ -0,0 +1,46 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
SOBJS-y := lowlevel_init.o
|
||||
|
||||
COBJS := $(sort $(COBJS-y))
|
||||
SOBJS := $(sort $(SOBJS-y))
|
||||
SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S)
|
||||
OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
209
board/nokia/rx51/lowlevel_init.S
Normal file
209
board/nokia/rx51/lowlevel_init.S
Normal file
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
* (C) Copyright 2011-2012
|
||||
* Pali Rohár <pali.rohar@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
relocaddr: /* address of this relocaddr section after coping */
|
||||
.word . /* address of section (calculated at compile time) */
|
||||
|
||||
startaddr: /* address of u-boot after copying */
|
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
kernaddr: /* address of kernel after copying */
|
||||
.word KERNEL_ADDRESS
|
||||
|
||||
kernsize: /* maximal size of kernel image */
|
||||
.word KERNEL_MAXSIZE
|
||||
|
||||
kernoffs: /* offset of kernel image in loaded u-boot */
|
||||
.word KERNEL_OFFSET
|
||||
|
||||
imagesize: /* maximal size of image */
|
||||
.word IMAGE_MAXSIZE
|
||||
|
||||
ih_magic: /* IH_MAGIC in big endian from include/image.h */
|
||||
.word 0x56190527
|
||||
|
||||
/*
|
||||
* Routine: save_boot_params (called after reset from start.S)
|
||||
* Description: Copy attached kernel to address KERNEL_ADDRESS
|
||||
* Copy u-boot to address CONFIG_SYS_TEXT_BASE
|
||||
* Return to copied u-boot address
|
||||
*/
|
||||
|
||||
.global save_boot_params
|
||||
save_boot_params:
|
||||
|
||||
|
||||
/* Copy valid attached kernel to address KERNEL_ADDRESS */
|
||||
|
||||
copy_kernel_start:
|
||||
adr r0, relocaddr /* r0 - address of section relocaddr */
|
||||
ldr r1, relocaddr /* r1 - address of relocaddr after relocation */
|
||||
cmp r0, r1
|
||||
|
||||
/* r4 - calculated offset */
|
||||
subhi r4, r0, r1
|
||||
sublo r4, r1, r0
|
||||
|
||||
/* r0 - start of kernel before */
|
||||
ldr r0, startaddr
|
||||
addhi r0, r0, r4
|
||||
sublo r0, r0, r4
|
||||
ldr r1, kernoffs
|
||||
add r0, r0, r1
|
||||
|
||||
/* r3 - start of kernel after */
|
||||
ldr r3, kernaddr
|
||||
|
||||
/* r2 - end of kernel after */
|
||||
ldr r1, kernsize
|
||||
add r2, r3, r1
|
||||
|
||||
/* r1 - end of kernel before */
|
||||
add r1, r0, r1
|
||||
|
||||
/* remove header in target kernel */
|
||||
mov r5, #0
|
||||
str r5, [r3]
|
||||
|
||||
/* check for valid kernel uImage */
|
||||
ldr r4, [r0] /* r4 - 4 bytes header of kernel */
|
||||
ldr r5, ih_magic /* r5 - IH_MAGIC */
|
||||
cmp r4, r5
|
||||
bne copy_kernel_end /* skip if invalid image */
|
||||
|
||||
copy_kernel_loop:
|
||||
ldmdb r1!, {r3 - r10}
|
||||
stmdb r2!, {r3 - r10}
|
||||
cmp r1, r0
|
||||
bhi copy_kernel_loop
|
||||
|
||||
copy_kernel_end:
|
||||
mov r5, #0
|
||||
str r5, [r0] /* remove 4 bytes header of kernel */
|
||||
|
||||
|
||||
/* Fix u-boot code */
|
||||
|
||||
fix_start:
|
||||
adr r0, relocaddr /* r0 - address of section relocaddr */
|
||||
ldr r1, relocaddr /* r1 - address of relocaddr after relocation */
|
||||
cmp r0, r1
|
||||
|
||||
beq copy_uboot_end /* skip if u-boot is on correct address */
|
||||
|
||||
/* r5 - calculated offset */
|
||||
subhi r5, r0, r1
|
||||
sublo r5, r1, r0
|
||||
|
||||
/* r6 - maximal u-boot size */
|
||||
ldr r6, imagesize
|
||||
|
||||
/* fix return address */
|
||||
subhi lr, lr, r5
|
||||
addlo lr, lr, r5
|
||||
|
||||
/* r1 - start of u-boot after */
|
||||
ldr r1, startaddr
|
||||
|
||||
/* r0 - start of u-boot before */
|
||||
addhi r0, r1, r5
|
||||
sublo r0, r1, r5
|
||||
|
||||
/* check if we need to move uboot copy code before calling it */
|
||||
cmp r5, r6
|
||||
bhi copy_uboot_start /* now coping u-boot code directly is safe */
|
||||
|
||||
|
||||
copy_code_start:
|
||||
/* r0 - start of u-boot before */
|
||||
/* r1 - start of u-boot after */
|
||||
/* r6 - maximal u-boot size */
|
||||
|
||||
/* r7 - maximal kernel size */
|
||||
ldr r7, kernsize
|
||||
|
||||
/* r4 - end of kernel before */
|
||||
add r4, r0, r6
|
||||
add r4, r4, r7
|
||||
|
||||
/* r5 - end of u-boot after */
|
||||
ldr r5, startaddr
|
||||
add r5, r5, r6
|
||||
|
||||
/* r2 - start of loop code after */
|
||||
cmp r4, r5 /* higher address (r4 or r5) */
|
||||
movhs r2, r4
|
||||
movlo r2, r5
|
||||
|
||||
/* r3 - end of loop code before */
|
||||
adr r3, end
|
||||
|
||||
/* r4 - end of loop code after */
|
||||
adr r4, copy_uboot_start
|
||||
sub r4, r3, r4
|
||||
add r4, r2, r4
|
||||
|
||||
copy_code_loop:
|
||||
ldmdb r3!, {r7 - r10}
|
||||
stmdb r4!, {r7 - r10}
|
||||
cmp r4, r2
|
||||
bhi copy_code_loop
|
||||
|
||||
copy_code_end:
|
||||
mov pc, r2
|
||||
|
||||
|
||||
/* Copy u-boot to address CONFIG_SYS_TEXT_BASE */
|
||||
|
||||
copy_uboot_start:
|
||||
/* r0 - start of u-boot before */
|
||||
/* r1 - start of u-boot after */
|
||||
/* r6 - maximal u-boot size */
|
||||
|
||||
/* r2 - end of u-boot after */
|
||||
add r2, r1, r6
|
||||
|
||||
/* condition for copying from left to right */
|
||||
cmp r0, r1
|
||||
addlo r1, r0, r6 /* r1 - end of u-boot before */
|
||||
blo copy_uboot_loop_right
|
||||
|
||||
copy_uboot_loop_left:
|
||||
ldmia r0!, {r3 - r10}
|
||||
stmia r1!, {r3 - r10}
|
||||
cmp r1, r2
|
||||
blo copy_uboot_loop_left
|
||||
b copy_uboot_end
|
||||
|
||||
copy_uboot_loop_right:
|
||||
ldmdb r1!, {r3 - r10}
|
||||
stmdb r2!, {r3 - r10}
|
||||
cmp r1, r0
|
||||
bhi copy_uboot_loop_right
|
||||
|
||||
copy_uboot_end:
|
||||
bx lr
|
||||
|
||||
end:
|
677
board/nokia/rx51/rx51.c
Normal file
677
board/nokia/rx51/rx51.c
Normal file
|
@ -0,0 +1,677 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* Ивайло Димитров <freemangordon@abv.bg>
|
||||
*
|
||||
* (C) Copyright 2011-2012
|
||||
* Pali Rohár <pali.rohar@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Alistair Buxton <a.j.buxton@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code:
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <malloc.h>
|
||||
#include <twl4030.h>
|
||||
#include <i2c.h>
|
||||
#include <video_fb.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
|
||||
#include "rx51.h"
|
||||
#include "tag_omap.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
GraphicDevice gdev;
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
DDR_STACKED,
|
||||
"Nokia RX-51",
|
||||
"OneNAND"
|
||||
};
|
||||
|
||||
/* This structure contains default omap tags needed for booting Maemo 5 */
|
||||
static struct tag_omap omap[] = {
|
||||
OMAP_TAG_UART_CONFIG(0x04),
|
||||
OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200),
|
||||
OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
|
||||
OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
|
||||
OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
|
||||
OMAP_TAG_PARTITION_CONFIG(PART1_NAME, PART1_SIZE * PART1_MULL,
|
||||
PART1_OFFS, PART1_MASK),
|
||||
OMAP_TAG_PARTITION_CONFIG(PART2_NAME, PART2_SIZE * PART2_MULL,
|
||||
PART2_OFFS, PART2_MASK),
|
||||
OMAP_TAG_PARTITION_CONFIG(PART3_NAME, PART3_SIZE * PART3_MULL,
|
||||
PART3_OFFS, PART3_MASK),
|
||||
OMAP_TAG_PARTITION_CONFIG(PART4_NAME, PART4_SIZE * PART4_MULL,
|
||||
PART4_OFFS, PART4_MASK),
|
||||
OMAP_TAG_PARTITION_CONFIG(PART5_NAME, PART5_SIZE * PART5_MULL,
|
||||
PART5_OFFS, PART5_MASK),
|
||||
OMAP_TAG_PARTITION_CONFIG(PART6_NAME, PART6_SIZE * PART6_MULL,
|
||||
PART6_OFFS, PART6_MASK),
|
||||
OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
|
||||
OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
|
||||
OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
|
||||
OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"),
|
||||
OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"),
|
||||
{ }
|
||||
};
|
||||
|
||||
static char *boot_reason_ptr;
|
||||
static char *hw_build_ptr;
|
||||
static char *nolo_version_ptr;
|
||||
static char *boot_mode_ptr;
|
||||
|
||||
/*
|
||||
* Routine: init_omap_tags
|
||||
* Description: Initialize pointers to values in tag_omap
|
||||
*/
|
||||
static void init_omap_tags(void)
|
||||
{
|
||||
char *component;
|
||||
char *version;
|
||||
int i = 0;
|
||||
while (omap[i].hdr.tag) {
|
||||
switch (omap[i].hdr.tag) {
|
||||
case OMAP_TAG_BOOT_REASON:
|
||||
boot_reason_ptr = omap[i].u.boot_reason.reason_str;
|
||||
break;
|
||||
case OMAP_TAG_VERSION_STR:
|
||||
component = omap[i].u.version.component;
|
||||
version = omap[i].u.version.version;
|
||||
if (strcmp(component, "hw-build") == 0)
|
||||
hw_build_ptr = version;
|
||||
else if (strcmp(component, "nolo") == 0)
|
||||
nolo_version_ptr = version;
|
||||
else if (strcmp(component, "boot-mode") == 0)
|
||||
boot_mode_ptr = version;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
static void reuse_omap_atags(struct tag_omap *t)
|
||||
{
|
||||
char *component;
|
||||
char *version;
|
||||
while (t->hdr.tag) {
|
||||
switch (t->hdr.tag) {
|
||||
case OMAP_TAG_BOOT_REASON:
|
||||
memset(boot_reason_ptr, 0, 12);
|
||||
strcpy(boot_reason_ptr, t->u.boot_reason.reason_str);
|
||||
break;
|
||||
case OMAP_TAG_VERSION_STR:
|
||||
component = t->u.version.component;
|
||||
version = t->u.version.version;
|
||||
if (strcmp(component, "hw-build") == 0) {
|
||||
memset(hw_build_ptr, 0, 12);
|
||||
strcpy(hw_build_ptr, version);
|
||||
} else if (strcmp(component, "nolo") == 0) {
|
||||
memset(nolo_version_ptr, 0, 12);
|
||||
strcpy(nolo_version_ptr, version);
|
||||
} else if (strcmp(component, "boot-mode") == 0) {
|
||||
memset(boot_mode_ptr, 0, 12);
|
||||
strcpy(boot_mode_ptr, version);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
t = tag_omap_next(t);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: reuse_atags
|
||||
* Description: Reuse atags from previous bootloader.
|
||||
* Reuse only only HW build, boot reason, boot mode and nolo
|
||||
*/
|
||||
static void reuse_atags(void)
|
||||
{
|
||||
struct tag *t = (struct tag *)gd->bd->bi_boot_params;
|
||||
|
||||
/* First tag must be ATAG_CORE */
|
||||
if (t->hdr.tag != ATAG_CORE)
|
||||
return;
|
||||
|
||||
if (!boot_reason_ptr || !hw_build_ptr)
|
||||
return;
|
||||
|
||||
/* Last tag must be ATAG_NONE */
|
||||
while (t->hdr.tag != ATAG_NONE) {
|
||||
switch (t->hdr.tag) {
|
||||
case ATAG_REVISION:
|
||||
memset(hw_build_ptr, 0, 12);
|
||||
sprintf(hw_build_ptr, "%x", t->u.revision.rev);
|
||||
break;
|
||||
case ATAG_BOARD:
|
||||
reuse_omap_atags((struct tag_omap *)&t->u);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
t = tag_next(t);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
/* in SRAM or SDRAM, finish GPMC */
|
||||
gpmc_init();
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: get_board_revision
|
||||
* Description: Return board revision.
|
||||
*/
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return simple_strtol(hw_build_ptr, NULL, 16);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: setup_board_tags
|
||||
* Description: Append board specific boot tags.
|
||||
*/
|
||||
void setup_board_tags(struct tag **in_params)
|
||||
{
|
||||
int setup_console_atag;
|
||||
char *setup_boot_reason_atag;
|
||||
char *setup_boot_mode_atag;
|
||||
char *str;
|
||||
int i;
|
||||
int size;
|
||||
int total_size;
|
||||
struct tag *params;
|
||||
struct tag_omap *t;
|
||||
|
||||
params = (struct tag *)gd->bd->bi_boot_params;
|
||||
|
||||
params->u.core.flags = 0x0;
|
||||
params->u.core.pagesize = 0x1000;
|
||||
params->u.core.rootdev = 0x0;
|
||||
|
||||
/* append omap atag only if env setup_omap_atag is set to 1 */
|
||||
str = getenv("setup_omap_atag");
|
||||
if (!str || str[0] != '1')
|
||||
return;
|
||||
|
||||
str = getenv("setup_console_atag");
|
||||
if (str && str[0] == '1')
|
||||
setup_console_atag = 1;
|
||||
else
|
||||
setup_console_atag = 0;
|
||||
|
||||
setup_boot_reason_atag = getenv("setup_boot_reason_atag");
|
||||
setup_boot_mode_atag = getenv("setup_boot_mode_atag");
|
||||
|
||||
params = *in_params;
|
||||
t = (struct tag_omap *)¶ms->u;
|
||||
total_size = sizeof(struct tag_header);
|
||||
|
||||
for (i = 0; omap[i].hdr.tag; i++) {
|
||||
|
||||
/* skip serial console tag */
|
||||
if (!setup_console_atag &&
|
||||
omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE)
|
||||
continue;
|
||||
|
||||
size = omap[i].hdr.size + sizeof(struct tag_omap_header);
|
||||
memcpy(t, &omap[i], size);
|
||||
|
||||
/* set uart tag to 0 - disable serial console */
|
||||
if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART)
|
||||
t->u.uart.enabled_uarts = 0;
|
||||
|
||||
/* change boot reason */
|
||||
if (setup_boot_reason_atag &&
|
||||
omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) {
|
||||
memset(t->u.boot_reason.reason_str, 0, 12);
|
||||
strcpy(t->u.boot_reason.reason_str,
|
||||
setup_boot_reason_atag);
|
||||
}
|
||||
|
||||
/* change boot mode */
|
||||
if (setup_boot_mode_atag &&
|
||||
omap[i].hdr.tag == OMAP_TAG_VERSION_STR &&
|
||||
strcmp(omap[i].u.version.component, "boot-mode") == 0) {
|
||||
memset(t->u.version.version, 0, 12);
|
||||
strcpy(t->u.version.version, setup_boot_mode_atag);
|
||||
}
|
||||
|
||||
total_size += size;
|
||||
t = tag_omap_next(t);
|
||||
|
||||
}
|
||||
|
||||
params->hdr.tag = ATAG_BOARD;
|
||||
params->hdr.size = total_size >> 2;
|
||||
params = tag_next(params);
|
||||
|
||||
*in_params = params;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: video_hw_init
|
||||
* Description: Set up the GraphicDevice depending on sys_boot.
|
||||
*/
|
||||
void *video_hw_init(void)
|
||||
{
|
||||
/* fill in Graphic Device */
|
||||
gdev.frameAdrs = 0x8f9c0000;
|
||||
gdev.winSizeX = 800;
|
||||
gdev.winSizeY = 480;
|
||||
gdev.gdfBytesPP = 2;
|
||||
gdev.gdfIndex = GDF_16BIT_565RGB;
|
||||
memset((void *)gdev.frameAdrs, 0, 0xbb800);
|
||||
return (void *) &gdev;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: twl4030_regulator_set_mode
|
||||
* Description: Set twl4030 regulator mode over i2c powerbus.
|
||||
*/
|
||||
static void twl4030_regulator_set_mode(u8 id, u8 mode)
|
||||
{
|
||||
u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
|
||||
TWL4030_PM_MASTER_PB_WORD_MSB);
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
|
||||
TWL4030_PM_MASTER_PB_WORD_LSB);
|
||||
}
|
||||
|
||||
static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
|
||||
{
|
||||
u32 i, num_params = *parameters;
|
||||
u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
|
||||
|
||||
/*
|
||||
* copy the parameters to an un-cached area to avoid coherency
|
||||
* issues
|
||||
*/
|
||||
for (i = 0; i < num_params; i++) {
|
||||
__raw_writel(*parameters, sram_scratch_space);
|
||||
parameters++;
|
||||
sram_scratch_space++;
|
||||
}
|
||||
|
||||
/* Now make the PPA call */
|
||||
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: omap3_update_aux_cr_secure_rx51
|
||||
* Description: Modify the contents Auxiliary Control Register.
|
||||
* Parameters:
|
||||
* set_bits - bits to set in ACR
|
||||
* clr_bits - bits to clear in ACR
|
||||
*/
|
||||
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
|
||||
{
|
||||
struct emu_hal_params_rx51 emu_romcode_params = { 0, };
|
||||
u32 acr;
|
||||
|
||||
/* Read ACR */
|
||||
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
|
||||
acr &= ~clear_bits;
|
||||
acr |= set_bits;
|
||||
|
||||
emu_romcode_params.num_params = 2;
|
||||
emu_romcode_params.param1 = acr;
|
||||
|
||||
omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
|
||||
(u32 *)&emu_romcode_params);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: misc_init_r
|
||||
* Description: Configure board specific parts.
|
||||
*/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char buf[12];
|
||||
u8 state;
|
||||
|
||||
/* reset lp5523 led */
|
||||
i2c_set_bus_num(1);
|
||||
state = 0xff;
|
||||
i2c_write(0x32, 0x3d, 1, &state, 1);
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
/* initialize twl4030 power managment */
|
||||
twl4030_power_init();
|
||||
|
||||
/* set VSIM to 1.8V */
|
||||
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
|
||||
TWL4030_PM_RECEIVER_VSIM_VSEL_18,
|
||||
TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
|
||||
TWL4030_PM_RECEIVER_DEV_GRP_P1);
|
||||
|
||||
/* store I2C access state */
|
||||
twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
|
||||
TWL4030_PM_MASTER_PB_CFG);
|
||||
|
||||
/* enable I2C access to powerbus (needed for twl4030 regulator) */
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
|
||||
TWL4030_PM_MASTER_PB_CFG);
|
||||
|
||||
/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
|
||||
twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
|
||||
twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE);
|
||||
twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
|
||||
|
||||
/* restore I2C access state */
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
|
||||
TWL4030_PM_MASTER_PB_CFG);
|
||||
|
||||
/* set env variable attkernaddr for relocated kernel */
|
||||
sprintf(buf, "%#x", KERNEL_ADDRESS);
|
||||
setenv("attkernaddr", buf);
|
||||
|
||||
/* initialize omap tags */
|
||||
init_omap_tags();
|
||||
|
||||
/* reuse atags from previous bootloader */
|
||||
reuse_atags();
|
||||
|
||||
dieid_num_r();
|
||||
print_cpuinfo();
|
||||
|
||||
/*
|
||||
* Cortex-A8(r1p0..r1p2) errata 430973 workaround
|
||||
* Set IBE bit in Auxiliary Control Register
|
||||
*/
|
||||
omap3_update_aux_cr_secure_rx51(1 << 6, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_RX51();
|
||||
}
|
||||
|
||||
static unsigned long int twl_wd_time; /* last time of watchdog reset */
|
||||
static unsigned long int twl_i2c_lock;
|
||||
|
||||
/*
|
||||
* Routine: hw_watchdog_reset
|
||||
* Description: Reset timeout of twl4030 watchdog.
|
||||
*/
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
u8 timeout = 0;
|
||||
|
||||
/* do not reset watchdog too often - max every 4s */
|
||||
if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
|
||||
return;
|
||||
|
||||
/* localy lock twl4030 i2c bus */
|
||||
if (test_and_set_bit(0, &twl_i2c_lock))
|
||||
return;
|
||||
|
||||
/* read actual watchdog timeout */
|
||||
twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
|
||||
TWL4030_PM_RECEIVER_WATCHDOG_CFG);
|
||||
|
||||
/* timeout 0 means watchdog is disabled */
|
||||
/* reset watchdog timeout to 31s (maximum) */
|
||||
if (timeout != 0)
|
||||
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
|
||||
TWL4030_PM_RECEIVER_WATCHDOG_CFG);
|
||||
|
||||
/* store last watchdog reset time */
|
||||
twl_wd_time = get_timer(0);
|
||||
|
||||
/* localy unlock twl4030 i2c bus */
|
||||
test_and_clear_bit(0, &twl_i2c_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* TWL4030 keypad handler for cfb_console
|
||||
*/
|
||||
|
||||
static const char keymap[] = {
|
||||
/* normal */
|
||||
'q', 'o', 'p', ',', '\b', 0, 'a', 's',
|
||||
'w', 'd', 'f', 'g', 'h', 'j', 'k', 'l',
|
||||
'e', '.', 0, '\r', 0, 'z', 'x', 'c',
|
||||
'r', 'v', 'b', 'n', 'm', ' ', ' ', 0,
|
||||
't', 0, 0, 0, 0, 0, 0, 0,
|
||||
'y', 0, 0, 0, 0, 0, 0, 0,
|
||||
'u', 0, 0, 0, 0, 0, 0, 0,
|
||||
'i', 5, 6, 0, 0, 0, 0, 0,
|
||||
/* fn */
|
||||
'1', '9', '0', '=', '\b', 0, '*', '+',
|
||||
'2', '#', '-', '_', '(', ')', '&', '!',
|
||||
'3', '?', '^', '\r', 0, 156, '$', 238,
|
||||
'4', '/', '\\', '"', '\'', '@', 0, '<',
|
||||
'5', '|', '>', 0, 0, 0, 0, 0,
|
||||
'6', 0, 0, 0, 0, 0, 0, 0,
|
||||
'7', 0, 0, 0, 0, 0, 0, 0,
|
||||
'8', 16, 17, 0, 0, 0, 0, 0,
|
||||
};
|
||||
|
||||
static u8 keys[8];
|
||||
static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0};
|
||||
#define KEYBUF_SIZE 32
|
||||
static u8 keybuf[KEYBUF_SIZE];
|
||||
static u8 keybuf_head;
|
||||
static u8 keybuf_tail;
|
||||
|
||||
/*
|
||||
* Routine: rx51_kp_init
|
||||
* Description: Initialize HW keyboard.
|
||||
*/
|
||||
int rx51_kp_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
u8 ctrl;
|
||||
ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
|
||||
TWL4030_KEYPAD_KEYP_CTRL_REG);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* turn on keyboard and use hardware scanning */
|
||||
ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
|
||||
ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
|
||||
ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
|
||||
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
|
||||
TWL4030_KEYPAD_KEYP_CTRL_REG);
|
||||
/* enable key event status */
|
||||
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
|
||||
TWL4030_KEYPAD_KEYP_IMR1);
|
||||
/* enable interrupt generation on rising and falling */
|
||||
/* this is a workaround for qemu twl4030 emulation */
|
||||
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
|
||||
TWL4030_KEYPAD_KEYP_EDR);
|
||||
/* enable ISR clear on read */
|
||||
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
|
||||
TWL4030_KEYPAD_KEYP_SIH_CTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rx51_kp_fill(u8 k, u8 mods)
|
||||
{
|
||||
/* check if some cursor key without meta fn key was pressed */
|
||||
if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) {
|
||||
keybuf[keybuf_tail++] = '\e';
|
||||
keybuf_tail %= KEYBUF_SIZE;
|
||||
keybuf[keybuf_tail++] = '[';
|
||||
keybuf_tail %= KEYBUF_SIZE;
|
||||
if (k == 18) /* up */
|
||||
keybuf[keybuf_tail++] = 'A';
|
||||
else if (k == 31) /* left */
|
||||
keybuf[keybuf_tail++] = 'D';
|
||||
else if (k == 33) /* down */
|
||||
keybuf[keybuf_tail++] = 'B';
|
||||
else if (k == 34) /* right */
|
||||
keybuf[keybuf_tail++] = 'C';
|
||||
keybuf_tail %= KEYBUF_SIZE;
|
||||
return;
|
||||
}
|
||||
|
||||
if (mods & 2) { /* fn meta key was pressed */
|
||||
k = keymap[k+64];
|
||||
} else {
|
||||
k = keymap[k];
|
||||
if (mods & 1) { /* ctrl key was pressed */
|
||||
if (k >= 'a' && k <= 'z')
|
||||
k -= 'a' - 1;
|
||||
}
|
||||
if (mods & 4) { /* shift key was pressed */
|
||||
if (k >= 'a' && k <= 'z')
|
||||
k += 'A' - 'a';
|
||||
else if (k == '.')
|
||||
k = ':';
|
||||
else if (k == ',')
|
||||
k = ';';
|
||||
}
|
||||
}
|
||||
keybuf[keybuf_tail++] = k;
|
||||
keybuf_tail %= KEYBUF_SIZE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: rx51_kp_tstc
|
||||
* Description: Test if key was pressed (from buffer).
|
||||
*/
|
||||
int rx51_kp_tstc(void)
|
||||
{
|
||||
u8 c, r, dk, i;
|
||||
u8 intr;
|
||||
u8 mods;
|
||||
|
||||
/* localy lock twl4030 i2c bus */
|
||||
if (test_and_set_bit(0, &twl_i2c_lock))
|
||||
return 0;
|
||||
|
||||
/* twl4030 remembers up to 2 events */
|
||||
for (i = 0; i < 2; i++) {
|
||||
|
||||
/* check interrupt register for events */
|
||||
twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
|
||||
TWL4030_KEYPAD_KEYP_ISR1+(2*i));
|
||||
|
||||
/* no event */
|
||||
if (!(intr&1))
|
||||
continue;
|
||||
|
||||
/* read the key state */
|
||||
i2c_read(TWL4030_CHIP_KEYPAD,
|
||||
TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8);
|
||||
|
||||
/* cut out modifier keys from the keystate */
|
||||
mods = keys[4] >> 4;
|
||||
keys[4] &= 0x0f;
|
||||
|
||||
for (c = 0; c < 8; c++) {
|
||||
|
||||
/* get newly pressed keys only */
|
||||
dk = ((keys[c] ^ old_keys[c])&keys[c]);
|
||||
old_keys[c] = keys[c];
|
||||
|
||||
/* fill the keybuf */
|
||||
for (r = 0; r < 8; r++) {
|
||||
if (dk&1)
|
||||
rx51_kp_fill((c*8)+r, mods);
|
||||
dk = dk >> 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* localy unlock twl4030 i2c bus */
|
||||
test_and_clear_bit(0, &twl_i2c_lock);
|
||||
|
||||
return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: rx51_kp_getc
|
||||
* Description: Get last pressed key (from buffer).
|
||||
*/
|
||||
int rx51_kp_getc(void)
|
||||
{
|
||||
keybuf_head %= KEYBUF_SIZE;
|
||||
while (!rx51_kp_tstc())
|
||||
WATCHDOG_RESET();
|
||||
return keybuf[keybuf_head++];
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: board_mmc_init
|
||||
* Description: Initialize mmc devices.
|
||||
*/
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
omap_mmc_init(0, 0, 0);
|
||||
omap_mmc_init(1, 0, 0);
|
||||
return 0;
|
||||
}
|
389
board/nokia/rx51/rx51.h
Normal file
389
board/nokia/rx51/rx51.h
Normal file
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* Ивайло Димитров <freemangordon@abv.bg>
|
||||
*
|
||||
* (C) Copyright 2011-2012
|
||||
* Pali Rohár <pali.rohar@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2008
|
||||
* Dirk Behme <dirk.behme@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _RX51_H_
|
||||
#define _RX51_H_
|
||||
|
||||
/* Needed for ROM SMC call */
|
||||
struct emu_hal_params_rx51 {
|
||||
u32 num_params;
|
||||
u32 param1;
|
||||
u32 param2;
|
||||
u32 param3;
|
||||
u32 param4;
|
||||
};
|
||||
|
||||
int print_cpuinfo(void);
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_RX51() \
|
||||
/* SDRC */\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/* GPMC */\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
/* DSS */\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/* CAMERA */\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
|
||||
/* Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLK*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/* Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/* Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
|
||||
/* Bluetooth */\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
|
||||
/* Modem Interface */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
|
||||
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
|
||||
/* Serial Interface */\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOM*/\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
|
||||
/* USB EHCI (port 2) */\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA1*/\
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*MMC1_WP*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MD*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA0*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA1*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA2*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA7*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA4*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA5*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA6*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA3*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26m*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespw*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswa*/\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9ni*/\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmare0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmare1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmare2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmare3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrs*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtc*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeu*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlere*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleac*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusfl*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusfl*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
|
||||
|
||||
#define MUX_RX51_C() \
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
|
||||
|
||||
#endif
|
311
board/nokia/rx51/tag_omap.h
Normal file
311
board/nokia/rx51/tag_omap.h
Normal file
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* (C) Copyright 2011-2012
|
||||
* Pali Rohár <pali.rohar@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2011
|
||||
* marcel@mesa.nl, Mesa Consulting B.V.
|
||||
*
|
||||
* (C) Copyright 2004-2005
|
||||
* Nokia Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Code copied from maemo kernel 2.6.28 file
|
||||
* arch/arm/plat-omap/include/mach/board.h
|
||||
*
|
||||
* Information structures for board-specific data
|
||||
*
|
||||
* Copyright (C) 2004 Nokia Corporation
|
||||
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
*/
|
||||
|
||||
/* Different peripheral ids */
|
||||
#define OMAP_TAG_CLOCK 0x4f01
|
||||
#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
|
||||
#define OMAP_TAG_USB 0x4f04
|
||||
#define OMAP_TAG_LCD 0x4f05
|
||||
#define OMAP_TAG_GPIO_SWITCH 0x4f06
|
||||
#define OMAP_TAG_UART 0x4f07
|
||||
#define OMAP_TAG_FBMEM 0x4f08
|
||||
#define OMAP_TAG_STI_CONSOLE 0x4f09
|
||||
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
|
||||
#define OMAP_TAG_PARTITION 0x4f0b
|
||||
#define OMAP_TAG_TEA5761 0x4f10
|
||||
#define OMAP_TAG_TMP105 0x4f11
|
||||
|
||||
#define OMAP_TAG_BOOT_REASON 0x4f80
|
||||
#define OMAP_TAG_FLASH_PART_STR 0x4f81
|
||||
#define OMAP_TAG_VERSION_STR 0x4f82
|
||||
|
||||
#define OMAP_TAG_NOKIA_BT 0x4e01
|
||||
#define OMAP_TAG_WLAN_CX3110X 0x4e02
|
||||
#define OMAP_TAG_CBUS 0x4e03
|
||||
#define OMAP_TAG_EM_ASIC_BB5 0x4e04
|
||||
|
||||
|
||||
struct omap_clock_config {
|
||||
/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
|
||||
u8 system_clock_type;
|
||||
};
|
||||
|
||||
struct omap_serial_console_config {
|
||||
u8 console_uart;
|
||||
u32 console_speed;
|
||||
};
|
||||
|
||||
struct omap_sti_console_config {
|
||||
unsigned enable:1;
|
||||
u8 channel;
|
||||
};
|
||||
|
||||
struct omap_usb_config {
|
||||
/* Configure drivers according to the connectors on your board:
|
||||
* - "A" connector (rectagular)
|
||||
* ... for host/OHCI use, set "register_host".
|
||||
* - "B" connector (squarish) or "Mini-B"
|
||||
* ... for device/gadget use, set "register_dev".
|
||||
* - "Mini-AB" connector (very similar to Mini-B)
|
||||
* ... for OTG use as device OR host, initialize "otg"
|
||||
*/
|
||||
unsigned register_host:1;
|
||||
unsigned register_dev:1;
|
||||
u8 otg; /* port number, 1-based: usb1 == 2 */
|
||||
|
||||
u8 hmc_mode;
|
||||
|
||||
/* implicitly true if otg: host supports remote wakeup? */
|
||||
u8 rwc;
|
||||
|
||||
/* signaling pins used to talk to transceiver on usbN:
|
||||
* 0 == usbN unused
|
||||
* 2 == usb0-only, using internal transceiver
|
||||
* 3 == 3 wire bidirectional
|
||||
* 4 == 4 wire bidirectional
|
||||
* 6 == 6 wire unidirectional (or TLL)
|
||||
*/
|
||||
u8 pins[3];
|
||||
};
|
||||
|
||||
struct omap_lcd_config {
|
||||
char panel_name[16];
|
||||
char ctrl_name[16];
|
||||
s16 nreset_gpio;
|
||||
u8 data_lines;
|
||||
};
|
||||
|
||||
struct omap_fbmem_config {
|
||||
u32 start;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
struct omap_gpio_switch_config {
|
||||
char name[12];
|
||||
u16 gpio;
|
||||
u8 flags:4;
|
||||
u8 type:4;
|
||||
unsigned int key_code:24; /* Linux key code */
|
||||
};
|
||||
|
||||
struct omap_uart_config {
|
||||
/* Bit field of UARTs present; bit 0 --> UART1 */
|
||||
unsigned int enabled_uarts;
|
||||
};
|
||||
|
||||
struct omap_tea5761_config {
|
||||
u16 enable_gpio;
|
||||
};
|
||||
|
||||
struct omap_partition_config {
|
||||
char name[16];
|
||||
unsigned int size;
|
||||
unsigned int offset;
|
||||
/* same as in include/linux/mtd/partitions.h */
|
||||
unsigned int mask_flags;
|
||||
};
|
||||
|
||||
struct omap_flash_part_str_config {
|
||||
char part_table[0];
|
||||
};
|
||||
|
||||
struct omap_boot_reason_config {
|
||||
char reason_str[12];
|
||||
};
|
||||
|
||||
struct omap_version_config {
|
||||
char component[12];
|
||||
char version[12];
|
||||
};
|
||||
|
||||
/*
|
||||
* Code copied from maemo kernel 2.6.28 file
|
||||
* arch/arm/plat-omap/include/mach/board-nokia.h
|
||||
*
|
||||
* Information structures for Nokia-specific board config data
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
*/
|
||||
|
||||
struct omap_bluetooth_config {
|
||||
u8 chip_type;
|
||||
u8 bt_wakeup_gpio;
|
||||
u8 host_wakeup_gpio;
|
||||
u8 reset_gpio;
|
||||
u8 bt_uart;
|
||||
u8 bd_addr[6];
|
||||
u8 bt_sysclk;
|
||||
};
|
||||
|
||||
struct omap_wlan_cx3110x_config {
|
||||
u8 chip_type;
|
||||
u8 reserverd;
|
||||
s16 power_gpio;
|
||||
s16 irq_gpio;
|
||||
s16 spi_cs_gpio;
|
||||
};
|
||||
|
||||
struct omap_cbus_config {
|
||||
s16 clk_gpio;
|
||||
s16 dat_gpio;
|
||||
s16 sel_gpio;
|
||||
};
|
||||
|
||||
struct omap_em_asic_bb5_config {
|
||||
s16 retu_irq_gpio;
|
||||
s16 tahvo_irq_gpio;
|
||||
};
|
||||
|
||||
/*
|
||||
* omap_tag handling
|
||||
*
|
||||
* processing omap tag structures
|
||||
*
|
||||
* Copyright (C) 2011 marcel@mesa.nl, Mesa Consulting B.V.
|
||||
* Copyright (C) 2012 Pali Rohár <pali.rohar@gmail.com>
|
||||
*/
|
||||
|
||||
/* TI OMAP specific information */
|
||||
#define ATAG_BOARD 0x414f4d50
|
||||
|
||||
struct tag_omap_header {
|
||||
u16 tag;
|
||||
u16 size;
|
||||
};
|
||||
|
||||
struct tag_omap {
|
||||
struct tag_omap_header hdr;
|
||||
union {
|
||||
struct omap_clock_config clock;
|
||||
struct omap_serial_console_config serial_console;
|
||||
struct omap_sti_console_config sti_console;
|
||||
struct omap_usb_config usb;
|
||||
struct omap_lcd_config lcd;
|
||||
struct omap_fbmem_config fbmem;
|
||||
struct omap_gpio_switch_config gpio_switch;
|
||||
struct omap_uart_config uart;
|
||||
struct omap_tea5761_config tea5761;
|
||||
struct omap_partition_config partition;
|
||||
struct omap_flash_part_str_config flash_part_str;
|
||||
struct omap_boot_reason_config boot_reason;
|
||||
struct omap_version_config version;
|
||||
struct omap_bluetooth_config bluetooth;
|
||||
struct omap_wlan_cx3110x_config wlan_cx3110x;
|
||||
struct omap_cbus_config cbus;
|
||||
struct omap_em_asic_bb5_config em_asic_bb5;
|
||||
} u;
|
||||
};
|
||||
|
||||
#define tag_omap_next(t) ((struct tag_omap *)((u8 *)(t) + \
|
||||
(t)->hdr.size + sizeof(struct tag_omap_header)))
|
||||
|
||||
#define OMAP_TAG_HEADER_CONFIG(config, type) \
|
||||
.hdr.tag = config, \
|
||||
.hdr.size = sizeof(struct type)
|
||||
|
||||
#define OMAP_TAG_UART_CONFIG(p1) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_UART, omap_uart_config), \
|
||||
.u.uart.enabled_uarts = p1, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_SERIAL_CONSOLE_CONFIG(p1, p2) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_SERIAL_CONSOLE, \
|
||||
omap_serial_console_config), \
|
||||
.u.serial_console.console_uart = p1, \
|
||||
.u.serial_console.console_speed = p2, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_LCD_CONFIG(p1, p2, p3, p4) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_LCD, omap_lcd_config), \
|
||||
.u.lcd.panel_name = p1, \
|
||||
.u.lcd.ctrl_name = p2, \
|
||||
.u.lcd.nreset_gpio = p3, \
|
||||
.u.lcd.data_lines = p4, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_GPIO_SWITCH_CONFIG(p1, p2, p3, p4, p5) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_GPIO_SWITCH, \
|
||||
omap_gpio_switch_config), \
|
||||
.u.gpio_switch.name = p1, \
|
||||
.u.gpio_switch.gpio = p2, \
|
||||
.u.gpio_switch.flags = p3, \
|
||||
.u.gpio_switch.type = p4, \
|
||||
.u.gpio_switch.key_code = p5, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_WLAN_CX3110X_CONFIG(p1, p2, p3, p4, p5) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_WLAN_CX3110X, \
|
||||
omap_wlan_cx3110x_config), \
|
||||
.u.wlan_cx3110x.chip_type = p1, \
|
||||
.u.wlan_cx3110x.reserverd = p2, \
|
||||
.u.wlan_cx3110x.power_gpio = p3, \
|
||||
.u.wlan_cx3110x.irq_gpio = p4, \
|
||||
.u.wlan_cx3110x.spi_cs_gpio = p5, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_PARTITION_CONFIG(p1, p2, p3, p4) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_PARTITION, \
|
||||
omap_partition_config), \
|
||||
.u.partition.name = p1, \
|
||||
.u.partition.size = p2, \
|
||||
.u.partition.offset = p3, \
|
||||
.u.partition.mask_flags = p4, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_BOOT_REASON_CONFIG(p1) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_BOOT_REASON, \
|
||||
omap_boot_reason_config), \
|
||||
.u.boot_reason.reason_str = p1, \
|
||||
}
|
||||
|
||||
#define OMAP_TAG_VERSION_STR_CONFIG(p1, p2) \
|
||||
{ \
|
||||
OMAP_TAG_HEADER_CONFIG(OMAP_TAG_VERSION_STR, \
|
||||
omap_version_config), \
|
||||
.u.version.component = p1, \
|
||||
.u.version.version = p2, \
|
||||
}
|
|
@ -25,9 +25,7 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(VENDOR).o
|
||||
|
||||
COBJS-y += board.o
|
||||
COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o
|
||||
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
|
||||
include common.mk
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
|
4
board/nvidia/common/common.mk
Normal file
4
board/nvidia/common/common.mk
Normal file
|
@ -0,0 +1,4 @@
|
|||
# common options for all tegra boards
|
||||
COBJS-y += ../../nvidia/common/board.o
|
||||
COBJS-$(CONFIG_SPI_UART_SWITCH) += ../../nvidia/common/uart-spi-switch.o
|
||||
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
usb1 = "/usb@c5004000";
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -52,7 +53,7 @@
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
status = "disabled";
|
||||
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
|
||||
};
|
||||
|
||||
nand-controller@70008000 {
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
usb0 = "/usb@c5008000";
|
||||
usb1 = "/usb@c5000000";
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -61,6 +60,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -75,3 +75,12 @@ int board_mmc_init(bd_t *bd)
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void pin_mux_usb(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
|
||||
pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
|
||||
pinmux_tristate_disable(PINGRP_CDEV2);
|
||||
/* USB2 PHY reset GPIO */
|
||||
pinmux_tristate_disable(PINGRP_UAC);
|
||||
}
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/mmc.h>
|
||||
#include <asm/gpio.h>
|
||||
|
@ -34,23 +35,14 @@
|
|||
#endif
|
||||
|
||||
/* TODO: Remove this code when the SPI switch is working */
|
||||
#ifndef CONFIG_SPI_UART_SWITCH
|
||||
/*
|
||||
* Routine: gpio_config_uart_seaboard
|
||||
* Description: Force GPIO_PI3 low on Seaboard so UART4 works.
|
||||
*/
|
||||
static void gpio_config_uart_seaboard(void)
|
||||
{
|
||||
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
|
||||
gpio_request(GPIO_PI3, NULL);
|
||||
gpio_direction_output(GPIO_PI3, 0);
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
|
||||
void gpio_early_init_uart(void)
|
||||
{
|
||||
if (machine_is_ventana())
|
||||
return;
|
||||
gpio_config_uart_seaboard();
|
||||
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
gpio_request(GPIO_PI3, NULL);
|
||||
#endif
|
||||
gpio_direction_output(GPIO_PI3, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -68,6 +68,11 @@ static inline int board_is_evm_sk(void)
|
|||
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_idk(void)
|
||||
{
|
||||
return !strncmp(header.config, "SKU#02", 6);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read header information from EEPROM into global structure.
|
||||
*/
|
||||
|
@ -242,7 +247,24 @@ void s_init(void)
|
|||
/* UART softreset */
|
||||
u32 regVal;
|
||||
|
||||
#ifdef CONFIG_SERIAL1
|
||||
enable_uart0_pin_mux();
|
||||
#endif /* CONFIG_SERIAL1 */
|
||||
#ifdef CONFIG_SERIAL2
|
||||
enable_uart1_pin_mux();
|
||||
#endif /* CONFIG_SERIAL2 */
|
||||
#ifdef CONFIG_SERIAL3
|
||||
enable_uart2_pin_mux();
|
||||
#endif /* CONFIG_SERIAL3 */
|
||||
#ifdef CONFIG_SERIAL4
|
||||
enable_uart3_pin_mux();
|
||||
#endif /* CONFIG_SERIAL4 */
|
||||
#ifdef CONFIG_SERIAL5
|
||||
enable_uart4_pin_mux();
|
||||
#endif /* CONFIG_SERIAL5 */
|
||||
#ifdef CONFIG_SERIAL6
|
||||
enable_uart5_pin_mux();
|
||||
#endif /* CONFIG_SERIAL6 */
|
||||
|
||||
regVal = readl(&uart_base->uartsyscfg);
|
||||
regVal |= UART_RESET;
|
||||
|
@ -381,7 +403,7 @@ int board_eth_init(bd_t *bis)
|
|||
return -1;
|
||||
}
|
||||
|
||||
if (board_is_bone() || board_is_bone_lt()) {
|
||||
if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
|
||||
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
||||
PHY_INTERFACE_MODE_MII;
|
||||
|
|
|
@ -44,6 +44,11 @@ struct am335x_baseboard_id {
|
|||
* is required on the board.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_uart1_pin_mux(void);
|
||||
void enable_uart2_pin_mux(void);
|
||||
void enable_uart3_pin_mux(void);
|
||||
void enable_uart4_pin_mux(void);
|
||||
void enable_uart5_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
void enable_board_pin_mux(struct am335x_baseboard_id *header);
|
||||
#endif
|
||||
|
|
|
@ -27,6 +27,36 @@ static struct module_pin_mux uart0_pin_mux[] = {
|
|||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart1_pin_mux[] = {
|
||||
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
|
||||
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart2_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
|
||||
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart3_pin_mux[] = {
|
||||
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart4_pin_mux[] = {
|
||||
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
|
||||
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart5_pin_mux[] = {
|
||||
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
|
||||
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
|
@ -39,6 +69,17 @@ static struct module_pin_mux mmc0_pin_mux[] = {
|
|||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
|
@ -135,6 +176,30 @@ void enable_uart0_pin_mux(void)
|
|||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart1_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart1_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart2_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart2_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart3_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart3_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart4_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart4_pin_mux);
|
||||
}
|
||||
|
||||
void enable_uart5_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart5_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
|
@ -196,12 +261,27 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
|
|||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
}
|
||||
} else if (!strncmp(header->config, "SKU#02", 6)) {
|
||||
/*
|
||||
* Industrial Motor Control (IDK)
|
||||
* note: IDK console is on UART3 by default.
|
||||
* So u-boot mus be build with CONFIG_SERIAL4 and
|
||||
* CONFIG_CONS_INDEX=4
|
||||
*/
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_no_cd_pin_mux);
|
||||
} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
|
||||
/* Starter Kit EVM */
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
configure_module_pin_mux(gpio0_7_pin_mux);
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
|
||||
} else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) {
|
||||
/* Beaglebone LT pinmux */
|
||||
configure_module_pin_mux(i2c1_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
} else {
|
||||
puts("Unknown board, cannot configure pinmux.");
|
||||
hang();
|
||||
|
|
44
board/toradex/colibri_t20-common/colibri_t20-common.c
Normal file
44
board/toradex/colibri_t20-common/colibri_t20-common.c
Normal file
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Lucas Stach
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/board.h>
|
||||
|
||||
#include "colibri_t20-common.h"
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_TEGRA
|
||||
void colibri_t20_common_pin_mux_usb(void)
|
||||
{
|
||||
/* module internal USB bus to connect ethernet chipset */
|
||||
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
|
||||
/* ULPI reference clock output */
|
||||
pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
|
||||
pinmux_tristate_disable(PINGRP_CDEV2);
|
||||
/* PHY reset GPIO */
|
||||
pinmux_tristate_disable(PINGRP_UAC);
|
||||
/* VBus GPIO */
|
||||
pinmux_tristate_disable(PINGRP_DTE);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEGRA_NAND
|
||||
void pin_mux_nand(void)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
|
||||
}
|
||||
#endif
|
16
board/toradex/colibri_t20-common/colibri_t20-common.h
Normal file
16
board/toradex/colibri_t20-common/colibri_t20-common.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Lucas Stach
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
void colibri_t20_common_pin_mux_usb(void);
|
40
board/toradex/colibri_t20_iris/Makefile
Normal file
40
board/toradex/colibri_t20_iris/Makefile
Normal file
|
@ -0,0 +1,40 @@
|
|||
#
|
||||
# (C) Copyright 2012 Lucas Stach
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
$(shell mkdir -p $(obj)../../nvidia/common)
|
||||
$(shell mkdir -p $(obj)../colibri_t20-common)
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := ../../nvidia/common/board.o
|
||||
COBJS += ../colibri_t20-common/colibri_t20-common.o
|
||||
COBJS += $(BOARD).o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
46
board/toradex/colibri_t20_iris/colibri_t20_iris.c
Normal file
46
board/toradex/colibri_t20_iris/colibri_t20_iris.c
Normal file
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Lucas Stach
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/board.h>
|
||||
#include <asm/arch-tegra/mmc.h>
|
||||
|
||||
#include "../colibri_t20-common/colibri_t20-common.h"
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_TEGRA
|
||||
void pin_mux_usb(void)
|
||||
{
|
||||
colibri_t20_common_pin_mux_usb();
|
||||
|
||||
/* USB 1 aka Tegra USB port 3 VBus*/
|
||||
pinmux_tristate_disable(PINGRP_SPIG);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEGRA_MMC
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
|
||||
pinmux_tristate_disable(PINGRP_GMB);
|
||||
|
||||
tegra_mmc_init(0, 4, -1, GPIO_PC7);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
38
board/toradex/dts/tegra20-colibri_t20_iris.dts
Normal file
38
board/toradex/dts/tegra20-colibri_t20_iris.dts
Normal file
|
@ -0,0 +1,38 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ ARCH_CPU_DTS
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri T20";
|
||||
compatible = "toradex,t20", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
usb1 = "/usb@c5000000";
|
||||
usb2 = "/usb@c5004000";
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
|
||||
nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
|
||||
};
|
||||
|
||||
usb@c5008000 {
|
||||
nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
|
||||
};
|
||||
|
||||
nand-controller@70008000 {
|
||||
nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
|
||||
nvidia,width = <8>;
|
||||
nvidia,timing = <15 100 25 80 25 10 15 10 100>;
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
compatible = "nand-flash";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -28,6 +28,7 @@
|
|||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
@ -43,7 +44,7 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct fb_videomode nec_nl6448bc26_09c = {
|
||||
static struct fb_videomode const nec_nl6448bc26_09c = {
|
||||
"NEC_NL6448BC26-09C",
|
||||
60, /* Refresh */
|
||||
640, /* xres */
|
||||
|
@ -590,6 +591,7 @@ int board_mmc_init(bd_t *bis)
|
|||
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
|
|
10
boards.cfg
10
boards.cfg
|
@ -225,7 +225,12 @@ versatileqemu arm arm926ejs versatile armltd
|
|||
integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES
|
||||
integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES
|
||||
ca9x4_ct_vxp arm armv7 vexpress armltd
|
||||
am335x_evm arm armv7 am335x ti am33xx
|
||||
am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1
|
||||
am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2
|
||||
am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3
|
||||
am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4
|
||||
am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5
|
||||
am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
|
||||
highbank arm armv7 highbank - highbank
|
||||
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
|
||||
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
|
||||
|
@ -240,6 +245,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca
|
|||
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
|
||||
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
|
||||
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
|
||||
eco5pk arm armv7 eco5pk 8dtech omap3
|
||||
cm_t35 arm armv7 cm_t35 - omap3
|
||||
omap3_overo arm armv7 overo - omap3
|
||||
omap3_pandora arm armv7 pandora - omap3
|
||||
|
@ -264,6 +270,7 @@ devkit8000 arm armv7 devkit8000 timll
|
|||
mcx arm armv7 mcx htkw omap3
|
||||
tricorder arm armv7 tricorder corscience omap3
|
||||
twister arm armv7 twister technexion omap3
|
||||
nokia_rx51 arm armv7 rx51 nokia omap3
|
||||
omap4_panda arm armv7 panda ti omap4
|
||||
omap4_sdp4430 arm armv7 sdp4430 ti omap4
|
||||
omap5_evm arm armv7 omap5_evm ti omap5
|
||||
|
@ -278,6 +285,7 @@ harmony arm armv7:arm720t harmony nvidia
|
|||
seaboard arm armv7:arm720t seaboard nvidia tegra20
|
||||
ventana arm armv7:arm720t ventana nvidia tegra20
|
||||
whistler arm armv7:arm720t whistler nvidia tegra20
|
||||
colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
|
||||
u8500_href arm armv7 u8500 st-ericsson u8500
|
||||
snowball arm armv7 snowball st-ericsson u8500
|
||||
kzm9g arm armv7 kzm9g kmc rmobile
|
||||
|
|
|
@ -113,13 +113,13 @@ void spl_parse_image_header(const struct image_header *header)
|
|||
}
|
||||
}
|
||||
|
||||
static void __noreturn jump_to_image_no_args(void)
|
||||
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
|
||||
{
|
||||
typedef void __noreturn (*image_entry_noargs_t)(u32 *);
|
||||
image_entry_noargs_t image_entry =
|
||||
(image_entry_noargs_t) spl_image.entry_point;
|
||||
(image_entry_noargs_t) spl_image->entry_point;
|
||||
|
||||
debug("image entry point: 0x%X\n", spl_image.entry_point);
|
||||
debug("image entry point: 0x%X\n", spl_image->entry_point);
|
||||
/* Pass the saved boot_params from rom code */
|
||||
#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
|
||||
image_entry = (image_entry_noargs_t)0x80100000;
|
||||
|
@ -223,7 +223,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
|
|||
default:
|
||||
debug("Unsupported OS image.. Jumping nevertheless..\n");
|
||||
}
|
||||
jump_to_image_no_args();
|
||||
jump_to_image_no_args(&spl_image);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
104
doc/README.nokia_rx51
Normal file
104
doc/README.nokia_rx51
Normal file
|
@ -0,0 +1,104 @@
|
|||
Board: Nokia RX-51 aka N900
|
||||
|
||||
This board definition results in a u-boot.bin which can be chainloaded
|
||||
from NOLO in qemu or on a real N900. It does very little hardware config
|
||||
because NOLO has already configured the board. Only needed is enabling
|
||||
internal eMMC memory via twl4030 regulator which is not enabled by NOLO.
|
||||
|
||||
NOLO is expecting a kernel image and will treat any image it finds in
|
||||
onenand as such. This u-boot is intended to be flashed to the N900 like
|
||||
a kernel. In order to transparently boot the original kernel, it will be
|
||||
appended to u-boot.bin at 0x40000. NOLO will load the entire image into
|
||||
(random) memory and execute u-boot, which saves hw revision, boot reason
|
||||
and boot mode ATAGs set by NOLO. Then the bootscripts will attempt to load
|
||||
uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external
|
||||
SD card or internal eMMC memory. If this fails or keyboard is closed then
|
||||
the appended kernel image will be booted using some generated and some
|
||||
stored ATAGs (see boot order).
|
||||
|
||||
There is support for hardware watchdog. Hardware watchdog is started by
|
||||
NOLO so u-boot must kick watchdog to prevent reboot device (but not very
|
||||
often, max every 2 seconds). There is also support for framebuffer display
|
||||
output with ANSI espace codes and the N900 HW keyboard input. USB tty works
|
||||
but is disabled because it prevents the current Maemo kernel from booting.
|
||||
|
||||
When U-Boot is starting it enable IBE bit in Auxiliary Control Register,
|
||||
which is needed for Thumb-2 ISA support. It is workaround for errata 430973.
|
||||
|
||||
Default boot order:
|
||||
|
||||
* 0. if keyboard is closed boot automatically attached kernel image
|
||||
* 1. try boot from external SD card
|
||||
* 2. try boot from internal eMMC memory
|
||||
* 3. try boot from attached kernel image
|
||||
|
||||
Boot from SD or eMMC in this order:
|
||||
|
||||
* 1.
|
||||
* 1.1 find boot.scr on first fat partition
|
||||
* 1.2 find uImage on first fat parition
|
||||
* 1.3 same order for 2. - 4. fat partition
|
||||
* 2. same as 1. but for ext2/3 partition
|
||||
* 3. same as 1. but for ext4 partition
|
||||
|
||||
|
||||
Available additional commands/variables:
|
||||
|
||||
* run sercon - Use serial port for control
|
||||
* run usbcon - Use usbtty for control
|
||||
* run vgacon - Use framebuffer and HW keyboard for control (default)
|
||||
|
||||
* run sdboot - Boot from external SD card (see boot order)
|
||||
* run emmcboot - Boot from internal eMMC memory (see boot order)
|
||||
* run attachboot - Boot attached kernel image (attached to U-Boot binary)
|
||||
|
||||
* run scriptload - Load boot script ${mmcscriptfile}
|
||||
* run scriptboot - Run loaded boot script
|
||||
* run kernload - Load kernel image ${mmckernfile}
|
||||
* run initrdload - Load initrd image ${mmcinitrdfile}
|
||||
* run kernboot - Boot loaded kernel image
|
||||
* run kerninitrdboot - Boot loaded kernel image with loaded initrd image
|
||||
|
||||
* run trymmcscriptboot - Try to load and boot script ${mmcscriptfile}
|
||||
* run trymmckernboot - Try to load and boot kernel image ${mmckernfile}
|
||||
* run trymmckerninitrdboot - Try to load and boot kernel image ${mmckernfile}
|
||||
with initrd image ${mmcinitrdfile}
|
||||
|
||||
Additional variables for loading files from mmc:
|
||||
|
||||
* mmc ${mmcnum} (0 - external, 1 - internal)
|
||||
* partition number ${mmcpart} (1 - 4)
|
||||
* parition type ${mmctype} (fat, ext2)
|
||||
|
||||
Additional varuables for booting kernel:
|
||||
|
||||
* setup_omap_atag - Add OMAP table into atags structure (needs maemo kernel)
|
||||
* setup_console_atag - Enable serial console in OMAP table
|
||||
* setup_boot_reason_atag - Change boot reason in OMAP table
|
||||
* setup_boot_mode_atag - Change boot mode in OMAP table
|
||||
|
||||
USB TTY:
|
||||
|
||||
Maemo kernel 2.6.28 will crash if u-boot enable usb tty. So USB TTY is disabled.
|
||||
For enabling USB TTY just add this line to file include/configs/nokia_rx51.h
|
||||
|
||||
#define CONFIG_USB_TTY
|
||||
|
||||
|
||||
ONENAND support:
|
||||
|
||||
ONENAND support is disabled because not working yet and cause linux kernel to
|
||||
crash or no access to mtd. For enabling ONENAND support add this line at begin
|
||||
of file include/configs/nokia_rx51.h
|
||||
|
||||
#define ONENAND_SUPPORT
|
||||
|
||||
|
||||
UBIFS support:
|
||||
|
||||
UBIFS support is disabled, because U-Boot image is too big and cannot be
|
||||
flashed with attached zImage to RX-51 kernel nand area. For enabling UBIFS
|
||||
support first enable ONENAND support and then add this line at begin of file
|
||||
include/configs/nokia_rx51.h
|
||||
|
||||
#define UBIFS_SUPPORT
|
|
@ -412,10 +412,10 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
|
|||
|
||||
static void set_sysctl(struct mmc *mmc, uint clock)
|
||||
{
|
||||
int sdhc_clk = gd->sdhc_clk;
|
||||
int div, pre_div;
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
|
||||
int sdhc_clk = cfg->sdhc_clk;
|
||||
uint clk;
|
||||
|
||||
if (clock < mmc->f_min)
|
||||
|
@ -598,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
|
|||
cfg = malloc(sizeof(struct fsl_esdhc_cfg));
|
||||
memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
|
||||
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
||||
cfg->sdhc_clk = gd->sdhc_clk;
|
||||
return fsl_esdhc_initialize(bis, cfg);
|
||||
}
|
||||
|
||||
|
|
|
@ -218,6 +218,34 @@ static uint8_t read_byte(struct mtd_info *mtd)
|
|||
return (uint8_t)dword_read;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read len bytes from the chip into a buffer
|
||||
*
|
||||
* @param mtd MTD device structure
|
||||
* @param buf buffer to store data to
|
||||
* @param len number of bytes to read
|
||||
*
|
||||
* Read function for 8bit bus-width
|
||||
*/
|
||||
static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
||||
{
|
||||
int i, s;
|
||||
unsigned int reg;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
struct nand_drv *info = (struct nand_drv *)chip->priv;
|
||||
|
||||
for (i = 0; i < len; i += 4) {
|
||||
s = (len - i) > 4 ? 4 : len - i;
|
||||
writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
|
||||
((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
|
||||
&info->reg->command);
|
||||
if (!nand_waitfor_cmd_completion(info->reg))
|
||||
puts("Command timeout during read_buf\n");
|
||||
reg = readl(&info->reg->resp);
|
||||
memcpy(buf + i, ®, s);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check NAND status to see if it is ready or not
|
||||
*
|
||||
|
@ -317,6 +345,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
|
|||
switch (command) {
|
||||
case NAND_CMD_READID:
|
||||
writel(NAND_CMD_READID, &info->reg->cmd_reg1);
|
||||
writel(column & 0xFF, &info->reg->addr_reg1);
|
||||
writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
|
||||
| CMD_RX |
|
||||
((4 - 1) << CMD_TRANS_SIZE_SHIFT)
|
||||
|
@ -324,6 +353,12 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
|
|||
&info->reg->command);
|
||||
info->pio_byte_index = 0;
|
||||
break;
|
||||
case NAND_CMD_PARAM:
|
||||
writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
|
||||
writel(column & 0xFF, &info->reg->addr_reg1);
|
||||
writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
|
||||
&info->reg->command);
|
||||
break;
|
||||
case NAND_CMD_READ0:
|
||||
writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
|
||||
writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
|
||||
|
@ -976,6 +1011,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
|
|||
nand->options = LP_OPTIONS;
|
||||
nand->cmdfunc = nand_command;
|
||||
nand->read_byte = read_byte;
|
||||
nand->read_buf = read_buf;
|
||||
nand->ecc.read_page = nand_read_page_hwecc;
|
||||
nand->ecc.write_page = nand_write_page_hwecc;
|
||||
nand->ecc.read_page_raw = nand_read_page_raw;
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if !defined(CONFIG_CONS_INDEX)
|
||||
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
|
||||
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
|
||||
#error "Invalid console index value."
|
||||
#endif
|
||||
|
||||
|
@ -46,12 +46,16 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#error "Console port 3 defined but not configured."
|
||||
#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
|
||||
#error "Console port 4 defined but not configured."
|
||||
#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
|
||||
#error "Console port 5 defined but not configured."
|
||||
#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
|
||||
#error "Console port 6 defined but not configured."
|
||||
#endif
|
||||
|
||||
/* Note: The port number specified in the functions is 1 based.
|
||||
* the array is 0 based.
|
||||
*/
|
||||
static NS16550_t serial_ports[4] = {
|
||||
static NS16550_t serial_ports[6] = {
|
||||
#ifdef CONFIG_SYS_NS16550_COM1
|
||||
(NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
#else
|
||||
|
@ -68,7 +72,17 @@ static NS16550_t serial_ports[4] = {
|
|||
NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NS16550_COM4
|
||||
(NS16550_t)CONFIG_SYS_NS16550_COM4
|
||||
(NS16550_t)CONFIG_SYS_NS16550_COM4,
|
||||
#else
|
||||
NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NS16550_COM5
|
||||
(NS16550_t)CONFIG_SYS_NS16550_COM5,
|
||||
#else
|
||||
NULL,
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NS16550_COM6
|
||||
(NS16550_t)CONFIG_SYS_NS16550_COM6
|
||||
#else
|
||||
NULL
|
||||
#endif
|
||||
|
@ -243,6 +257,12 @@ struct serial_device eserial3_device =
|
|||
DECLARE_ESERIAL_FUNCTIONS(4);
|
||||
struct serial_device eserial4_device =
|
||||
INIT_ESERIAL_STRUCTURE(4, "eserial3");
|
||||
DECLARE_ESERIAL_FUNCTIONS(5);
|
||||
struct serial_device eserial5_device =
|
||||
INIT_ESERIAL_STRUCTURE(5, "eserial4");
|
||||
DECLARE_ESERIAL_FUNCTIONS(6);
|
||||
struct serial_device eserial6_device =
|
||||
INIT_ESERIAL_STRUCTURE(6, "eserial5");
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
|
@ -254,6 +274,10 @@ __weak struct serial_device *default_serial_console(void)
|
|||
return &eserial3_device;
|
||||
#elif CONFIG_CONS_INDEX == 4
|
||||
return &eserial4_device;
|
||||
#elif CONFIG_CONS_INDEX == 5
|
||||
return &eserial5_device;
|
||||
#elif CONFIG_CONS_INDEX == 6
|
||||
return &eserial6_device;
|
||||
#else
|
||||
#error "Bad CONFIG_CONS_INDEX."
|
||||
#endif
|
||||
|
@ -273,4 +297,10 @@ void ns16550_serial_initialize(void)
|
|||
#if defined(CONFIG_SYS_NS16550_COM4)
|
||||
serial_register(&eserial4_device);
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_NS16550_COM5)
|
||||
serial_register(&eserial5_device);
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_NS16550_COM6)
|
||||
serial_register(&eserial6_device);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -385,6 +385,13 @@ static u32 eorx, fgx, bgx; /* color pats */
|
|||
|
||||
static int cfb_do_flush_cache;
|
||||
|
||||
#ifdef CONFIG_CFB_CONSOLE_ANSI
|
||||
static char ansi_buf[10];
|
||||
static int ansi_buf_size;
|
||||
static int ansi_colors_need_revert;
|
||||
static int ansi_cursor_hidden;
|
||||
#endif
|
||||
|
||||
static const int video_font_draw_table8[] = {
|
||||
0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
|
||||
0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
|
||||
|
@ -768,9 +775,97 @@ static void console_back(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void console_newline(void)
|
||||
#ifdef CONFIG_CFB_CONSOLE_ANSI
|
||||
|
||||
static void console_clear(void)
|
||||
{
|
||||
console_row++;
|
||||
#ifdef VIDEO_HW_RECTFILL
|
||||
video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
|
||||
0, /* dest pos x */
|
||||
video_logo_height, /* dest pos y */
|
||||
VIDEO_VISIBLE_COLS, /* frame width */
|
||||
VIDEO_VISIBLE_ROWS, /* frame height */
|
||||
bgx /* fill color */
|
||||
);
|
||||
#else
|
||||
memsetl(CONSOLE_ROW_FIRST, CONSOLE_SIZE, bgx);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void console_cursor_fix(void)
|
||||
{
|
||||
if (console_row < 0)
|
||||
console_row = 0;
|
||||
if (console_row >= CONSOLE_ROWS)
|
||||
console_row = CONSOLE_ROWS - 1;
|
||||
if (console_col < 0)
|
||||
console_col = 0;
|
||||
if (console_col >= CONSOLE_COLS)
|
||||
console_col = CONSOLE_COLS - 1;
|
||||
}
|
||||
|
||||
static void console_cursor_up(int n)
|
||||
{
|
||||
console_row -= n;
|
||||
console_cursor_fix();
|
||||
}
|
||||
|
||||
static void console_cursor_down(int n)
|
||||
{
|
||||
console_row += n;
|
||||
console_cursor_fix();
|
||||
}
|
||||
|
||||
static void console_cursor_left(int n)
|
||||
{
|
||||
console_col -= n;
|
||||
console_cursor_fix();
|
||||
}
|
||||
|
||||
static void console_cursor_right(int n)
|
||||
{
|
||||
console_col += n;
|
||||
console_cursor_fix();
|
||||
}
|
||||
|
||||
static void console_cursor_set_position(int row, int col)
|
||||
{
|
||||
if (console_row != -1)
|
||||
console_row = row;
|
||||
if (console_col != -1)
|
||||
console_col = col;
|
||||
console_cursor_fix();
|
||||
}
|
||||
|
||||
static void console_previousline(int n)
|
||||
{
|
||||
/* FIXME: also scroll terminal ? */
|
||||
console_row -= n;
|
||||
console_cursor_fix();
|
||||
}
|
||||
|
||||
static void console_swap_colors(void)
|
||||
{
|
||||
eorx = fgx;
|
||||
fgx = bgx;
|
||||
bgx = eorx;
|
||||
eorx = fgx ^ bgx;
|
||||
}
|
||||
|
||||
static inline int console_cursor_is_visible(void)
|
||||
{
|
||||
return !ansi_cursor_hidden;
|
||||
}
|
||||
#else
|
||||
static inline int console_cursor_is_visible(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void console_newline(int n)
|
||||
{
|
||||
console_row += n;
|
||||
console_col = 0;
|
||||
|
||||
/* Check if we need to scroll the terminal */
|
||||
|
@ -779,7 +874,7 @@ static void console_newline(void)
|
|||
console_scrollup();
|
||||
|
||||
/* Decrement row number */
|
||||
console_row--;
|
||||
console_row = CONSOLE_ROWS - 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -788,11 +883,12 @@ static void console_cr(void)
|
|||
console_col = 0;
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
static void parse_putc(const char c)
|
||||
{
|
||||
static int nl = 1;
|
||||
|
||||
CURSOR_OFF;
|
||||
if (console_cursor_is_visible())
|
||||
CURSOR_OFF;
|
||||
|
||||
switch (c) {
|
||||
case 13: /* back to first column */
|
||||
|
@ -801,7 +897,7 @@ void video_putc(const char c)
|
|||
|
||||
case '\n': /* next line */
|
||||
if (console_col || (!console_col && nl))
|
||||
console_newline();
|
||||
console_newline(1);
|
||||
nl = 1;
|
||||
break;
|
||||
|
||||
|
@ -810,7 +906,7 @@ void video_putc(const char c)
|
|||
console_col &= ~0x0007;
|
||||
|
||||
if (console_col >= CONSOLE_COLS)
|
||||
console_newline();
|
||||
console_newline(1);
|
||||
break;
|
||||
|
||||
case 8: /* backspace */
|
||||
|
@ -827,11 +923,225 @@ void video_putc(const char c)
|
|||
|
||||
/* check for newline */
|
||||
if (console_col >= CONSOLE_COLS) {
|
||||
console_newline();
|
||||
console_newline(1);
|
||||
nl = 0;
|
||||
}
|
||||
}
|
||||
CURSOR_SET;
|
||||
|
||||
if (console_cursor_is_visible())
|
||||
CURSOR_SET;
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
{
|
||||
#ifdef CONFIG_CFB_CONSOLE_ANSI
|
||||
int i;
|
||||
|
||||
if (c == 27) {
|
||||
for (i = 0; i < ansi_buf_size; ++i)
|
||||
parse_putc(ansi_buf[i]);
|
||||
ansi_buf[0] = 27;
|
||||
ansi_buf_size = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
if (ansi_buf_size > 0) {
|
||||
/*
|
||||
* 0 - ESC
|
||||
* 1 - [
|
||||
* 2 - num1
|
||||
* 3 - ..
|
||||
* 4 - ;
|
||||
* 5 - num2
|
||||
* 6 - ..
|
||||
* - cchar
|
||||
*/
|
||||
int next = 0;
|
||||
|
||||
int flush = 0;
|
||||
int fail = 0;
|
||||
|
||||
int num1 = 0;
|
||||
int num2 = 0;
|
||||
int cchar = 0;
|
||||
|
||||
ansi_buf[ansi_buf_size++] = c;
|
||||
|
||||
if (ansi_buf_size >= sizeof(ansi_buf))
|
||||
fail = 1;
|
||||
|
||||
for (i = 0; i < ansi_buf_size; ++i) {
|
||||
if (fail)
|
||||
break;
|
||||
|
||||
switch (next) {
|
||||
case 0:
|
||||
if (ansi_buf[i] == 27)
|
||||
next = 1;
|
||||
else
|
||||
fail = 1;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
if (ansi_buf[i] == '[')
|
||||
next = 2;
|
||||
else
|
||||
fail = 1;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
|
||||
num1 = ansi_buf[i]-'0';
|
||||
next = 3;
|
||||
} else if (ansi_buf[i] != '?') {
|
||||
--i;
|
||||
num1 = 1;
|
||||
next = 4;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3:
|
||||
if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
|
||||
num1 *= 10;
|
||||
num1 += ansi_buf[i]-'0';
|
||||
} else {
|
||||
--i;
|
||||
next = 4;
|
||||
}
|
||||
break;
|
||||
|
||||
case 4:
|
||||
if (ansi_buf[i] != ';') {
|
||||
--i;
|
||||
next = 7;
|
||||
} else
|
||||
next = 5;
|
||||
break;
|
||||
|
||||
case 5:
|
||||
if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
|
||||
num2 = ansi_buf[i]-'0';
|
||||
next = 6;
|
||||
} else
|
||||
fail = 1;
|
||||
break;
|
||||
|
||||
case 6:
|
||||
if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') {
|
||||
num2 *= 10;
|
||||
num2 += ansi_buf[i]-'0';
|
||||
} else {
|
||||
--i;
|
||||
next = 7;
|
||||
}
|
||||
break;
|
||||
|
||||
case 7:
|
||||
if ((ansi_buf[i] >= 'A' && ansi_buf[i] <= 'H')
|
||||
|| ansi_buf[i] == 'J'
|
||||
|| ansi_buf[i] == 'K'
|
||||
|| ansi_buf[i] == 'h'
|
||||
|| ansi_buf[i] == 'l'
|
||||
|| ansi_buf[i] == 'm') {
|
||||
cchar = ansi_buf[i];
|
||||
flush = 1;
|
||||
} else
|
||||
fail = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (fail) {
|
||||
for (i = 0; i < ansi_buf_size; ++i)
|
||||
parse_putc(ansi_buf[i]);
|
||||
ansi_buf_size = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (flush) {
|
||||
if (!ansi_cursor_hidden)
|
||||
CURSOR_OFF;
|
||||
ansi_buf_size = 0;
|
||||
switch (cchar) {
|
||||
case 'A':
|
||||
/* move cursor num1 rows up */
|
||||
console_cursor_up(num1);
|
||||
break;
|
||||
case 'B':
|
||||
/* move cursor num1 rows down */
|
||||
console_cursor_down(num1);
|
||||
break;
|
||||
case 'C':
|
||||
/* move cursor num1 columns forward */
|
||||
console_cursor_right(num1);
|
||||
break;
|
||||
case 'D':
|
||||
/* move cursor num1 columns back */
|
||||
console_cursor_left(num1);
|
||||
break;
|
||||
case 'E':
|
||||
/* move cursor num1 rows up at begin of row */
|
||||
console_previousline(num1);
|
||||
break;
|
||||
case 'F':
|
||||
/* move cursor num1 rows down at begin of row */
|
||||
console_newline(num1);
|
||||
break;
|
||||
case 'G':
|
||||
/* move cursor to column num1 */
|
||||
console_cursor_set_position(-1, num1-1);
|
||||
break;
|
||||
case 'H':
|
||||
/* move cursor to row num1, column num2 */
|
||||
console_cursor_set_position(num1-1, num2-1);
|
||||
break;
|
||||
case 'J':
|
||||
/* clear console and move cursor to 0, 0 */
|
||||
console_clear();
|
||||
console_cursor_set_position(0, 0);
|
||||
break;
|
||||
case 'K':
|
||||
/* clear line */
|
||||
if (num1 == 0)
|
||||
console_clear_line(console_row,
|
||||
console_col,
|
||||
CONSOLE_COLS-1);
|
||||
else if (num1 == 1)
|
||||
console_clear_line(console_row,
|
||||
0, console_col);
|
||||
else
|
||||
console_clear_line(console_row,
|
||||
0, CONSOLE_COLS-1);
|
||||
break;
|
||||
case 'h':
|
||||
ansi_cursor_hidden = 0;
|
||||
break;
|
||||
case 'l':
|
||||
ansi_cursor_hidden = 1;
|
||||
break;
|
||||
case 'm':
|
||||
if (num1 == 0) { /* reset swapped colors */
|
||||
if (ansi_colors_need_revert) {
|
||||
console_swap_colors();
|
||||
ansi_colors_need_revert = 0;
|
||||
}
|
||||
} else if (num1 == 7) { /* once swap colors */
|
||||
if (!ansi_colors_need_revert) {
|
||||
console_swap_colors();
|
||||
ansi_colors_need_revert = 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (!ansi_cursor_hidden)
|
||||
CURSOR_SET;
|
||||
}
|
||||
} else {
|
||||
parse_putc(c);
|
||||
}
|
||||
#else
|
||||
parse_putc(c);
|
||||
#endif
|
||||
}
|
||||
|
||||
void video_puts(const char *s)
|
||||
|
|
|
@ -45,7 +45,7 @@ static int mxcfb_unmap_video_memory(struct fb_info *fbi);
|
|||
|
||||
/* graphics setup */
|
||||
static GraphicDevice panel;
|
||||
static struct fb_videomode *gmode;
|
||||
static struct fb_videomode const *gmode;
|
||||
static uint8_t gdisp;
|
||||
static uint32_t gpixfmt;
|
||||
|
||||
|
@ -503,7 +503,7 @@ static struct fb_info *mxcfb_init_fbinfo(void)
|
|||
* @return Appropriate error code to the kernel common code
|
||||
*/
|
||||
static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp,
|
||||
struct fb_videomode *mode)
|
||||
struct fb_videomode const *mode)
|
||||
{
|
||||
struct fb_info *fbi;
|
||||
struct mxcfb_info *mxcfbi;
|
||||
|
@ -619,7 +619,9 @@ void video_set_lut(unsigned int index, /* color number */
|
|||
return;
|
||||
}
|
||||
|
||||
int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt)
|
||||
int ipuv3_fb_init(struct fb_videomode const *mode,
|
||||
uint8_t disp,
|
||||
uint32_t pixfmt)
|
||||
{
|
||||
gmode = mode;
|
||||
gdisp = disp;
|
||||
|
|
|
@ -169,9 +169,15 @@
|
|||
/* NS16550 Configuration */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK (48000000)
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
|
||||
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
|
||||
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
|
||||
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
|
||||
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
|
||||
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_I2C
|
||||
|
@ -193,11 +199,7 @@
|
|||
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
|
||||
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SERIAL1 1
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
|
83
include/configs/colibri_t20_iris.h
Normal file
83
include/configs/colibri_t20_iris.h
Normal file
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Lucas Stach
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "tegra20-common.h"
|
||||
|
||||
/* Enable FDT support */
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE tegra20-colibri_t20_iris
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra20 (Colibri) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_TEGRA_ENABLE_UARTA
|
||||
#define CONFIG_TEGRA_UARTA_SDIO1
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* SD/MMC support */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_TEGRA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
|
||||
/* File system support */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
/* USB host support */
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_TEGRA
|
||||
#define CONFIG_USB_ULPI
|
||||
#define CONFIG_USB_ULPI_VIEWPORT
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/* USB networking support */
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
/* NAND support */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_TEGRA_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET (SZ_2M)
|
||||
#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
|
||||
#define CONFIG_ENV_SIZE (SZ_64K)
|
||||
|
||||
/* Debug commands */
|
||||
#define CONFIG_CMD_BDI
|
||||
#define CONFIG_CMD_CACHE
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -43,6 +43,10 @@
|
|||
|
||||
#define MACH_TYPE_EB_CPUX9K2 1977
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#ifndef CONFIG_RAMBOOT
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
||||
|
@ -56,7 +60,6 @@
|
|||
#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
|
||||
|
||||
|
||||
#define CONFIG_BOOT_RETRY_TIME 30
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
|
|
81
include/configs/eco5pk.h
Normal file
81
include/configs/eco5pk.h
Normal file
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (C) 2012 8D Technologies inc.
|
||||
* Based on mt_ventoux.h, original banner below:
|
||||
*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* Copyright (C) 2009 TechNexion Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "tam3517-common.h"
|
||||
|
||||
#undef CONFIG_USB_EHCI
|
||||
#undef CONFIG_USB_EHCI_OMAP
|
||||
#undef CONFIG_USB_OMAP3
|
||||
#undef CONFIG_CMD_USB
|
||||
|
||||
/* Our console port is port3 */
|
||||
#undef CONFIG_CONS_INDEX
|
||||
#undef CONFIG_SYS_NS16550_COM1
|
||||
#undef CONFIG_SERIAL1
|
||||
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3
|
||||
|
||||
#define MACH_TYPE_ECO5_PK 4017
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK
|
||||
|
||||
#define CONFIG_BOOTDELAY 10
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define V_PROMPT "ECO5-PK # "
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
|
||||
/*
|
||||
* Set its own mtdparts, different from common
|
||||
*/
|
||||
#undef MTDIDS_DEFAULT
|
||||
#undef MTDPARTS_DEFAULT
|
||||
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader-nand)," \
|
||||
"1024k(uboot-nand),256k(params-nand)," \
|
||||
"5120k(kernel),-(ubifs)"
|
||||
|
||||
/*
|
||||
* The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten.
|
||||
*/
|
||||
#undef CONFIG_ENV_OFFSET_REDUND
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_SYS_ENV_SECT_SIZE)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
|
||||
"install_kernel=if dhcp $bootfile; then nand erase kernel;" \
|
||||
"nand write $fileaddr kernel; fi\0" \
|
||||
"mtdparts="MTDPARTS_DEFAULT"\0" \
|
||||
"serverip=192.168.142.60\0"
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -72,8 +72,11 @@
|
|||
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
|
||||
|
||||
/* USB Host support */
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_TEGRA
|
||||
#define CONFIG_USB_ULPI
|
||||
#define CONFIG_USB_ULPI_VIEWPORT
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
|
|
|
@ -15,6 +15,8 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
@ -41,8 +43,13 @@
|
|||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Memory Test */
|
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
|
||||
|
|
|
@ -96,7 +96,6 @@
|
|||
/*
|
||||
* Eth Configs
|
||||
*/
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_MII
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
|
|
|
@ -73,7 +73,6 @@
|
|||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* Eth Configs */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_MII
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
|
|
|
@ -58,7 +58,6 @@
|
|||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* Eth Configs */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_MII
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
|
@ -222,6 +221,6 @@
|
|||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_IPUV3_CLK 133000000
|
||||
#define CONFIG_IPUV3_CLK 200000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC_BOUNCE_BUFFER
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
|
@ -164,6 +165,4 @@
|
|||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
@ -45,6 +45,7 @@
|
|||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC_BOUNCE_BUFFER
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
@ -86,7 +87,7 @@
|
|||
"initrd_high=0xffffffff\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
|
@ -168,8 +169,6 @@
|
|||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6Q SabreSD board.
|
||||
* Configuration settings for the Freescale i.MX6Q SabreAuto board.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
@ -15,6 +15,7 @@
|
|||
#define CONFIG_MACH_TYPE 3529
|
||||
#define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
#define CONFIG_CONSOLE_DEV "ttymxc3"
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
|
||||
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
|
||||
|
||||
#include "mx6qsabre_common.h"
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
@ -72,6 +72,7 @@
|
|||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC_BOUNCE_BUFFER
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
@ -119,6 +120,19 @@
|
|||
/* Miscellaneous commands */
|
||||
#define CONFIG_CMD_BMODE
|
||||
|
||||
/* Framebuffer and LCD */
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_IPUV3
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_IPUV3_CLK 260000000
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
@ -234,8 +248,6 @@
|
|||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
#define CONFIG_MACH_TYPE 3980
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
#define CONFIG_CONSOLE_DEV "ttymxc0"
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
|
||||
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
|
||||
|
||||
#include "mx6qsabre_common.h"
|
||||
|
|
452
include/configs/nokia_rx51.h
Normal file
452
include/configs/nokia_rx51.h
Normal file
|
@ -0,0 +1,452 @@
|
|||
/*
|
||||
* (C) Copyright 2011-2012
|
||||
* Pali Rohár <pali.rohar@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Alistair Buxton <a.j.buxton@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board code:
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments.
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* Configuration settings for the Nokia RX-51 aka N900.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
|
||||
#define CONFIG_OMAP /* in a TI OMAP core */
|
||||
#define CONFIG_OMAP34XX /* which is a 34XX */
|
||||
#define CONFIG_OMAP3430 /* which is in a 3430 */
|
||||
#define CONFIG_OMAP3_RX51 /* working with RX51 */
|
||||
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
|
||||
|
||||
/*
|
||||
* Nokia X-Loader loading secondary image to address 0x80400000
|
||||
* NOLO loading boot image to random place, so it doesn't really
|
||||
* matter what we set this to. We have to copy u-boot to this address
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80008000
|
||||
|
||||
#define CONFIG_SDRC /* The chip has SDRC controller */
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap3.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
#undef CONFIG_USE_IRQ /* no support for IRQs */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */
|
||||
#define CONFIG_INITRD_TAG /* enable passing initrd */
|
||||
#define CONFIG_REVISION_TAG /* enable passing revision tag*/
|
||||
#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE (128 << 10)
|
||||
#define CONFIG_UBI_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
|
||||
(128 << 10))
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3 3 /* UART3 on RX-51 */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_OMAP_HSMMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_MUSB_UDC
|
||||
#define CONFIG_MUSB_HDC
|
||||
#define CONFIG_USB_OMAP3
|
||||
#define CONFIG_TWL4030_USB
|
||||
|
||||
/* USB device configuration */
|
||||
#define CONFIG_USB_DEVICE
|
||||
#define CONFIG_USBD_VENDORID 0x0421
|
||||
#define CONFIG_USBD_PRODUCTID 0x01c8
|
||||
#define CONFIG_USBD_MANUFACTURER "Nokia"
|
||||
#define CONFIG_USBD_PRODUCT_NAME "N900"
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */
|
||||
#define CONFIG_CMD_EXT4 /* EXT4 Support */
|
||||
#define CONFIG_CMD_FAT /* FAT support */
|
||||
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */
|
||||
#define CONFIG_CMD_MMC /* MMC support */
|
||||
#define CONFIG_CMD_GPIO /* Enable gpio command */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING /* add command line history */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
|
||||
#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */
|
||||
|
||||
#ifdef ONENAND_SUPPORT
|
||||
|
||||
#define CONFIG_CMD_ONENAND /* ONENAND support */
|
||||
#define CONFIG_CMD_MTDPARTS /* mtd parts support */
|
||||
|
||||
#ifdef UBIFS_SUPPORT
|
||||
#define CONFIG_CMD_UBI /* UBI Support */
|
||||
#define CONFIG_CMD_UBIFS /* UBIFS Support */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* commands not needed from config_cmd_default.h */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||
#undef CONFIG_CMD_IMI /* iminfo */
|
||||
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
|
||||
#undef CONFIG_CMD_NFS /* NFS support */
|
||||
#undef CONFIG_CMD_SAVEENV /* saveenv */
|
||||
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
||||
|
||||
#define CONFIG_OMAP3_SPI
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
||||
|
||||
/*
|
||||
* TWL4030
|
||||
*/
|
||||
#define CONFIG_TWL4030_POWER
|
||||
#define CONFIG_TWL4030_LED
|
||||
#define CONFIG_TWL4030_KEYPAD
|
||||
|
||||
#define CONFIG_OMAP_GPIO
|
||||
#define GPIO_SLIDE 71
|
||||
|
||||
/*
|
||||
* Board ONENAND Info.
|
||||
*/
|
||||
|
||||
#define PART1_NAME "bootloader"
|
||||
#define PART1_SIZE 128
|
||||
#define PART1_MULL 1024
|
||||
#define PART1_SUFF "k"
|
||||
#define PART1_OFFS 0x00000000
|
||||
#define PART1_MASK 0x00000003
|
||||
|
||||
#define PART2_NAME "config"
|
||||
#define PART2_SIZE 384
|
||||
#define PART2_MULL 1024
|
||||
#define PART2_SUFF "k"
|
||||
#define PART2_OFFS 0x00020000
|
||||
#define PART2_MASK 0x00000000
|
||||
|
||||
#define PART3_NAME "log"
|
||||
#define PART3_SIZE 256
|
||||
#define PART3_MULL 1024
|
||||
#define PART3_SUFF "k"
|
||||
#define PART3_OFFS 0x00080000
|
||||
#define PART3_MASK 0x00000000
|
||||
|
||||
#define PART4_NAME "kernel"
|
||||
#define PART4_SIZE 2
|
||||
#define PART4_MULL 1024*1024
|
||||
#define PART4_SUFF "m"
|
||||
#define PART4_OFFS 0x000c0000
|
||||
#define PART4_MASK 0x00000000
|
||||
|
||||
#define PART5_NAME "initfs"
|
||||
#define PART5_SIZE 2
|
||||
#define PART5_MULL 1024*1024
|
||||
#define PART5_SUFF "m"
|
||||
#define PART5_OFFS 0x002c0000
|
||||
#define PART5_MASK 0x00000000
|
||||
|
||||
#define PART6_NAME "rootfs"
|
||||
#define PART6_SIZE 257280
|
||||
#define PART6_MULL 1024
|
||||
#define PART6_SUFF "k"
|
||||
#define PART6_OFFS 0x004c0000
|
||||
#define PART6_MASK 0x00000000
|
||||
|
||||
#ifdef ONENAND_SUPPORT
|
||||
|
||||
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
|
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
|
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
|
||||
#ifdef UBIFS_SUPPORT
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_LZO
|
||||
#endif
|
||||
|
||||
#define MTDIDS_DEFAULT "onenand0=onenand"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=onenand:" \
|
||||
__stringify(PART1_SIZE) PART1_SUFF "(" PART1_NAME ")ro," \
|
||||
__stringify(PART2_SIZE) PART2_SUFF "(" PART2_NAME ")," \
|
||||
__stringify(PART3_SIZE) PART3_SUFF "(" PART3_NAME ")," \
|
||||
__stringify(PART4_SIZE) PART4_SUFF "(" PART4_NAME ")," \
|
||||
__stringify(PART5_SIZE) PART5_SUFF "(" PART5_NAME ")," \
|
||||
"-(" PART6_NAME ")"
|
||||
|
||||
#endif
|
||||
|
||||
/* Watchdog support */
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
/*
|
||||
* Framebuffer
|
||||
*/
|
||||
/* Video console */
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_CFB_CONSOLE_ANSI /* Enable ANSI escape codes in framebuffer */
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define VIDEO_FB_16BPP_PIXEL_SWAP
|
||||
#define VIDEO_FB_16BPP_WORD_SWAP
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
|
||||
/* functions for cfb_console */
|
||||
#define VIDEO_KBD_INIT_FCT rx51_kp_init()
|
||||
#define VIDEO_TSTC_FCT rx51_kp_tstc
|
||||
#define VIDEO_GETC_FCT rx51_kp_getc
|
||||
#ifndef __ASSEMBLY__
|
||||
int rx51_kp_init(void);
|
||||
int rx51_kp_tstc(void);
|
||||
int rx51_kp_getc(void);
|
||||
#endif
|
||||
|
||||
#ifndef MTDPARTS_DEFAULT
|
||||
#define MTDPARTS_DEFAULT
|
||||
#endif
|
||||
|
||||
/* Environment information */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"usbtty=cdc_acm\0" \
|
||||
"stdin=vga\0" \
|
||||
"stdout=vga\0" \
|
||||
"stderr=vga\0" \
|
||||
"setcon=setenv stdin ${con};" \
|
||||
"setenv stdout ${con};" \
|
||||
"setenv stderr ${con}\0" \
|
||||
"sercon=setenv con serial; run setcon\0" \
|
||||
"usbcon=setenv con usbtty; run setcon\0" \
|
||||
"vgacon=setenv con vga; run setcon\0" \
|
||||
"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
|
||||
"switchmmc=mmc dev ${mmcnum}\0" \
|
||||
"kernaddr=0x82008000\0" \
|
||||
"initrdaddr=0x84008000\0" \
|
||||
"scriptaddr=0x86008000\0" \
|
||||
"fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \
|
||||
"${loadaddr} ${mmcfile}\0" \
|
||||
"kernload=setenv loadaddr ${kernaddr};" \
|
||||
"setenv mmcfile ${mmckernfile};" \
|
||||
"run fileload\0" \
|
||||
"initrdload=setenv loadaddr ${initrdaddr};" \
|
||||
"setenv mmcfile ${mmcinitrdfile};" \
|
||||
"run fileload\0" \
|
||||
"scriptload=setenv loadaddr ${scriptaddr};" \
|
||||
"setenv mmcfile ${mmcscriptfile};" \
|
||||
"run fileload\0" \
|
||||
"scriptboot=echo Running ${mmcscriptfile} from mmc " \
|
||||
"${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \
|
||||
"kernboot=echo Booting ${mmckernfile} from mmc " \
|
||||
"${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \
|
||||
"kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\
|
||||
"${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \
|
||||
"attachboot=echo Booting attached kernel image ...;" \
|
||||
"setenv setup_omap_atag 1;" \
|
||||
"bootm ${attkernaddr};" \
|
||||
"setenv setup_omap_atag\0" \
|
||||
"trymmcscriptboot=if run switchmmc; then " \
|
||||
"if run scriptload; then " \
|
||||
"run scriptboot;" \
|
||||
"fi;" \
|
||||
"fi\0" \
|
||||
"trymmckernboot=if run switchmmc; then " \
|
||||
"if run kernload; then " \
|
||||
"run kernboot;" \
|
||||
"fi;" \
|
||||
"fi\0" \
|
||||
"trymmckerninitrdboot=if run switchmmc; then " \
|
||||
"if run initrdload; then " \
|
||||
"if run kernload; then " \
|
||||
"run kerninitrdboot;" \
|
||||
"fi;" \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \
|
||||
"setenv mmckernfile uImage; run trymmckernboot\0" \
|
||||
"trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \
|
||||
"setenv mmcpart 2; run trymmcpartboot;" \
|
||||
"setenv mmcpart 3; run trymmcpartboot;" \
|
||||
"setenv mmcpart 4; run trymmcpartboot\0" \
|
||||
"trymmcboot=if run switchmmc; then " \
|
||||
"setenv mmctype fat;" \
|
||||
"run trymmcallpartboot;" \
|
||||
"setenv mmctype ext2;" \
|
||||
"run trymmcallpartboot;" \
|
||||
"setenv mmctype ext4;" \
|
||||
"run trymmcallpartboot;" \
|
||||
"fi\0" \
|
||||
"emmcboot=setenv mmcnum 1; run trymmcboot\0" \
|
||||
"sdboot=setenv mmcnum 0; run trymmcboot\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_PREBOOT \
|
||||
"if run slide; then true; else run attachboot; fi;" \
|
||||
"echo Extra commands:;" \
|
||||
"echo run sercon - Use serial port for control.;" \
|
||||
"echo run usbcon - Use usbtty for control.;" \
|
||||
"echo run vgacon - Use framebuffer/keyboard.;" \
|
||||
"echo run sdboot - Boot from SD card slot.;" \
|
||||
"echo run emmcboot - Boot internal eMMC memory.;" \
|
||||
"echo run attachboot - Boot attached kernel image.;" \
|
||||
"echo"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"run sdboot;" \
|
||||
"run emmcboot;" \
|
||||
"run attachboot;" \
|
||||
"echo"
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT "Nokia RX-51 # "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
|
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/
|
||||
|
||||
/* default load address */
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
|
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 2
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Attached kernel image
|
||||
*/
|
||||
|
||||
#define SDRAM_SIZE 0x10000000 /* 256 MB */
|
||||
#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
|
||||
|
||||
#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */
|
||||
#define KERNEL_OFFSET 0x40000 /* 256 kB */
|
||||
#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET)
|
||||
#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE)
|
||||
|
||||
/* Reserve protected RAM for attached kernel */
|
||||
#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1)
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -81,6 +81,7 @@
|
|||
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||
|
||||
/* USB Host support */
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_TEGRA
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
|
|
@ -95,8 +95,6 @@
|
|||
#endif
|
||||
|
||||
#define BOOTCMDS_COMMON \
|
||||
"scriptaddr=0x400000\0" \
|
||||
\
|
||||
"rootpart=1\0" \
|
||||
\
|
||||
"script_boot=" \
|
||||
|
@ -140,10 +138,36 @@
|
|||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x10000000\0" \
|
||||
"kernel_addr_r=0x01000000\0" \
|
||||
"fdt_addr_r=0x02000000\0" \
|
||||
"ramdisk_addr_r=0x02100000\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
TEGRA_DEVICE_SETTINGS \
|
||||
"fdt_load=0x01000000\0" \
|
||||
"fdt_high=01100000\0" \
|
||||
MEM_LAYOUT_ENV_SETTINGS \
|
||||
BOOTCMDS_COMMON
|
||||
|
||||
/* overrides for SPL build here */
|
||||
|
|
|
@ -169,8 +169,11 @@
|
|||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0010c000
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
|
@ -184,9 +187,13 @@
|
|||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_RAM_DEVICE
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_NAND_SIMPLE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00108000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x00004000
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
|
||||
#define CONFIG_SPL_STACK 0x000ffffc
|
||||
|
@ -198,5 +205,6 @@
|
|||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
|
||||
|
||||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
#endif /* __TEGRA20_COMMON_H */
|
||||
|
|
|
@ -167,6 +167,7 @@
|
|||
|
||||
struct fsl_esdhc_cfg {
|
||||
u32 esdhc_base;
|
||||
u32 sdhc_clk;
|
||||
};
|
||||
|
||||
/* Select the correct accessors depending on endianess */
|
||||
|
|
|
@ -76,7 +76,9 @@
|
|||
#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
|
||||
#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
|
||||
|
||||
int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
|
||||
int ipuv3_fb_init(struct fb_videomode const *mode,
|
||||
uint8_t disp,
|
||||
uint32_t pixfmt);
|
||||
void ipuv3_fb_shutdown(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -151,6 +151,103 @@
|
|||
#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
|
||||
#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
|
||||
|
||||
/* Power bus message definitions */
|
||||
|
||||
/* The TWL4030/5030 splits its power-management resources (the various
|
||||
* regulators, clock and reset lines) into 3 processor groups - P1, P2 and
|
||||
* P3. These groups can then be configured to transition between sleep, wait-on
|
||||
* and active states by sending messages to the power bus. See Section 5.4.2
|
||||
* Power Resources of TWL4030 TRM
|
||||
*/
|
||||
|
||||
/* Processor groups */
|
||||
#define DEV_GRP_NULL 0x0
|
||||
#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
|
||||
#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
|
||||
#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
|
||||
|
||||
/* Resource groups */
|
||||
#define RES_GRP_RES 0x0 /* Reserved */
|
||||
#define RES_GRP_PP 0x1 /* Power providers */
|
||||
#define RES_GRP_RC 0x2 /* Reset and control */
|
||||
#define RES_GRP_PP_RC 0x3
|
||||
#define RES_GRP_PR 0x4 /* Power references */
|
||||
#define RES_GRP_PP_PR 0x5
|
||||
#define RES_GRP_RC_PR 0x6
|
||||
#define RES_GRP_ALL 0x7 /* All resource groups */
|
||||
|
||||
#define RES_TYPE2_R0 0x0
|
||||
|
||||
#define RES_TYPE_ALL 0x7
|
||||
|
||||
/* Resource states */
|
||||
#define RES_STATE_WRST 0xF
|
||||
#define RES_STATE_ACTIVE 0xE
|
||||
#define RES_STATE_SLEEP 0x8
|
||||
#define RES_STATE_OFF 0x0
|
||||
|
||||
/* Power resources */
|
||||
|
||||
/* Power providers */
|
||||
#define RES_VAUX1 1
|
||||
#define RES_VAUX2 2
|
||||
#define RES_VAUX3 3
|
||||
#define RES_VAUX4 4
|
||||
#define RES_VMMC1 5
|
||||
#define RES_VMMC2 6
|
||||
#define RES_VPLL1 7
|
||||
#define RES_VPLL2 8
|
||||
#define RES_VSIM 9
|
||||
#define RES_VDAC 10
|
||||
#define RES_VINTANA1 11
|
||||
#define RES_VINTANA2 12
|
||||
#define RES_VINTDIG 13
|
||||
#define RES_VIO 14
|
||||
#define RES_VDD1 15
|
||||
#define RES_VDD2 16
|
||||
#define RES_VUSB_1V5 17
|
||||
#define RES_VUSB_1V8 18
|
||||
#define RES_VUSB_3V1 19
|
||||
#define RES_VUSBCP 20
|
||||
#define RES_REGEN 21
|
||||
/* Reset and control */
|
||||
#define RES_NRES_PWRON 22
|
||||
#define RES_CLKEN 23
|
||||
#define RES_SYSEN 24
|
||||
#define RES_HFCLKOUT 25
|
||||
#define RES_32KCLKOUT 26
|
||||
#define RES_RESET 27
|
||||
/* Power Reference */
|
||||
#define RES_Main_Ref 28
|
||||
|
||||
#define TOTAL_RESOURCES 28
|
||||
/*
|
||||
* Power Bus Message Format ... these can be sent individually by Linux,
|
||||
* but are usually part of downloaded scripts that are run when various
|
||||
* power events are triggered.
|
||||
*
|
||||
* Broadcast Message (16 Bits):
|
||||
* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
|
||||
* RES_STATE[3:0]
|
||||
*
|
||||
* Singular Message (16 Bits):
|
||||
* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
|
||||
*/
|
||||
|
||||
#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
|
||||
((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
|
||||
| (type) << 4 | (state))
|
||||
|
||||
#define MSG_SINGULAR(devgrp, id, state) \
|
||||
((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
|
||||
|
||||
#define MSG_BROADCAST_ALL(devgrp, state) \
|
||||
((devgrp) << 5 | (state))
|
||||
|
||||
#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
|
||||
#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
|
||||
#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
|
||||
|
||||
/* Power Managment Receiver */
|
||||
#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
|
||||
#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
|
||||
|
@ -311,6 +408,7 @@
|
|||
#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
|
||||
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
|
||||
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
|
||||
#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
|
||||
|
||||
/* Device Selection in PM Receiver Module */
|
||||
#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
|
||||
|
|
102
tools/imximage.c
102
tools/imximage.c
|
@ -71,6 +71,8 @@ static uint32_t imximage_version;
|
|||
static set_dcd_val_t set_dcd_val;
|
||||
static set_dcd_rst_t set_dcd_rst;
|
||||
static set_imx_hdr_t set_imx_hdr;
|
||||
static uint32_t max_dcd_entries;
|
||||
static uint32_t *header_size_ptr;
|
||||
|
||||
static uint32_t get_cfg_value(char *token, char *name, int linenr)
|
||||
{
|
||||
|
@ -170,13 +172,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
|
|||
{
|
||||
dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
|
||||
|
||||
if (dcd_len > MAX_HW_CFG_SIZE_V1) {
|
||||
fprintf(stderr, "Error: %s[%d] -"
|
||||
"DCD table exceeds maximum size(%d)\n",
|
||||
name, lineno, MAX_HW_CFG_SIZE_V1);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
dcd_v1->preamble.barker = DCD_BARKER;
|
||||
dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
|
||||
}
|
||||
|
@ -190,13 +185,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
|
|||
{
|
||||
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
|
||||
|
||||
if (dcd_len > MAX_HW_CFG_SIZE_V2) {
|
||||
fprintf(stderr, "Error: %s[%d] -"
|
||||
"DCD table exceeds maximum size(%d)\n",
|
||||
name, lineno, MAX_HW_CFG_SIZE_V2);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
dcd_v2->header.tag = DCD_HEADER_TAG;
|
||||
dcd_v2->header.length = cpu_to_be16(
|
||||
dcd_len * sizeof(dcd_addr_data_t) + 8);
|
||||
|
@ -208,84 +196,55 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
|
|||
}
|
||||
|
||||
static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
|
||||
struct stat *sbuf,
|
||||
struct mkimage_params *params)
|
||||
uint32_t entry_point, uint32_t flash_offset)
|
||||
{
|
||||
imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
|
||||
flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
|
||||
dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
|
||||
uint32_t base_offset;
|
||||
|
||||
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
|
||||
if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
|
||||
fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
|
||||
params->imagename);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
uint32_t hdr_base;
|
||||
uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
|
||||
- ((char *)imxhdr));
|
||||
|
||||
/* Set magic number */
|
||||
fhdr_v1->app_code_barker = APP_CODE_BARKER;
|
||||
|
||||
fhdr_v1->app_dest_ptr = params->addr;
|
||||
fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
|
||||
sizeof(struct imx_header);
|
||||
fhdr_v1->app_code_jump_vector = params->ep;
|
||||
hdr_base = entry_point - sizeof(struct imx_header);
|
||||
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
|
||||
fhdr_v1->app_code_jump_vector = entry_point;
|
||||
|
||||
base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
|
||||
fhdr_v1->dcd_ptr_ptr =
|
||||
(uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
|
||||
offsetof(flash_header_v1_t, app_code_jump_vector) +
|
||||
base_offset);
|
||||
|
||||
fhdr_v1->dcd_ptr = base_offset +
|
||||
offsetof(imx_header_v1_t, dcd_table);
|
||||
|
||||
/* The external flash header must be at the end of the DCD table */
|
||||
dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
|
||||
imxhdr->flash_offset +
|
||||
sizeof(struct imx_header);
|
||||
fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
|
||||
fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
|
||||
|
||||
/* Security feature are not supported */
|
||||
fhdr_v1->app_code_csf = 0;
|
||||
fhdr_v1->super_root_key = 0;
|
||||
header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
|
||||
}
|
||||
|
||||
static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
|
||||
struct stat *sbuf,
|
||||
struct mkimage_params *params)
|
||||
uint32_t entry_point, uint32_t flash_offset)
|
||||
{
|
||||
imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
|
||||
flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
|
||||
|
||||
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
|
||||
if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
|
||||
fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
|
||||
params->imagename);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
uint32_t hdr_base;
|
||||
|
||||
/* Set magic number */
|
||||
fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
|
||||
fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
|
||||
fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
|
||||
|
||||
fhdr_v2->entry = params->ep;
|
||||
fhdr_v2->entry = entry_point;
|
||||
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
|
||||
fhdr_v2->self = params->ep - sizeof(struct imx_header);
|
||||
fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
|
||||
|
||||
fhdr_v2->dcd_ptr = fhdr_v2->self +
|
||||
offsetof(imx_header_v2_t, dcd_table);
|
||||
|
||||
fhdr_v2->boot_data_ptr = fhdr_v2->self +
|
||||
offsetof(imx_header_v2_t, boot_data);
|
||||
|
||||
hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
|
||||
hdr_v2->boot_data.size = sbuf->st_size +
|
||||
imxhdr->flash_offset +
|
||||
sizeof(struct imx_header);
|
||||
fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
|
||||
fhdr_v2->boot_data_ptr = hdr_base
|
||||
+ offsetof(imx_header_v2_t, boot_data);
|
||||
hdr_v2->boot_data.start = hdr_base - flash_offset;
|
||||
|
||||
/* Security feature are not supported */
|
||||
fhdr_v2->csf = 0;
|
||||
header_size_ptr = &hdr_v2->boot_data.size;
|
||||
}
|
||||
|
||||
static void set_hdr_func(struct imx_header *imxhdr)
|
||||
|
@ -295,11 +254,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
|
|||
set_dcd_val = set_dcd_val_v1;
|
||||
set_dcd_rst = set_dcd_rst_v1;
|
||||
set_imx_hdr = set_imx_hdr_v1;
|
||||
max_dcd_entries = MAX_HW_CFG_SIZE_V1;
|
||||
break;
|
||||
case IMXIMAGE_V2:
|
||||
set_dcd_val = set_dcd_val_v2;
|
||||
set_dcd_rst = set_dcd_rst_v2;
|
||||
set_imx_hdr = set_imx_hdr_v2;
|
||||
max_dcd_entries = MAX_HW_CFG_SIZE_V2;
|
||||
break;
|
||||
default:
|
||||
err_imximage_version(imximage_version);
|
||||
|
@ -426,8 +387,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
|
|||
value = get_cfg_value(token, name, lineno);
|
||||
(*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
|
||||
|
||||
if (fld == CFG_REG_VALUE)
|
||||
if (fld == CFG_REG_VALUE) {
|
||||
(*dcd_len)++;
|
||||
if (*dcd_len > max_dcd_entries) {
|
||||
fprintf(stderr, "Error: %s[%d] -"
|
||||
"DCD table exceeds maximum size(%d)\n",
|
||||
name, lineno, max_dcd_entries);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
@ -480,6 +448,11 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
|
|||
(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
|
||||
fclose(fd);
|
||||
|
||||
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
|
||||
if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
|
||||
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
return dcd_len;
|
||||
}
|
||||
|
||||
|
@ -541,7 +514,8 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
|
|||
dcd_len = parse_cfg_file(imxhdr, params->imagename);
|
||||
|
||||
/* Set the imx header */
|
||||
(*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
|
||||
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
|
||||
*header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
|
||||
}
|
||||
|
||||
int imximage_check_params(struct mkimage_params *params)
|
||||
|
|
|
@ -168,9 +168,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
|
|||
uint32_t dcd_len,
|
||||
char *name, int lineno);
|
||||
|
||||
typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
|
||||
uint32_t dcd_len,
|
||||
struct stat *sbuf,
|
||||
struct mkimage_params *params);
|
||||
typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
|
||||
uint32_t entry_point, uint32_t flash_offset);
|
||||
|
||||
#endif /* _IMXIMAGE_H_ */
|
||||
|
|
Loading…
Reference in a new issue