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omap3: mem: Define and use common macros
Define common macros to arrive at the values of registers SDRC_ACTIM_CTRLA and SDRC_ACTIM_CTRLB for different memory types. This doesn't make any real change in the execution but helps readability. Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sanjeev Premi
Sandeep Paulraj
parent
92e86c8dae
commit
e3596e35f5
1 changed files with 62 additions and 24 deletions
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@ -54,6 +54,38 @@ enum {
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#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
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(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
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/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
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#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
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#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
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#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
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#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
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#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
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#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
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#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
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#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
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#define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \
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ACTIM_CTRLA_TRFC(a) | \
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ACTIM_CTRLA_TRC(b) | \
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ACTIM_CTRLA_TRAS(b) | \
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ACTIM_CTRLA_TRP(d) | \
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ACTIM_CTRLA_TRCD(e) | \
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ACTIM_CTRLA_TRRD(f) | \
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ACTIM_CTRLA_TDPL(g) | \
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ACTIM_CTRLA_TDAL(h)
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/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
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#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
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#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
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#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
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#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
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#define ACTIM_CTRLB(a,b,c,d) \
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ACTIM_CTRLB_TWTR(a) | \
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ACTIM_CTRLB_TCKE(b) | \
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ACTIM_CTRLB_TXP(b) | \
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ACTIM_CTRLB_TXSR(d)
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
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@ -76,19 +108,21 @@ enum {
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#define INFINEON_TRAS_165 7
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#define INFINEON_TRC_165 10
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#define INFINEON_TRFC_165 12
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#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
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(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
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(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
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(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
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(INFINEON_TDAL_165))
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#define INFINEON_V_ACTIMA_165 \
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ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
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INFINEON_TRAS_165, INFINEON_TRP_165, \
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INFINEON_TRCD_165, INFINEON_TRRD_165, \
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INFINEON_TDPL_165, INFINEON_TDAL_165)
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#define INFINEON_TWTR_165 1
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#define INFINEON_TCKE_165 2
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#define INFINEON_TXP_165 2
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#define INFINEON_XSR_165 20
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#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
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(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
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(INFINEON_TWTR_165 << 16))
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#define INFINEON_V_ACTIMB_165 \
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ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
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INFINEON_TXP_165, INFINEON_XSR_165)
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/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
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* ACTIMA
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@ -114,19 +148,21 @@ enum {
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#define MICRON_TRAS_165 7
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#define MICRON_TRC_165 10
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#define MICRON_TRFC_165 21
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#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
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(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
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(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
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(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
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(MICRON_TDAL_165))
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#define MICRON_V_ACTIMA_165 \
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ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
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MICRON_TRAS_165, MICRON_TRP_165, \
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MICRON_TRCD_165, MICRON_TRRD_165, \
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MICRON_TDPL_165, MICRON_TDAL_165)
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#define MICRON_TWTR_165 1
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#define MICRON_TCKE_165 1
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#define MICRON_XSR_165 23
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#define MICRON_TXP_165 5
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#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
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(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
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(MICRON_TWTR_165 << 16))
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#define MICRON_V_ACTIMB_165 \
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ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
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MICRON_TXP_165, MICRON_XSR_165)
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#define MICRON_RAMTYPE 0x1
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#define MICRON_DDRTYPE 0x0
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@ -180,19 +216,21 @@ enum {
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#define NUMONYX_TRAS_165 7
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#define NUMONYX_TRC_165 10
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#define NUMONYX_TRFC_165 24
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#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
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(NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
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(NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
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(NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
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(NUMONYX_TDAL_165))
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#define NUMONYX_V_ACTIMA_165 \
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ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
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NUMONYX_TRAS_165, NUMONYX_TRP_165, \
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NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
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NUMONYX_TDPL_165, NUMONYX_TDAL_165)
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#define NUMONYX_TWTR_165 2
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#define NUMONYX_TCKE_165 2
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#define NUMONYX_TXP_165 3
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#define NUMONYX_XSR_165 34
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#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
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(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
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(NUMONYX_TWTR_165 << 16))
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#define NUMONYX_V_ACTIMB_165 \
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ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
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NUMONYX_TXP_165, NUMONYX_XSR_165)
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#ifdef CONFIG_OMAP3_INFINEON_DDR
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#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
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