Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-25 22:20:45 +00:00
Code Issues Projects Releases Packages Wiki Activity

arm: dra7xx: clock: Add the prcm changes

Browse source 
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
This commit is contained in:
Lokesh Vutla 2013-02-17 23:33:37 +00:00 committed by Tom Rini
parent d4d986ee27
commit d4e4129c31
6 changed files with 252 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/cpu/armv7/omap4/hw_data.c
View file

@ -290,7 +290,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_2_gpmc_clkctrl,
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,

2
arch/arm/cpu/armv7/omap4/prcm-regs.c
View file

@ -153,7 +153,7 @@ struct prcm_regs const omap4_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_2_gpmc_clkctrl = 0x4a008828,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,

6
arch/arm/cpu/armv7/omap5/hw_data.c
View file

@ -278,7 +278,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_2_gpmc_clkctrl,
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
@ -503,6 +503,10 @@ void hw_data_init(void)
*omap_vcores = &omap5430_volts_es2;
break;
case DRA752_ES1_0:
*prcm = &dra7xx_prcm;
break;
default:
printf("\n INVALID OMAP REVISION ");
}

9
arch/arm/cpu/armv7/omap5/hwinit.c
View file

@ -351,7 +351,12 @@ void reset_cpu(ulong ignored)
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
else
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}
u32 warm_reset(void)
{
return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}

224
arch/arm/cpu/armv7/omap5/prcm-regs.c
View file

@ -156,7 +156,7 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_2_gpmc_clkctrl = 0x4a008828,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@ -296,6 +296,8 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_wkup_bandgap_clkctrl = 0x4ae07888,
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
.prm_rstctrl = 0x4ae07b00,
.prm_rstst = 0x4ae07b04,
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
@ -513,7 +515,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_2_gpmc_clkctrl = 0x4a008828,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
@ -653,6 +655,8 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_wkup_bandgap_clkctrl = 0x4ae07988,
.cm_wkupaon_scrm_clkctrl = 0x4ae07990,
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
.prm_rstctrl = 0x4ae07c00,
.prm_rstst = 0x4ae07c04,
.prm_vc_val_bypass = 0x4ae07ca0,
.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
@ -664,3 +668,219 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
};
struct prcm_regs const dra7xx_prcm = {
/* cm1.ckgen */
.cm_clksel_core = 0x4a005100,
.cm_clksel_abe = 0x4a005108,
.cm_dll_ctrl = 0x4a005110,
.cm_clkmode_dpll_core = 0x4a005120,
.cm_idlest_dpll_core = 0x4a005124,
.cm_autoidle_dpll_core = 0x4a005128,
.cm_clksel_dpll_core = 0x4a00512c,
.cm_div_m2_dpll_core = 0x4a005130,
.cm_div_m3_dpll_core = 0x4a005134,
.cm_div_h11_dpll_core = 0x4a005138,
.cm_div_h12_dpll_core = 0x4a00513c,
.cm_div_h13_dpll_core = 0x4a005140,
.cm_div_h14_dpll_core = 0x4a005144,
.cm_ssc_deltamstep_dpll_core = 0x4a005148,
.cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
.cm_div_h21_dpll_core = 0x4a005150,
.cm_div_h22_dpllcore = 0x4a005154,
.cm_div_h23_dpll_core = 0x4a005158,
.cm_div_h24_dpll_core = 0x4a00515c,
.cm_clkmode_dpll_mpu = 0x4a005160,
.cm_idlest_dpll_mpu = 0x4a005164,
.cm_autoidle_dpll_mpu = 0x4a005168,
.cm_clksel_dpll_mpu = 0x4a00516c,
.cm_div_m2_dpll_mpu = 0x4a005170,
.cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
.cm_bypclk_dpll_mpu = 0x4a00519c,
.cm_clkmode_dpll_iva = 0x4a0051a0,
.cm_idlest_dpll_iva = 0x4a0051a4,
.cm_autoidle_dpll_iva = 0x4a0051a8,
.cm_clksel_dpll_iva = 0x4a0051ac,
.cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
.cm_bypclk_dpll_iva = 0x4a0051dc,
.cm_clkmode_dpll_abe = 0x4a0051e0,
.cm_idlest_dpll_abe = 0x4a0051e4,
.cm_autoidle_dpll_abe = 0x4a0051e8,
.cm_clksel_dpll_abe = 0x4a0051ec,
.cm_div_m2_dpll_abe = 0x4a0051f0,
.cm_div_m3_dpll_abe = 0x4a0051f4,
.cm_ssc_deltamstep_dpll_abe = 0x4a005208,
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
.cm_clkmode_dpll_ddrphy = 0x4a005210,
.cm_idlest_dpll_ddrphy = 0x4a005214,
.cm_autoidle_dpll_ddrphy = 0x4a005218,
.cm_clksel_dpll_ddrphy = 0x4a00521c,
.cm_div_m2_dpll_ddrphy = 0x4a005220,
.cm_div_h11_dpll_ddrphy = 0x4a005228,
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
/* cm1.dsp */
.cm_dsp_clkstctrl = 0x4a005400,
.cm_dsp_dsp_clkctrl = 0x4a005420,
/* cm2.ckgen */
.cm_clksel_usb_60mhz = 0x4a008104,
.cm_clkmode_dpll_per = 0x4a008140,
.cm_idlest_dpll_per = 0x4a008144,
.cm_autoidle_dpll_per = 0x4a008148,
.cm_clksel_dpll_per = 0x4a00814c,
.cm_div_m2_dpll_per = 0x4a008150,
.cm_div_m3_dpll_per = 0x4a008154,
.cm_div_h11_dpll_per = 0x4a008158,
.cm_div_h12_dpll_per = 0x4a00815c,
.cm_div_h13_dpll_per = 0x4a008160,
.cm_div_h14_dpll_per = 0x4a008164,
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
.cm_clkmode_dpll_usb = 0x4a008180,
.cm_idlest_dpll_usb = 0x4a008184,
.cm_autoidle_dpll_usb = 0x4a008188,
.cm_clksel_dpll_usb = 0x4a00818c,
.cm_div_m2_dpll_usb = 0x4a008190,
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
.cm_clkmode_dpll_pcie_ref = 0x4a008200,
.cm_clkmode_apll_pcie = 0x4a00821c,
.cm_idlest_apll_pcie = 0x4a008220,
.cm_div_m2_apll_pcie = 0x4a008224,
.cm_clkvcoldo_apll_pcie = 0x4a008228,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
.cm_l3_1_dynamicdep = 0x4a008708,
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
.cm_l3_gpmc_clkctrl = 0x4a008728,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
.cm_mpu_m3_dynamicdep = 0x4a008908,
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
.cm_sdma_clkstctrl = 0x4a008a00,
.cm_sdma_staticdep = 0x4a008a04,
.cm_sdma_dynamicdep = 0x4a008a08,
.cm_sdma_sdma_clkctrl = 0x4a008a20,
.cm_memif_clkstctrl = 0x4a008b00,
.cm_memif_dmm_clkctrl = 0x4a008b20,
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
.cm_memif_emif_1_clkctrl = 0x4a008b30,
.cm_memif_emif_2_clkctrl = 0x4a008b38,
.cm_memif_dll_clkctrl = 0x4a008b40,
.cm_l4cfg_clkstctrl = 0x4a008d00,
.cm_l4cfg_dynamicdep = 0x4a008d08,
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
.cm_l3instr_clkstctrl = 0x4a008e00,
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
/* cm2.ivahd */
.cm_ivahd_clkstctrl = 0x4a008f00,
.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
.cm_ivahd_sl2_clkctrl = 0x4a008f28,
/* cm2.cam */
.cm_cam_clkstctrl = 0x4a009000,
.cm_cam_vip1_clkctrl = 0x4a009020,
.cm_cam_vip2_clkctrl = 0x4a009028,
.cm_cam_vip3_clkctrl = 0x4a009030,
.cm_cam_lvdsrx_clkctrl = 0x4a009038,
.cm_cam_csi1_clkctrl = 0x4a009040,
.cm_cam_csi2_clkctrl = 0x4a009048,
/* cm2.dss */
.cm_dss_clkstctrl = 0x4a009100,
.cm_dss_dss_clkctrl = 0x4a009120,
/* cm2.sgx */
.cm_sgx_clkstctrl = 0x4a009200,
.cm_sgx_sgx_clkctrl = 0x4a009220,
/* cm2.l3init */
.cm_l3init_clkstctrl = 0x4a009300,
/* cm2.l3init */
.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,
.cm_l4per_dynamicdep = 0x4a009708,
.cm_l4per_gptimer10_clkctrl = 0x4a009728,
.cm_l4per_gptimer11_clkctrl = 0x4a009730,
.cm_l4per_gptimer2_clkctrl = 0x4a009738,
.cm_l4per_gptimer3_clkctrl = 0x4a009740,
.cm_l4per_gptimer4_clkctrl = 0x4a009748,
.cm_l4per_gptimer9_clkctrl = 0x4a009750,
.cm_l4per_elm_clkctrl = 0x4a009758,
.cm_l4per_gpio2_clkctrl = 0x4a009760,
.cm_l4per_gpio3_clkctrl = 0x4a009768,
.cm_l4per_gpio4_clkctrl = 0x4a009770,
.cm_l4per_gpio5_clkctrl = 0x4a009778,
.cm_l4per_gpio6_clkctrl = 0x4a009780,
.cm_l4per_hdq1w_clkctrl = 0x4a009788,
.cm_l4per_i2c1_clkctrl = 0x4a0097a0,
.cm_l4per_i2c2_clkctrl = 0x4a0097a8,
.cm_l4per_i2c3_clkctrl = 0x4a0097b0,
.cm_l4per_i2c4_clkctrl = 0x4a0097b8,
.cm_l4per_l4per_clkctrl = 0x4a0097c0,
.cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
.cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
.cm_l4per_mcspi3_clkctrl = 0x4a009800,
.cm_l4per_mcspi4_clkctrl = 0x4a009808,
.cm_l4per_gpio7_clkctrl = 0x4a009810,
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl = 0x4a009820,
.cm_l4per_mmcsd4_clkctrl = 0x4a009828,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
.cm_l4per_uart4_clkctrl = 0x4a009858,
.cm_l4per_uart5_clkctrl = 0x4a009870,
.cm_l4sec_clkstctrl = 0x4a009880,
.cm_l4sec_staticdep = 0x4a009884,
.cm_l4sec_dynamicdep = 0x4a009888,
.cm_l4sec_aes1_clkctrl = 0x4a0098a0,
.cm_l4sec_aes2_clkctrl = 0x4a0098a8,
.cm_l4sec_des3des_clkctrl = 0x4a0098b0,
.cm_l4sec_rng_clkctrl = 0x4a0098c0,
.cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
.cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
.cm_wkup_clkstctrl = 0x4ae07800,
.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
.cm_wkup_gpio1_clkctrl = 0x4ae07838,
.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
.cm_wkup_sarram_clkctrl = 0x4ae07860,
.cm_wkup_keyboard_clkctrl = 0x4ae07878,
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.prm_rstctrl = 0x4ae07d00,
.prm_rstst = 0x4ae07d04,
.prm_vc_val_bypass = 0x4ae07da0,
.prm_vc_cfg_i2c_mode = 0x4ae07db4,
.prm_vc_cfg_i2c_clk = 0x4ae07db8,
};

17
arch/arm/include/asm/omap_common.h
View file

@ -85,6 +85,7 @@ struct prcm_regs {
u32 cm_div_h12_dpll_ddrphy;
u32 cm_div_h13_dpll_ddrphy;
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 cm_clkmode_dpll_dsp;
u32 cm_shadow_freq_config1;
u32 cm_mpu_mpu_clkctrl;
@ -143,6 +144,11 @@ struct prcm_regs {
u32 cm_ssc_deltamstep_dpll_usb;
u32 cm_ssc_modfreqdiv_dpll_usb;
u32 cm_clkdcoldo_dpll_usb;
u32 cm_clkmode_dpll_pcie_ref;
u32 cm_clkmode_apll_pcie;
u32 cm_idlest_apll_pcie;
u32 cm_div_m2_apll_pcie;
u32 cm_clkvcoldo_apll_pcie;
u32 cm_clkmode_dpll_unipro;
u32 cm_idlest_dpll_unipro;
u32 cm_autoidle_dpll_unipro;
@ -160,7 +166,7 @@ struct prcm_regs {
u32 cm_l3_2_clkstctrl;
u32 cm_l3_2_dynamicdep;
u32 cm_l3_2_l3_2_clkctrl;
u32 cm_l3_2_gpmc_clkctrl;
u32 cm_l3_gpmc_clkctrl;
u32 cm_l3_2_ocmc_ram_clkctrl;
u32 cm_mpu_m3_clkstctrl;
u32 cm_mpu_m3_staticdep;
@ -205,6 +211,12 @@ struct prcm_regs {
u32 cm_cam_clkstctrl;
u32 cm_cam_iss_clkctrl;
u32 cm_cam_fdif_clkctrl;
u32 cm_cam_vip1_clkctrl;
u32 cm_cam_vip2_clkctrl;
u32 cm_cam_vip3_clkctrl;
u32 cm_cam_lvdsrx_clkctrl;
u32 cm_cam_csi1_clkctrl;
u32 cm_cam_csi2_clkctrl;
/* cm2.dss */
u32 cm_dss_clkstctrl;
@ -302,6 +314,8 @@ struct prcm_regs {
u32 cm_wkup_bandgap_clkctrl;
u32 cm_wkupaon_scrm_clkctrl;
u32 cm_wkupaon_io_srcomp_clkctrl;
u32 prm_rstctrl;
u32 prm_rstst;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
@ -485,6 +499,7 @@ extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
extern struct prcm_regs const omap5_es2_prcm;
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];