tegra: fdt: Add NAND controller binding and definitions

Add a NAND controller along with a bindings file for review.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass 2012-07-29 20:53:27 +00:00 committed by Tom Warren
parent 35e1132c88
commit c6af2e7d87
2 changed files with 60 additions and 0 deletions

View file

@ -204,4 +204,11 @@
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;
};
nand: nand-controller@70008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
};
};

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@ -0,0 +1,53 @@
NAND Flash
----------
(there isn't yet a generic binding in Linux, so this describes what is in
U-Boot. There should not be Linux-specific or U-Boot specific binding, just
a binding that describes this hardware. But agreeing a binding in Linux in
the absence of a driver may be beyond my powers.)
The device node for a NAND flash device is as follows:
Required properties :
- compatible : Should be "manufacturer,device", "nand-flash"
This node should sit inside its controller.
Nvidia NAND Controller
----------------------
The device node for a NAND flash controller is as follows:
Optional properties:
nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
phandle, parameter, flags
nvidia,nand-width : bus width of the NAND device in bits
- nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
MAX_TRP_TREA is:
non-EDO mode: Max(tRP, tREA) + 6ns
EDO mode: tRP timing
The 'reg' property should provide the chip select used by the flash chip.
Example
-------
nand-controller@0x70008000 {
compatible = "nvidia,tegra20-nand";
#address-cells = <1>;
#size-cells = <0>;
nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
nvidia,nand-width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
reg = <0>;
compatible = "hynix,hy27uf4g2b", "nand-flash";
};
};