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OMAP5: DPLL core lock for OMAP5432

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No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2012-05-22 00:03:26 +00:00 committed by Albert ARIBAUD
parent 784ab7c545
commit 753bae8c5d
4 changed files with 25 additions and 6 deletions
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8
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -299,8 +299,12 @@ static void setup_dplls(void)
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
"core");
if (omap_revision() != OMAP5432_ES1_0)
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |

13
arch/arm/cpu/armv7/omap-common/emif-common.c
View file

@ -1232,6 +1232,7 @@ void dmm_init(u32 base)
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
u32 omap_rev = omap_revision();
debug(">>sdram_init()\n");
@ -1241,9 +1242,12 @@ void sdram_init(void)
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
if (!in_sdram)
bypass_dpll(&prcm->cm_clkmode_dpll_core);
if (!in_sdram) {
if (omap_rev != OMAP5432_ES1_0)
bypass_dpll(&prcm->cm_clkmode_dpll_core);
else
writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
}
do_sdram_init(EMIF1_BASE);
do_sdram_init(EMIF2_BASE);
@ -1255,7 +1259,8 @@ void sdram_init(void)
}
/* for the shadow registers to take effect */
freq_update_core();
if (omap_rev != OMAP5432_ES1_0)
freq_update_core();
/* Do some testing after the init */
if (!in_sdram) {

5
arch/arm/include/asm/arch-omap4/clocks.h
View file

@ -525,6 +525,11 @@ struct omap4_scrm_regs {
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE 0
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)

5
arch/arm/include/asm/arch-omap5/clocks.h
View file

@ -490,6 +490,11 @@ struct omap5_prcm_regs {
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
#define CM_DLL_CTRL_NO_OVERRIDE 0
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)