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mx53: Turn off child clocks before reconfigure perclk_root

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In addition to ensuring that PERCLK remains at least 2.5 times slower
than the AHB clock, certain steps need to be followed to ensure robust
operation of PERCLK when reconfiguring the PERCLK clock source.

To properly configure the PERCLK clock source, the following steps are
required:

1.In the CCGR registers, gate the clocks to all PERCLK-dependent
  modules.
2.Select the desired input clock for the PERCLK root clock (to be either
  source from the peripherals main source clock or the
  lp_apm clock source). Refer to the CMCBR register,  perclk_lp_apm_sel bit.
3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers
  to the desired setting.  Refer to the CBCDR register for details.
4.In the CCGR registers, enable the desired clocks for the
  PERCLK-dependent module clocks.

If these steps aren't followed, GPT timer may stop and the kernel stops
at "Calibrating delay loop".

Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2011-10-24 08:08:00 +00:00 committed by Albert ARIBAUD
parent 544aa66a66
commit 41c881c0ca
1 changed files with 15 additions and 0 deletions
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15
arch/arm/cpu/armv7/mx5/lowlevel_init.S
View file

@ -180,6 +180,21 @@
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
#else
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
ldr r1, =0x0
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r1, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #CLKCTL_CCGR5]
ldr r1, =0x0F00030F
str r1, [r0, #CLKCTL_CCGR6]
#endif
/* Switch ARM to step clock */