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EXYNOS5: Change parent clock of FIMD to MPLL

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With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Ajay Kumar 2013-01-08 20:42:23 +00:00 committed by Minkyu Kang
parent 9b572852c0
commit 1673f199d9
1 changed files with 1 additions and 1 deletions
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arch/arm/cpu/armv7/exynos/clock.c
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@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void)
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
cfg |= 0x8;
cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
/*