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https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
MIPS: start.S: unify and simplify reset vector handling
Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Daniel Schwierzeck
parent
4dc7412afa
commit
8b1c7345c6
2 changed files with 65 additions and 184 deletions
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@ -47,19 +47,16 @@
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.set pop
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.endm
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#define RVECENT(f,n) \
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b f; nop
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#define XVECENT(f,bev) \
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b f ; \
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li k0,bev
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.set noreorder
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.globl _start
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.text
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_start:
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RVECENT(reset,0) # U-boot entry point
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RVECENT(reset,1) # software reboot
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/* U-boot entry point */
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b reset
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nop
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.org 0x10
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#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
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/*
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* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
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@ -69,141 +66,39 @@ _start:
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* device with correct parameters. This config option is board-specific.
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*/
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.word CONFIG_SYS_XWAY_EBU_BOOTCFG
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.word 0x00000000
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#else
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RVECENT(romReserved,2)
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.word 0x0
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#endif
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RVECENT(romReserved,3)
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RVECENT(romReserved,4)
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RVECENT(romReserved,5)
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RVECENT(romReserved,6)
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RVECENT(romReserved,7)
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RVECENT(romReserved,8)
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RVECENT(romReserved,9)
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RVECENT(romReserved,10)
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RVECENT(romReserved,11)
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RVECENT(romReserved,12)
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RVECENT(romReserved,13)
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RVECENT(romReserved,14)
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RVECENT(romReserved,15)
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RVECENT(romReserved,16)
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RVECENT(romReserved,17)
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RVECENT(romReserved,18)
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RVECENT(romReserved,19)
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RVECENT(romReserved,20)
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RVECENT(romReserved,21)
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RVECENT(romReserved,22)
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RVECENT(romReserved,23)
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RVECENT(romReserved,24)
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RVECENT(romReserved,25)
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RVECENT(romReserved,26)
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RVECENT(romReserved,27)
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RVECENT(romReserved,28)
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RVECENT(romReserved,29)
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RVECENT(romReserved,30)
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RVECENT(romReserved,31)
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RVECENT(romReserved,32)
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RVECENT(romReserved,33)
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RVECENT(romReserved,34)
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RVECENT(romReserved,35)
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RVECENT(romReserved,36)
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RVECENT(romReserved,37)
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RVECENT(romReserved,38)
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RVECENT(romReserved,39)
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RVECENT(romReserved,40)
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RVECENT(romReserved,41)
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RVECENT(romReserved,42)
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RVECENT(romReserved,43)
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RVECENT(romReserved,44)
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RVECENT(romReserved,45)
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RVECENT(romReserved,46)
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RVECENT(romReserved,47)
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RVECENT(romReserved,48)
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RVECENT(romReserved,49)
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RVECENT(romReserved,50)
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RVECENT(romReserved,51)
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RVECENT(romReserved,52)
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RVECENT(romReserved,53)
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RVECENT(romReserved,54)
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RVECENT(romReserved,55)
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RVECENT(romReserved,56)
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RVECENT(romReserved,57)
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RVECENT(romReserved,58)
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RVECENT(romReserved,59)
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RVECENT(romReserved,60)
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RVECENT(romReserved,61)
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RVECENT(romReserved,62)
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RVECENT(romReserved,63)
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XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
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RVECENT(romReserved,65)
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RVECENT(romReserved,66)
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RVECENT(romReserved,67)
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RVECENT(romReserved,68)
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RVECENT(romReserved,69)
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RVECENT(romReserved,70)
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RVECENT(romReserved,71)
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RVECENT(romReserved,72)
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RVECENT(romReserved,73)
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RVECENT(romReserved,74)
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RVECENT(romReserved,75)
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RVECENT(romReserved,76)
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RVECENT(romReserved,77)
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RVECENT(romReserved,78)
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RVECENT(romReserved,79)
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XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
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RVECENT(romReserved,81)
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RVECENT(romReserved,82)
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RVECENT(romReserved,83)
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RVECENT(romReserved,84)
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RVECENT(romReserved,85)
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RVECENT(romReserved,86)
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RVECENT(romReserved,87)
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RVECENT(romReserved,88)
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RVECENT(romReserved,89)
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RVECENT(romReserved,90)
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RVECENT(romReserved,91)
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RVECENT(romReserved,92)
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RVECENT(romReserved,93)
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RVECENT(romReserved,94)
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RVECENT(romReserved,95)
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XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
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RVECENT(romReserved,97)
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RVECENT(romReserved,98)
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RVECENT(romReserved,99)
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RVECENT(romReserved,100)
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RVECENT(romReserved,101)
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RVECENT(romReserved,102)
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RVECENT(romReserved,103)
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RVECENT(romReserved,104)
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RVECENT(romReserved,105)
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RVECENT(romReserved,106)
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RVECENT(romReserved,107)
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RVECENT(romReserved,108)
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RVECENT(romReserved,109)
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RVECENT(romReserved,110)
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RVECENT(romReserved,111)
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XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
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RVECENT(romReserved,113)
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RVECENT(romReserved,114)
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RVECENT(romReserved,115)
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RVECENT(romReserved,116)
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RVECENT(romReserved,116)
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RVECENT(romReserved,118)
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RVECENT(romReserved,119)
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RVECENT(romReserved,120)
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RVECENT(romReserved,121)
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RVECENT(romReserved,122)
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RVECENT(romReserved,123)
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RVECENT(romReserved,124)
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RVECENT(romReserved,125)
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RVECENT(romReserved,126)
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RVECENT(romReserved,127)
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/*
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* We hope there are no more reserved vectors!
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* 128 * 8 == 1024 == 0x400
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* so this is address R_VEC+0x400 == 0xbfc00400
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*/
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.org 0x200
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/* TLB refill, 32 bit task */
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1: b 1b
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nop
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.org 0x280
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/* XTLB refill, 64 bit task */
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1: b 1b
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nop
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.org 0x300
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/* Cache error exception */
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1: b 1b
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nop
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.org 0x380
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/* General exception */
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1: b 1b
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nop
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.org 0x400
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/* Catch interrupt exceptions */
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1: b 1b
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nop
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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.align 4
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reset:
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@ -351,12 +246,3 @@ in_ram:
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move a1, s2
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.end relocate_code
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/* Exception handlers */
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romReserved:
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b romReserved
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nop
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romExcHandle:
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b romExcHandle
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nop
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@ -52,40 +52,40 @@
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.globl _start
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.text
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_start:
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.org 0x000
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/* U-boot entry point */
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b reset
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nop
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.org 0x080
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b romReserved
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nop
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.org 0x100
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b romReserved
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nop
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.org 0x180
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b romReserved
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nop
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.org 0x200
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b romReserved
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nop
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.org 0x280
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b romReserved
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nop
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.org 0x300
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b romReserved
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nop
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.org 0x380
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b romReserved
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nop
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.org 0x480
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b romReserved
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/* TLB refill, 32 bit task */
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1: b 1b
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nop
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.org 0x280
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/* XTLB refill, 64 bit task */
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1: b 1b
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nop
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.org 0x300
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/* Cache error exception */
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1: b 1b
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nop
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.org 0x380
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/* General exception */
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1: b 1b
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nop
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.org 0x400
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/* Catch interrupt exceptions */
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1: b 1b
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nop
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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/*
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* We hope there are no more reserved vectors!
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* 128 * 8 == 1024 == 0x400
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* so this is address R_VEC+0x400 == 0xbfc00400
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*/
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.org 0x500
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.align 4
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reset:
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@ -238,8 +238,3 @@ in_ram:
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move a1, s2
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.end relocate_code
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/* Exception handlers */
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romReserved:
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b romReserved
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nop
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