Ajay Kumar 1673f199d9 EXYNOS5: Change parent clock of FIMD to MPLL ... With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2013-01-10 10:19:47 +09:00
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arm	EXYNOS5: Change parent clock of FIMD to MPLL	2013-01-10 10:19:47 +09:00
avr32	common: Discard the __u_boot_cmd section	2012-10-22 08:29:42 -07:00
blackfin	common: Discard the __u_boot_cmd section	2012-10-22 08:29:42 -07:00
m68k	env: Use getenv_yesno() more generally	2012-12-13 11:46:55 -07:00
microblaze	env: Use getenv_yesno() more generally	2012-12-13 11:46:55 -07:00
mips	mips: serial: Fix busted manual relocation	2012-12-12 13:20:24 +01:00
nds32	common: Discard the __u_boot_cmd section	2012-10-22 08:29:42 -07:00
nios2	nios2: remove asm/status_led.h	2012-11-10 19:45:58 +08:00
openrisc	openrisc: Change bi_baudrate and global data baudrate to int	2012-10-19 15:25:45 -07:00
powerpc	env: Use getenv_yesno() more generally	2012-12-13 11:46:55 -07:00
sandbox	common: Discard the __u_boot_cmd section	2012-10-22 08:29:42 -07:00
sh	sh: fix trigger_address_error()	2012-11-30 15:06:04 +09:00
sparc	env: Use getenv_yesno() more generally	2012-12-13 11:46:55 -07:00
x86	x86: Build vga video code only if CONFIG_VIDEO_VGA is defined	2012-12-06 14:30:44 -08:00
.gitignore	update include/asm/ gitignore after move	2010-05-07 00:17:30 +02:00