powerpc/8xxx: Add support for interactive DDR programming interface

Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash. To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax: setenv ddr_interactive on After reset, U-boot prompts before initializing DDR controllers FSL DDR> The available commands are print print SPD and intermediate computed data reset reboot machine recompute reload SPD and options to default and recompute regs edit modify spd, parameter, or option compute recompute registers from current next_step to end next_step shows current next_step help this message go program the memory controller and continue with u-boot The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2024-11-10 15:14:43 +00:00 · 2011-09-16 13:21:35 -07:00 · 2011-09-16 13:21:35 -07:00 · 6f5e1dc531
commit 6f5e1dc531
parent 0841ca90f2
7 changed files with 1880 additions and 18 deletions
--- a/3
+++ b/3
@ -3099,6 +3099,9 @@ Low Level (hardware related) configuration options:
 		parameters are extracted from datasheet and hard-coded into
 		header files or board specific files.

+- CONFIG_FSL_DDR_INTERACTIVE
+		Enable interactive DDR debugging. See doc/README.fsl-ddr.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
--- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
@ -1,5 +1,5 @@
 #
-# Copyright 2008 Freescale Semiconductor, Inc.
+# Copyright 2008-2011 Freescale Semiconductor, Inc.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License
@ -30,6 +30,7 @@ COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
 endif

+COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o

 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@ -56,32 +56,46 @@ typedef struct {
 #define STEP_PROGRAM_REGS            (1 << 6)
 #define STEP_ALL                     0xFFF

-extern unsigned long long
+unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				       unsigned int size_only);

-extern const char * step_to_string(unsigned int step);
+const char *step_to_string(unsigned int step);

-extern unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			       fsl_ddr_cfg_regs_t *ddr,
 			       const common_timing_params_t *common_dimm,
 			       const dimm_params_t *dimm_parameters,
 			       unsigned int dbw_capacity_adjust,
 			       unsigned int size_only);
-extern unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
-				      common_timing_params_t *outpdimm,
-				      unsigned int number_of_dimms);
-extern unsigned int populate_memctl_options(int all_DIMMs_registered,
+unsigned int compute_lowest_common_dimm_parameters(
+				const dimm_params_t *dimm_params,
+				common_timing_params_t *outpdimm,
+				unsigned int number_of_dimms);
+unsigned int populate_memctl_options(int all_DIMMs_registered,
 				memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
-extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
+void check_interleaving_options(fsl_ddr_info_t *pinfo);

-extern unsigned int mclk_to_picos(unsigned int mclk);
-extern unsigned int get_memory_clk_period_ps(void);
-extern unsigned int picos_to_mclk(unsigned int picos);
+unsigned int mclk_to_picos(unsigned int mclk);
+unsigned int get_memory_clk_period_ps(void);
+unsigned int picos_to_mclk(unsigned int picos);
+void fsl_ddr_set_lawbar(
+		const common_timing_params_t *memctl_common_params,
+		unsigned int memctl_interleaved,
+		unsigned int ctrl_num);
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo);
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+			   unsigned int ctrl_num);
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+
+/* processor specific function */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num);

 /* board specific function */
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@ -135,7 +135,6 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 *				|  interleaving
 */

-#ifdef DEBUG
 const char *step_string_tbl[] = {
 	"STEP_GET_SPD",
 	"STEP_COMPUTE_DIMM_PARMS",
@ -156,7 +155,6 @@ const char * step_to_string(unsigned int step) {

 	return step_string_tbl[s];
 }
-#endif

 int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			  unsigned int dbw_cap_adj[],
@ -499,7 +497,12 @@ phys_size_t fsl_ddr_sdram(void)
 	memset(&info, 0, sizeof(fsl_ddr_info_t));

 	/* Compute it once normally. */
-	total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
+#ifdef CONFIG_FSL_DDR_INTERACTIVE
+	if (getenv("ddr_interactive"))
+		total_memory = fsl_ddr_interactive(&info);
+	else
+#endif
+		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);

 	/* Check for memory controller interleaving. */
 	memctl_interleaved = 0;
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@ -222,3 +222,153 @@ Single slot system

 Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf

+
+Interactive DDR debugging
+===========================
+
+For DDR parameter tuning up and debugging, the interactive DDR debugging can
+be activated by saving an environment variable "ddr_interactive". The value
+doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR
+controller. The available commands can be seen by typing "help".
+
+The example flow of using interactive debugging is
+type command "compute" to calculate the parameters from the default
+type command "print" with arguments to show SPD, options, registers
+type command "edit" with arguments to change any if desired
+type command "go" to continue calculation and enable DDR controller
+type command "reset" to reset the board
+type command "recompute" to reload SPD and start over
+
+Note, check "next_step" to show the flow. For example, after edit opts, the
+next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
+STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled
+with current setting without further calculation.
+
+The detail syntax for each commands are
+
+print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
+	c<n>		- the controller number, eg. c0, c1
+	d<n>		- the DIMM number, eg. d0, d1
+	spd		- print SPD data
+	dimmparms	- DIMM paramaters, calcualted from SPD
+	commonparms	- lowest common parameters for all DIMMs
+	opts		- options
+	addresses	- address assignment (not implemented yet)
+	regs		- controller registers
+
+edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
+	c<n>		- the controller number, eg. c0, c1
+	d<n>		- the DIMM number, eg. d0, d1
+	spd		- print SPD data
+	dimmparms	- DIMM paramaters, calcualted from SPD
+	commonparms	- lowest common parameters for all DIMMs
+	opts		- options
+	addresses	- address assignment (not implemented yet)
+	regs		- controller registers
+	<element>	- name of the modified element
+			  byte number if the object is SPD
+	<value>		- decimal or heximal (prefixed with 0x) numbers
+
+reset
+	no arguement	- reset the board
+
+recompute
+	no argument	- reload SPD and start over
+
+compute
+	no argument	- recompute from current next_step
+
+next_step
+	no argument	- show current next_step
+
+help
+	no argument	- print a list of all commands
+
+go
+	no argument	- program memory controller(s) and continue with U-boot
+
+Examples of debugging flow
+
+	FSL DDR>compute
+	Detected UDIMM UG51U6400N8SU-ACF
+	SL DDR>print
+	print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
+	FSL DDR>print dimmparms
+	DIMM parameters:  Controller=0 DIMM=0
+	DIMM organization parameters:
+	module part name = UG51U6400N8SU-ACF
+	rank_density = 2147483648 bytes (2048 megabytes)
+	capacity = 4294967296 bytes (4096 megabytes)
+	burst_lengths_bitmask = 0C
+	base_addresss = 0 (00000000 00000000)
+	n_ranks = 2
+	data_width = 64
+	primary_sdram_width = 64
+	ec_sdram_width = 0
+	registered_dimm = 0
+	n_row_addr = 15
+	n_col_addr = 10
+	edc_config = 0
+	n_banks_per_sdram_device = 8
+	tCKmin_X_ps = 1500
+	tCKmin_X_minus_1_ps = 0
+	tCKmin_X_minus_2_ps = 0
+	tCKmax_ps = 0
+	caslat_X = 960
+	tAA_ps = 13125
+	caslat_X_minus_1 = 0
+	caslat_X_minus_2 = 0
+	caslat_lowest_derated = 0
+	tRCD_ps = 13125
+	tRP_ps = 13125
+	tRAS_ps = 36000
+	tWR_ps = 15000
+	tWTR_ps = 7500
+	tRFC_ps = 160000
+	tRRD_ps = 6000
+	tRC_ps = 49125
+	refresh_rate_ps = 7800000
+	tIS_ps = 0
+	tIH_ps = 0
+	tDS_ps = 0
+	tDH_ps = 0
+	tRTP_ps = 7500
+	tDQSQ_max_ps = 0
+	tQHS_ps = 0
+	FSL DDR>edit c0 opts ECC_mode 0
+	FSL DDR>edit c0 regs cs0_bnds 0x000000FF
+	FSL DDR>go
+	2 GiB left unmapped
+	4 GiB (DDR3, 64-bit, CL=9, ECC off)
+	       DDR Chip-Select Interleaving Mode: CS0+CS1
+	Testing 0x00000000 - 0x7fffffff
+	Testing 0x80000000 - 0xffffffff
+	Remap DDR 2 GiB left unmapped
+
+	POST memory PASSED
+	Flash: 128 MiB
+	L2:    128 KB enabled
+	Corenet Platform Cache: 1024 KB enabled
+	SERDES: timeout resetting bank 3
+	SRIO1: disabled
+	SRIO2: disabled
+	MMC:  FSL_ESDHC: 0
+	EEPROM: Invalid ID (ff ff ff ff)
+	PCIe1: disabled
+	PCIe2: Root Complex, x1, regs @ 0xfe201000
+	  01:00.0     - 8086:10d3 - Network controller
+	PCIe2: Bus 00 - 01
+	PCIe3: disabled
+	In:    serial
+	Out:   serial
+	Err:   serial
+	Net:   Initializing Fman
+	Fman1: Uploading microcode version 101.8.0
+	e1000: 00:1b:21:81:d2:e0
+	FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
+	Warning: e1000#0 MAC addresses don't match:
+	Address in SROM is         00:1b:21:81:d2:e0
+	Address in environment is  00:e0:0c:00:ea:05
+
+	Hit any key to stop autoboot:  0
+	=>
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@ -232,7 +232,7 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
-#define CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_FSL_DDR_INTERACTIVE

 #ifdef CONFIG_P1020MBG
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G