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Tegra: Change Tegra20 to Tegra in common code, prep for T30

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Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Tom Warren 2012-09-04 17:00:24 -07:00
parent 22e7394021
commit 29f3e3f248
37 changed files with 143 additions and 146 deletions
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8
arch/arm/cpu/arm720t/tegra20/cpu.c
View file

@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable)
static int is_cpu_powered(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
/* Remove the clamps on the CPU I/O signals */
@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void)
static void powerup_cpu(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
@ -157,7 +157,7 @@ static void powerup_cpu(void)
static void enable_cpu_power_rail(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_cntrl);

2
arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
View file

@ -46,7 +46,7 @@
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
puts("Entering RCM...\n");
udelay(50000);

2
arch/arm/cpu/tegra20-common/Makefile
View file

@ -33,7 +33,7 @@ LIB = $(obj)lib$(SOC)-common.o
SOBJS += lowlevel_init.o
COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS-$(CONFIG_TEGRA_PMU) += pmu.o

6
arch/arm/cpu/tegra20-common/ap20.c
View file

@ -32,7 +32,7 @@
int tegra_get_chip_type(void)
{
struct apb_misc_gp_ctlr *gp;
struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
uint tegra_sku_id, rev;
/*
@ -40,7 +40,7 @@ int tegra_get_chip_type(void)
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
* Tegra30
*/
gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
tegra_sku_id = readl(&fuse->sku_info) & 0xff;
@ -101,7 +101,7 @@ static u32 get_odmdata(void)
static void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 odmdata;
int i;

14
arch/arm/cpu/tegra20-common/board.c
View file

@ -47,7 +47,7 @@ enum {
unsigned int query_sdram_size(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_scratch20);
@ -81,11 +81,11 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
#elif defined(CONFIG_TEGRA20_UARTA_GPU)
#elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
#else
FUNCMUX_UART1_IRRX_IRTX,
@ -125,13 +125,13 @@ void board_init_uart_f(void)
{
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA20_ENABLE_UARTA
#ifdef CONFIG_TEGRA_ENABLE_UARTA
uart_ids |= UARTA;
#endif
#ifdef CONFIG_TEGRA20_ENABLE_UARTB
#ifdef CONFIG_TEGRA_ENABLE_UARTB
uart_ids |= UARTB;
#endif
#ifdef CONFIG_TEGRA20_ENABLE_UARTD
#ifdef CONFIG_TEGRA_ENABLE_UARTD
uart_ids |= UARTD;
#endif
setup_uarts(uart_ids);

14
arch/arm/cpu/tegra20-common/warmboot.c
View file

@ -39,7 +39,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_TEGRA_CLOCK_SCALING
#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
#endif
/*
@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void)
u32 ram_code;
struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
union scratch2_reg scratch2;
union scratch4_reg scratch4;
@ -205,7 +205,7 @@ static u32 get_major_version(void)
{
u32 major_id;
struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
HIDREV_MAJORPREV_SHIFT;
@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse)
static int ap20_is_odm_production_mode(void)
{
struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (!is_failure_analysis_mode(fuse) &&
is_odm_production_mode_fuse_set(fuse))
@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void)
static int ap20_is_production_mode(void)
{
struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (get_major_version() == 0)
return 1;
@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void)
{
u32 chip_id;
struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
HIDREV_CHIPID_SHIFT;

2
arch/arm/cpu/tegra20-common/warmboot_avp.c
View file

@ -38,7 +38,7 @@
void wb_start(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;

3
arch/arm/include/asm/arch-tegra20/ap20.h
View file

@ -95,9 +95,6 @@
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
/* Start up the tegra20 SOC */
void tegra20_start(void);
/* This is the main entry into U-Boot, used by the Cortex-A9 */
extern void _start(void);

8
arch/arm/include/asm/arch-tegra20/mmc.h
View file

@ -19,9 +19,9 @@
* MA 02111-1307 USA
*/
#ifndef _TEGRA20_MMC_H_
#define _TEGRA20_MMC_H_
#ifndef _TEGRA_MMC_H_
#define _TEGRA_MMC_H_
int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
#endif /* TEGRA20_MMC_H_ */
#endif /* _TEGRA_MMC_H_ */

4
arch/arm/include/asm/arch-tegra20/sys_proto.h
View file

@ -24,12 +24,12 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
struct tegra20_sysinfo {
struct tegra_sysinfo {
char *board_string;
};
void invalidate_dcache(void);
extern const struct tegra20_sysinfo sysinfo;
extern const struct tegra_sysinfo sysinfo;
#endif

14
arch/arm/include/asm/arch-tegra20/tegra20.h
View file

@ -33,22 +33,22 @@
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define TEGRA20_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
#define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
#define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_CSITE_BASE 0x70040000
#define TEGRA_USB1_BASE 0xC5000000
#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
@ -86,7 +86,7 @@ enum {
};
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL TEGRA20_PMC_BASE
#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
#endif /* TEGRA20_H */

12
drivers/mmc/tegra_mmc.h → arch/arm/include/asm/arch-tegra20/tegra_mmc.h
View file

@ -22,13 +22,13 @@
#ifndef __TEGRA_MMC_H_
#define __TEGRA_MMC_H_
#define TEGRA20_SDMMC1_BASE 0xC8000000
#define TEGRA20_SDMMC2_BASE 0xC8000200
#define TEGRA20_SDMMC3_BASE 0xC8000400
#define TEGRA20_SDMMC4_BASE 0xC8000600
#define TEGRA_SDMMC1_BASE 0xC8000000
#define TEGRA_SDMMC2_BASE 0xC8000200
#define TEGRA_SDMMC3_BASE 0xC8000400
#define TEGRA_SDMMC4_BASE 0xC8000600
#ifndef __ASSEMBLY__
struct tegra20_mmc {
struct tegra_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
@ -118,7 +118,7 @@ struct tegra20_mmc {
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
struct mmc_host {
struct tegra20_mmc *reg;
struct tegra_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */

2
arch/arm/include/asm/arch-tegra20/tegra_spi.h
View file

@ -70,6 +70,6 @@ struct spi_tegra {
#define SPI_STAT_CUR_BLKCNT (1 << 15)
#define SPI_TIMEOUT 1000
#define TEGRA20_SPI_MAX_FREQ 52000000
#define TEGRA_SPI_MAX_FREQ 52000000
#endif /* _TEGRA_SPI_H_ */

4
arch/arm/include/asm/arch-tegra20/timer.h
View file

@ -21,8 +21,8 @@
/* Tegra20 timer functions */
#ifndef _TEGRA20_TIMER_H
#define _TEGRA20_TIMER_H
#ifndef _TEGRA_TIMER_H
#define _TEGRA_TIMER_H
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);

2
board/avionic-design/common/tamonten.c
View file

@ -78,7 +78,7 @@ int board_mmc_init(bd_t *bd)
pin_mux_mmc();
/* init dev 0, SD slot, with 4-bit bus */
tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
return 0;
}

4
board/compal/paz00/paz00.c
View file

@ -70,11 +70,11 @@ int board_mmc_init(bd_t *bd)
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
tegra20_mmc_init(0, 4, -1, -1);
tegra_mmc_init(0, 4, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
return 0;
}

4
board/compulab/trimslice/trimslice.c
View file

@ -69,10 +69,10 @@ int board_mmc_init(bd_t *bd)
pin_mux_mmc();
/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
tegra20_mmc_init(0, 4, -1, GPIO_PP1);
tegra_mmc_init(0, 4, -1, GPIO_PP1);
/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
tegra20_mmc_init(3, 4, -1, -1);
tegra_mmc_init(3, 4, -1, -1);
return 0;
}

8
board/nvidia/common/board.c
View file

@ -45,8 +45,8 @@
DECLARE_GLOBAL_DATA_PTR;
const struct tegra20_sysinfo sysinfo = {
CONFIG_TEGRA20_BOARD_STRING
const struct tegra_sysinfo sysinfo = {
CONFIG_TEGRA_BOARD_STRING
};
#ifndef CONFIG_SPL_BUILD
@ -79,7 +79,7 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
static void power_det_init(void)
{
#if defined(CONFIG_TEGRA20)
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
/* turn off power detects */
writel(0, &pmc->pmc_pwr_det_latch);
@ -132,7 +132,7 @@ int board_init(void)
board_usb_init(gd->fdt_blob);
#endif
#ifdef CONFIG_TEGRA20_LP0
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();

4
board/nvidia/harmony/harmony.c
View file

@ -73,11 +73,11 @@ int board_mmc_init(bd_t *bd)
debug("board_mmc_init: init SD slot J26\n");
/* init dev 0, SD slot J26, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
debug("board_mmc_init: init SD slot J5\n");
/* init dev 2, SD slot J5, with 4-bit bus */
tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
return 0;
}

4
board/nvidia/seaboard/seaboard.c
View file

@ -81,11 +81,11 @@ int board_mmc_init(bd_t *bd)
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
tegra20_mmc_init(0, 4, -1, -1);
tegra_mmc_init(0, 4, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 1, SD slot, with 4-bit bus */
tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
return 0;
}

4
board/nvidia/whistler/whistler.c
View file

@ -81,10 +81,10 @@ int board_mmc_init(bd_t *bd)
pin_mux_mmc();
/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
tegra20_mmc_init(0, 8, -1, -1);
tegra_mmc_init(0, 8, -1, -1);
/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
tegra20_mmc_init(1, 8, -1, -1);
tegra_mmc_init(1, 8, -1, -1);
return 0;
}

8
drivers/gpio/tegra_gpio.c
View file

@ -34,10 +34,10 @@
#include <asm/gpio.h>
enum {
TEGRA20_CMD_INFO,
TEGRA20_CMD_PORT,
TEGRA20_CMD_OUTPUT,
TEGRA20_CMD_INPUT,
TEGRA_CMD_INFO,
TEGRA_CMD_PORT,
TEGRA_CMD_OUTPUT,
TEGRA_CMD_INPUT,
};
static struct gpio_names {

12
drivers/i2c/tegra_i2c.c
View file

@ -262,7 +262,7 @@ exit:
return error;
}
static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len)
{
int error;
struct i2c_trans_info trans_info;
@ -275,12 +275,12 @@ static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
if (error)
debug("tegra20_i2c_write_data: Error (%d) !!!\n", error);
debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
return error;
}
static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len)
{
int error;
struct i2c_trans_info trans_info;
@ -293,7 +293,7 @@ static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
if (error)
debug("tegra20_i2c_read_data: Error (%d) !!!\n", error);
debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
return error;
}
@ -438,7 +438,7 @@ int i2c_write_data(uchar chip, uchar *buffer, int len)
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
rc = tegra20_i2c_write_data(chip << 1, buffer, len);
rc = tegra_i2c_write_data(chip << 1, buffer, len);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
@ -452,7 +452,7 @@ int i2c_read_data(uchar chip, uchar *buffer, int len)
debug("inside i2c_read_data():\n");
/* Shift 7-bit address over for lower-level i2c functions */
rc = tegra20_i2c_read_data(chip << 1, buffer, len);
rc = tegra_i2c_read_data(chip << 1, buffer, len);
if (rc) {
debug("i2c_read_data(): rc=%d\n", rc);
return rc;

2
drivers/input/Makefile
View file

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libinput.o
COBJS-$(CONFIG_I8042_KBD) += i8042.o
COBJS-$(CONFIG_TEGRA20_KEYBOARD) += tegra-kbc.o
COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
ifdef CONFIG_PS2KBD
COBJS-y += keyboard.o pc_keyb.o
COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o

34
drivers/mmc/tegra_mmc.c
View file

@ -25,7 +25,7 @@
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include "tegra_mmc.h"
#include <asm/arch/tegra_mmc.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
@ -39,31 +39,31 @@ struct mmc_host mmc_host[4];
* @param host Structure to fill in (base, reg, mmc_id)
* @param dev_index Device index (0-3)
*/
static void tegra20_get_setup(struct mmc_host *host, int dev_index)
static void tegra_get_setup(struct mmc_host *host, int dev_index)
{
debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index);
debug("tegra_get_setup: dev_index = %d\n", dev_index);
switch (dev_index) {
case 1:
host->base = TEGRA20_SDMMC3_BASE;
host->base = TEGRA_SDMMC3_BASE;
host->mmc_id = PERIPH_ID_SDMMC3;
break;
case 2:
host->base = TEGRA20_SDMMC2_BASE;
host->base = TEGRA_SDMMC2_BASE;
host->mmc_id = PERIPH_ID_SDMMC2;
break;
case 3:
host->base = TEGRA20_SDMMC1_BASE;
host->base = TEGRA_SDMMC1_BASE;
host->mmc_id = PERIPH_ID_SDMMC1;
break;
case 0:
default:
host->base = TEGRA20_SDMMC4_BASE;
host->base = TEGRA_SDMMC4_BASE;
host->mmc_id = PERIPH_ID_SDMMC4;
break;
}
host->reg = (struct tegra20_mmc *)host->base;
host->reg = (struct tegra_mmc *)host->base;
}
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
@ -345,7 +345,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
debug(" mmc_change_clock called\n");
/*
* Change Tegra20 SDMMCx clock divisor here. Source is 216MHz,
* Change Tegra SDMMCx clock divisor here. Source is 216MHz,
* PLLP_OUT0
*/
if (clock == 0)
@ -494,11 +494,11 @@ static int mmc_core_init(struct mmc *mmc)
return 0;
}
int tegra20_mmc_getcd(struct mmc *mmc)
int tegra_mmc_getcd(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
debug("tegra20_mmc_getcd called\n");
debug("tegra_mmc_getcd called\n");
if (host->cd_gpio >= 0)
return !gpio_get_value(host->cd_gpio);
@ -506,13 +506,13 @@ int tegra20_mmc_getcd(struct mmc *mmc)
return 1;
}
int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
{
struct mmc_host *host;
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
struct mmc *mmc;
debug(" tegra20_mmc_init: index %d, bus width %d "
debug(" tegra_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, bus_width, pwr_gpio, cd_gpio);
@ -521,7 +521,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
host->clock = 0;
host->pwr_gpio = pwr_gpio;
host->cd_gpio = cd_gpio;
tegra20_get_setup(host, dev_index);
tegra_get_setup(host, dev_index);
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
@ -539,12 +539,12 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
mmc = &mmc_dev[dev_index];
sprintf(mmc->name, "Tegra20 SD/MMC");
sprintf(mmc->name, "Tegra SD/MMC");
mmc->priv = host;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->getcd = tegra20_mmc_getcd;
mmc->getcd = tegra_mmc_getcd;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
@ -559,7 +559,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
* Both of these are the closest equivalents w/216MHz source
* clock and Tegra20 SDMMC divisors.
* clock and Tegra SDMMC divisors.
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;

6
drivers/spi/tegra_spi.c
View file

@ -72,9 +72,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
return NULL;
}
if (max_hz > TEGRA20_SPI_MAX_FREQ) {
if (max_hz > TEGRA_SPI_MAX_FREQ) {
printf("SPI error: unsupported frequency %d Hz. Max frequency"
" is %d Hz\n", max_hz, TEGRA20_SPI_MAX_FREQ);
" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
return NULL;
}
@ -86,7 +86,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
spi->slave.bus = bus;
spi->slave.cs = cs;
spi->freq = max_hz;
spi->regs = (struct spi_tegra *)TEGRA20_SPI_BASE;
spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
spi->mode = mode;
return &spi->slave;

10
include/configs/harmony.h
View file

@ -34,15 +34,15 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Harmony) # "
#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Harmony"
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTD
#define CONFIG_TEGRA_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#ifdef CONFIG_TEGRA20_ENABLE_UARTA
#ifdef CONFIG_TEGRA_ENABLE_UARTA
/* UARTA: debug board UART */
#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
#endif
@ -66,7 +66,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE
#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
/* Environment in NAND (which is 512M), aligned to start of last sector */
#define CONFIG_ENV_IS_IN_NAND
@ -87,6 +87,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

6
include/configs/medcom.h
View file

@ -35,11 +35,11 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Medcom) # "
#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Medcom"
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
@ -78,6 +78,6 @@
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

6
include/configs/paz00.h
View file

@ -27,11 +27,11 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Paz00) MOD # "
#define CONFIG_TEGRA20_BOARD_STRING "Compal Paz00"
#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTA
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
@ -69,6 +69,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

6
include/configs/plutux.h
View file

@ -35,11 +35,11 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Plutux) # "
#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Plutux"
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
@ -78,6 +78,6 @@
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

20
include/configs/seaboard.h
View file

@ -27,7 +27,7 @@
#include <asm/sizes.h>
/* LP0 suspend / resume */
#define CONFIG_TEGRA20_LP0
#define CONFIG_TEGRA_LP0
#define CONFIG_AES
#define CONFIG_TEGRA_PMU
#define CONFIG_TPS6586X_POWER
@ -42,11 +42,11 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (SeaBoard) # "
#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Seaboard"
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTD
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
@ -96,15 +96,15 @@
#define CONFIG_CMD_DHCP
/* Enable keyboard */
#define CONFIG_TEGRA20_KEYBOARD
#define CONFIG_TEGRA_KEYBOARD
#define CONFIG_KEYBOARD
#undef TEGRA20_DEVICE_SETTINGS
#define TEGRA20_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
"stdout=serial\0" \
"stderr=serial\0"
#undef TEGRA_DEVICE_SETTINGS
#define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
"stdout=serial\0" \
"stderr=serial\0"
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
/* NAND support */
#define CONFIG_CMD_NAND
@ -114,5 +114,5 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Somewhat oddly, the NAND base address must be a config option */
#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE
#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
#endif /* __CONFIG_H */

8
include/configs/tec.h
View file

@ -35,12 +35,12 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TEC) # "
#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
@ -55,7 +55,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE
#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_IS_IN_NAND
@ -87,6 +87,6 @@
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

12
include/configs/tegra20-common-post.h → include/configs/tegra-common-post.h
View file

@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
#ifndef __TEGRA20_COMMON_POST_H
#define __TEGRA20_COMMON_POST_H
#ifndef __TEGRA_COMMON_POST_H
#define __TEGRA_COMMON_POST_H
#ifdef CONFIG_BOOTCOMMAND
@ -141,7 +141,7 @@
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA20_DEVICE_SETTINGS \
TEGRA_DEVICE_SETTINGS \
"fdt_load=0x01000000\0" \
"fdt_high=01100000\0" \
BOOTCMDS_COMMON
@ -174,8 +174,8 @@
#ifdef CONFIG_GENERIC_MMC
#undef CONFIG_GENERIC_MMC
#endif
#ifdef CONFIG_TEGRA20_MMC
#undef CONFIG_TEGRA20_MMC
#ifdef CONFIG_TEGRA_MMC
#undef CONFIG_TEGRA_MMC
#endif
#ifdef CONFIG_CMD_MMC
#undef CONFIG_CMD_MMC
@ -211,4 +211,4 @@
#endif /* CONFIG_SPL_BUILD */
#endif /* __TEGRA20_COMMON_POST_H */
#endif /* __TEGRA_COMMON_POST_H */

12
include/configs/tegra20-common.h
View file

@ -54,7 +54,7 @@
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
#ifdef CONFIG_TEGRA20_LP0
#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
@ -132,9 +132,9 @@
/* Environment information, boards can override if required */
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
@ -157,7 +157,7 @@
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
@ -169,7 +169,7 @@
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_TEXT_BASE 0x0010c000

8
include/configs/trimslice.h
View file

@ -34,12 +34,12 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TrimSlice) # "
#define CONFIG_TEGRA20_BOARD_STRING "Compulab Trimslice"
#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTA
#define CONFIG_TEGRA20_UARTA_GPU
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
@ -94,6 +94,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

6
include/configs/ventana.h
View file

@ -34,11 +34,11 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Ventana) # "
#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Ventana"
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTD
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
@ -76,6 +76,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

8
include/configs/whistler.h
View file

@ -34,12 +34,12 @@
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Whistler) # "
#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Whistler"
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA20_ENABLE_UARTA
#define CONFIG_TEGRA20_UARTA_UAA_UAB
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
@ -90,6 +90,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra20-common-post.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */