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arm, arm-kirkwood: disable l2c before linux boot

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The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Michael Walle 2012-02-06 22:42:10 +05:30 committed by Albert ARIBAUD
parent 81a6c009fe
commit 679530278d
4 changed files with 46 additions and 0 deletions
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9
arch/arm/cpu/arm926ejs/cache.c
View file

@ -68,3 +68,12 @@ void flush_cache(unsigned long start, unsigned long size)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
/*
* Stub implementations for l2 cache operations
*/
void __l2_cache_disable(void)
{
}
void l2_cache_disable(void)
__attribute__((weak, alias("__l2_cache_disable")));

2
arch/arm/cpu/arm926ejs/cpu.c
View file

@ -50,6 +50,8 @@ int cleanup_before_linux (void)
/* turn off I/D-cache */
icache_disable();
dcache_disable();
l2_cache_disable();
/* flush I/D-cache */
cache_flush();

1
arch/arm/cpu/arm926ejs/kirkwood/Makefile
View file

@ -30,6 +30,7 @@ COBJS-y = cpu.o
COBJS-y += dram.o
COBJS-y += mpp.o
COBJS-y += timer.o
COBJS-y += cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))

34
arch/arm/cpu/arm926ejs/kirkwood/cache.c Normal file
View file

@ -0,0 +1,34 @@
/*
* Copyright (c) 2012 Michael Walle
* Michael Walle <michael@walle.cc>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <common.h>
#include <asm/arch/cpu.h>
#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
void l2_cache_disable()
{
u32 ctrl;
ctrl = readfr_extra_feature_reg();
ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
writefr_extra_feature_reg(ctrl);
}