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powerpc/85xx: always implement the work-around for Erratum SATA_A001

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On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default.  So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi 2011-11-21 17:10:23 -06:00 committed by Kumar Gala
parent 3e0529f742
commit fbc20aab11
3 changed files with 34 additions and 25 deletions
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37
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -37,12 +37,15 @@
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <linux/compiler.h>
#include "mp.h"
#ifdef CONFIG_SYS_QE_FW_IN_NAND
#include <nand.h>
#include <errno.h>
#endif
#include "../../../../drivers/block/fsl_sata.h"
DECLARE_GLOBAL_DATA_PTR;
extern void srio_init(void);
@ -301,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
*/
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
@ -316,10 +320,9 @@ int cpu_init_r(void)
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
uint ver;
u32 l2siz_field;
svr = get_svr();
ver = SVR_SOC_VER(svr);
asm("msync;isync");
@ -401,8 +404,8 @@ int cpu_init_r(void)
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
(SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
if ((SVR_SOC_VER(svr) == SVR_P2040) ||
(SVR_SOC_VER(svr) == SVR_P2040_E)) {
puts("N/A\n");
goto skip_l2;
}
@ -488,6 +491,32 @@ skip_l2:
fman_enet_init();
#endif
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
* expected enterprise mode. Software needs to clear bit[28]
* of HControl register to change to enterprise mode from
* legacy mode. We assume that the controller is offline.
*/
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
(SVR_SOC_VER(svr) == SVR_P1022_E) ||
(SVR_SOC_VER(svr) == SVR_P1013) ||
(SVR_SOC_VER(svr) == SVR_P1013_E))) {
fsl_sata_reg_t *reg;
/* first SATA controller */
reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
/* second SATA controller */
reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
}
#endif
return 0;
}

21
drivers/block/fsl_sata.c
View file

@ -197,27 +197,6 @@ int init_sata(int dev)
/* Wait the controller offline */
ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
* expected enterprise mode. software needs to clear bit[28]
* of HControl register to change to enterprise mode from
* legacy mode.
*/
{
u32 svr = get_svr();
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
(SVR_SOC_VER(svr) == SVR_P1022_E) ||
(SVR_SOC_VER(svr) == SVR_P1013) ||
(SVR_SOC_VER(svr) == SVR_P1013_E))) {
out_le32(&reg->hstatus, 0x20000000);
out_le32(&reg->hcontrol, 0x00000100);
}
}
#endif
/* Set the command header base address to CHBA register to tell DMA */
out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);

1
drivers/block/fsl_sata.h
View file

@ -103,6 +103,7 @@ typedef struct fsl_sata_reg {
*/
#define HCONTROL_ONOFF 0x80000000 /* Online or offline request */
#define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */
#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */
#define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */
#define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */