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omap3: mem: Move comments next to definitions
Calculations for ACTIM_CTRLA amd ACTIM_CTRLB values are defined in 'header' style comments. Moved them along with definitions. Should help maintain consistency between comments and code if any of these are tweaked in future. Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sanjeev Premi
Sandeep Paulraj
parent
f883c5d8fa
commit
2c5b87561a
1 changed files with 35 additions and 76 deletions
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@ -86,28 +86,16 @@ enum {
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ACTIM_CTRLB_TXP(b) | \
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ACTIM_CTRLB_TXSR(d)
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 18/6 = 3
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 72/6 = 12
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* ACTIMB
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* TCKE = 2
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* XSR = 120/6 = 20
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*/
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#define INFINEON_TDAL_165 6
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#define INFINEON_TDPL_165 3
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#define INFINEON_TRRD_165 2
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#define INFINEON_TRCD_165 3
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#define INFINEON_TRP_165 3
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#define INFINEON_TRAS_165 7
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#define INFINEON_TRC_165 10
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#define INFINEON_TRFC_165 12
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
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#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
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#define INFINEON_TRRD_165 2 /* 12/6 = 2 */
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#define INFINEON_TRCD_165 3 /* 18/6 = 3 */
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#define INFINEON_TRP_165 3 /* 18/6 = 3 */
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#define INFINEON_TRAS_165 7 /* 42/6 = 7 */
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#define INFINEON_TRC_165 10 /* 60/6 = 10 */
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#define INFINEON_TRFC_165 12 /* 72/6 = 12 */
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#define INFINEON_V_ACTIMA_165 \
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ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
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@ -118,36 +106,22 @@ enum {
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#define INFINEON_TWTR_165 1
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#define INFINEON_TCKE_165 2
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#define INFINEON_TXP_165 2
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#define INFINEON_XSR_165 20
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#define INFINEON_XSR_165 20 /* 120/6 = 20 */
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#define INFINEON_V_ACTIMB_165 \
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ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
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INFINEON_TXP_165, INFINEON_XSR_165)
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/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 18/6 = 3
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 125/6 = 21
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* ACTIMB
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* TWTR = 1
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* TCKE = 1
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* TXSR = 138/6 = 23
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* TXP = 25/6 = 4.1 ~5
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*/
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#define MICRON_TDAL_165 6
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#define MICRON_TDPL_165 3
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#define MICRON_TRRD_165 2
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#define MICRON_TRCD_165 3
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#define MICRON_TRP_165 3
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#define MICRON_TRAS_165 7
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#define MICRON_TRC_165 10
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#define MICRON_TRFC_165 21
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/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
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#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
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#define MICRON_TRRD_165 2 /* 12/6 = 2 */
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#define MICRON_TRCD_165 3 /* 18/6 = 3 */
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#define MICRON_TRP_165 3 /* 18/6 = 3 */
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#define MICRON_TRAS_165 7 /* 42/6 = 7 */
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#define MICRON_TRC_165 10 /* 60/6 = 10 */
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#define MICRON_TRFC_165 21 /* 125/6 = 21 */
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#define MICRON_V_ACTIMA_165 \
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ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
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@ -157,8 +131,8 @@ enum {
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#define MICRON_TWTR_165 1
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#define MICRON_TCKE_165 1
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#define MICRON_XSR_165 23
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#define MICRON_TXP_165 5
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#define MICRON_XSR_165 23 /* 138/6 = 23 */
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#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
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#define MICRON_V_ACTIMB_165 \
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ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
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@ -191,31 +165,16 @@ enum {
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#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
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(MICRON_SIL << 3) | (MICRON_BL))
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/*
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* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 22.5/6 = 3.75 -> 4
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 140/6 = 23.3 -> 24
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* ACTIMB
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* TWTR = 2
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* TCKE = 2
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* TXSR = 200/6 = 33.3 -> 34
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* TXP = 1.0 + 1.1 = 2.1 -> 3
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*/
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#define NUMONYX_TDAL_165 6
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#define NUMONYX_TDPL_165 3
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#define NUMONYX_TRRD_165 2
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#define NUMONYX_TRCD_165 4
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#define NUMONYX_TRP_165 3
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#define NUMONYX_TRAS_165 7
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#define NUMONYX_TRC_165 10
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#define NUMONYX_TRFC_165 24
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/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
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#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
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#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
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#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
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#define NUMONYX_TRP_165 3 /* 18/6 = 3 */
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#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
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#define NUMONYX_TRC_165 10 /* 60/6 = 10 */
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#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
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#define NUMONYX_V_ACTIMA_165 \
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ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
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@ -225,8 +184,8 @@ enum {
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#define NUMONYX_TWTR_165 2
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#define NUMONYX_TCKE_165 2
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#define NUMONYX_TXP_165 3
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#define NUMONYX_XSR_165 34
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#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
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#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
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#define NUMONYX_V_ACTIMB_165 \
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ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
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