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mx51: Fix USB PHY clocks

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The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
This commit is contained in:
Benoît Thébaudeau 2012-09-28 07:09:03 +00:00 committed by Tom Rini
parent 248cdf0b52
commit 414e1660c8
3 changed files with 22 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -126,11 +126,26 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
}
#endif
void set_usb_phy1_clk(void)
void set_usb_phy_clk(void)
{
clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
}
#if defined(CONFIG_MX51)
void enable_usb_phy1_clk(unsigned char enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
clrsetbits_le32(&mxc_ccm->CCGR2,
MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
MXC_CCM_CCGR2_USB_PHY(cg));
}
void enable_usb_phy2_clk(unsigned char enable)
{
/* i.MX51 has a single USB PHY clock, so do nothing here. */
}
#elif defined(CONFIG_MX53)
void enable_usb_phy1_clk(unsigned char enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
@ -140,11 +155,6 @@ void enable_usb_phy1_clk(unsigned char enable)
MXC_CCM_CCGR4_USB_PHY1(cg));
}
void set_usb_phy2_clk(void)
{
clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
}
void enable_usb_phy2_clk(unsigned char enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
@ -153,6 +163,7 @@ void enable_usb_phy2_clk(unsigned char enable)
MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
MXC_CCM_CCGR4_USB_PHY2(cg));
}
#endif
/*
* Calculate the frequency of PLLn.
@ -804,7 +815,7 @@ void mxc_set_sata_internal_clock(void)
u32 *tmp_base =
(u32 *)(IIM_BASE_ADDR + 0x180c);
set_usb_phy1_clk();
set_usb_phy_clk();
clrsetbits_le32(tmp_base, 0x6, 0x4);
}

3
arch/arm/include/asm/arch-mx5/clock.h
View file

@ -57,7 +57,8 @@ u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
void set_usb_phy2_clk(void);
void set_usb_phy_clk(void);
void enable_usb_phy1_clk(unsigned char enable);
void enable_usb_phy2_clk(unsigned char enable);
void set_usboh3_clk(void);
void enable_usboh3_clk(unsigned char enable);

3
drivers/usb/host/ehci-mx5.c
View file

@ -220,7 +220,8 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
set_usboh3_clk();
enable_usboh3_clk(1);
set_usb_phy2_clk();
set_usb_phy_clk();
enable_usb_phy1_clk(1);
enable_usb_phy2_clk(1);
mdelay(1);