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https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
mxc_spi: move machine specifics into CPU headers
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
Introduce two new macros to control conditional setup
MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
This commit is contained in:
Eric Nelson
Albert ARIBAUD
parent
4b3a30e9ae
commit
08c61a589b
4 changed files with 90 additions and 89 deletions
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@ -901,4 +901,31 @@ struct esdc_regs {
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#define MXC_EHCI_IPPUE_DOWN (1 << 8)
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#define MXC_EHCI_IPPUE_UP (1 << 9)
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 8)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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0x43fa4000, \
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0x50010000, \
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0x53f84000,
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#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
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@ -179,6 +179,31 @@
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#define IPU_CONF_IC_EN (1<<1)
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#define IPU_CONF_SCI_EN (1<<0)
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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0x43fa4000, \
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0x50010000,
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#define GPIO_PORT_NUM 3
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#define GPIO_NUM_PIN 32
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@ -222,6 +222,36 @@
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#define CS0_64M_CS1_32M_CS2_32M 2
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#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
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/*
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* CSPI register definitions
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*/
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#define MXC_ECSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_POL 4
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#define MXC_CSPICON_PHA 0
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#define MXC_CSPICON_SSPOL 12
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#define MXC_SPI_BASE_ADDRESSES \
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CSPI1_BASE_ADDR, \
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CSPI2_BASE_ADDR, \
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CSPI3_BASE_ADDR,
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/*
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* Number of GPIO pins per port
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*/
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@ -33,93 +33,12 @@
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#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
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"See linux mxc_spi driver from Freescale for details."
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#elif defined(CONFIG_MX31)
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 8)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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static unsigned long spi_bases[] = {
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0x43fa4000,
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0x50010000,
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0x53f84000,
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};
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#elif defined(CONFIG_MX51)
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_POL 4
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#define MXC_CSPICON_PHA 0
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#define MXC_CSPICON_SSPOL 12
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static unsigned long spi_bases[] = {
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CSPI1_BASE_ADDR,
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CSPI2_BASE_ADDR,
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CSPI3_BASE_ADDR,
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};
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#elif defined(CONFIG_MX35)
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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static unsigned long spi_bases[] = {
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0x43fa4000,
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0x50010000,
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};
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#else
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#error "Unsupported architecture"
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#endif
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static unsigned long spi_bases[] = {
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MXC_SPI_BASE_ADDRESSES
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};
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#define OUT MXC_GPIO_DIRECTION_OUT
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#define reg_read readl
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@ -129,7 +48,7 @@ struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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u32 ctrl_reg;
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#if defined(CONFIG_MX51)
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#if defined(MXC_ECSPI)
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u32 cfg_reg;
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#endif
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int gpio;
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@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div)
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return i;
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}
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#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
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#ifdef MXC_CSPI
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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}
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#endif
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#if defined(CONFIG_MX51)
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#ifdef MXC_ECSPI
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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#ifdef CONFIG_MX51
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#ifdef MXC_ECSPI
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reg_write(®s->cfg, mxcs->cfg_reg);
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#endif
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