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imx: iomux-v3: Fix common pad control definitions
Commit dc88403
"iomux-v3: Place pad control definitions into common file" broke
mx51_efikamx because it made i.MX6's pad control definitions conflict with
i.MX51's.
i.MX51's pad control definitions are actually common to some other i.MX
(25/35/53), so move them to the common iomux-v3.h (just like what is done in
Linux's), and select the correct definitions depending on whether CONFIG_MX6 is
defined or not.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
parent
eec3f0242d
commit
d73b97604b
2 changed files with 28 additions and 23 deletions
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@ -21,27 +21,6 @@
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#include <asm/imx-common/iomux-v3.h>
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#define PAD_CTL_DVS (1 << 13)
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#define PAD_CTL_INPUT_DDR (1 << 9)
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#define PAD_CTL_HYS (1 << 8)
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#define PAD_CTL_PKE (1 << 7)
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#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
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#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_ODE (1 << 3)
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#define PAD_CTL_DSE_LOW (0 << 1)
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#define PAD_CTL_DSE_MED (1 << 1)
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#define PAD_CTL_DSE_HIGH (2 << 1)
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#define PAD_CTL_DSE_MAX (3 << 1)
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#define PAD_CTL_SRE_FAST (1 << 0)
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#define PAD_CTL_SRE_SLOW (0 << 0)
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/* Pad control groupings */
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#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
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PAD_CTL_HYS | PAD_CTL_SRE_FAST)
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@ -61,8 +40,6 @@
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PAD_CTL_SRE_FAST | PAD_CTL_DVS)
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#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
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#define __NA_ 0x000
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/*
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* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
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* If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
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@ -23,6 +23,8 @@
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#ifndef __MACH_IOMUX_V3_H__
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#define __MACH_IOMUX_V3_H__
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#include <common.h>
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/*
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* build IOMUX_PAD structure
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*
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@ -95,6 +97,8 @@ typedef u64 iomux_v3_cfg_t;
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#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
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#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
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#ifdef CONFIG_MX6
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#define PAD_CTL_HYS (1 << 16)
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#define PAD_CTL_PUS_100K_DOWN (0 << 14)
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#define PAD_CTL_PUS_47K_UP (1 << 14)
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@ -115,10 +119,34 @@ typedef u64 iomux_v3_cfg_t;
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#define PAD_CTL_DSE_48ohm (5 << 3)
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#define PAD_CTL_DSE_40ohm (6 << 3)
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#define PAD_CTL_DSE_34ohm (7 << 3)
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#else
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#define PAD_CTL_DVS (1 << 13)
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#define PAD_CTL_INPUT_DDR (1 << 9)
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#define PAD_CTL_HYS (1 << 8)
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#define PAD_CTL_PKE (1 << 7)
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#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
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#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
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#define PAD_CTL_ODE (1 << 3)
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#define PAD_CTL_DSE_LOW (0 << 1)
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#define PAD_CTL_DSE_MED (1 << 1)
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#define PAD_CTL_DSE_HIGH (2 << 1)
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#define PAD_CTL_DSE_MAX (3 << 1)
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#endif
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#define PAD_CTL_SRE_FAST (1 << 0)
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#define PAD_CTL_SRE_SLOW (0 << 0)
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#define IOMUX_CONFIG_SION 0x10
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#define __NA_ 0x000
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#define NO_MUX_I 0
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#define NO_PAD_I 0
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