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Merge branch 'master' of git://git.denx.de/u-boot-arm

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* 'master' of git://git.denx.de/u-boot-arm: (145 commits)
  beagleboard: enable HUB power on all variants of the BeagleBoard
  dm3730: enable dpll5
  ehci-hcd: Allow cleanups to happen gracefully on a timeout.
  OMAP3: Add DSS driver for OMAP3
  led: Remove state-saving of led for toggle functionality and add toggle option to led command
  led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all'
  led: correct off/on locations in structure
  led: added cmd_led to Makefile
  BeagleBoard: fix LED 0/1 in driver
  Corrected LED name match finding avoiding extraneous Usage printouts
  BeagleBoard: config: updated default configuration
  BeagleBoard: config: Enabled multibus support for I2C in configuration
  BeagleBoard: config: add optargs/buddy/camera
  BeagleBoard: config: increase command-line functionality
  BeagleBoard: config: make mtest run
  BeagleBoard: config: enable DSS
  BeagleBoard: config: enable asix driver and dhcp
  BeagleBoard: config: enable networking
  BeagleBoard: config: decrease bootdelay to 2 seconds
  BeagleBoard: config: use uImage.beagle for tftp
  BeagleBoard: config: hardcode MAC for onboard SMSC
  BeagleBoard: config: load kernel from MMC ext, not FAT
  BeagleBoard: Configure DVI/S-video
  BeagleBoard: Added userbutton command
  BeagleBoard: turn off clocks in ehci_stop
  USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor
  beagleboard: add support for xM revision C
  beagle: pass expansionboard name in bootargs
  OMAP: Remove omapfb.debug=y from Beagle and Overo env settings
  OMAP3 Beagle Pin Mux initialization glitch fix
  da850: modifications for Logic PD Rev.3 AM18xx EVM
  da850: fix the channel number for EMAC teardown init
  da850: add support for Spectrum Digital AM18xx EVM
  da850: add support to wake up DSP during board init
  da850: modify the U-Boot prompt string
  da850: add NOR boot mode support
  da8xx: add support for multiple PLL controllers
  da850: indicate cache usage disable in config file
  dm365: modify boot prompt from dm365 to dm36x
  dm365: disable cache usage due to coherency issues
  dm6446: disable cache usage due to coherency issues
  OMAP3: Remove legacy mmc driver
  devkit8000: Use generic MMC driver
  TI OMAP3 SDP3430: Use generic MMC driver
  AM3517 CraneBoard: Use generic MMC driver
  OMAP3: pandora: Use generic MMC driver
  OMAP3: Zoom2: Use generic MMC driver
  OMAP3: Zoom1: Use generic MMC driver
  OMAP3: DIG297: Use generic MMC driver
  OMAP3: CM-T35: Use generic MMC driver
  am3517evm: Use generic MMC driver
  omap3evm: Use generic MMC driver
  omap3:clock: check cpu_family before enabling clks for IVA & CAM
  omap3:clock: configure GFX clock to 200MHz for AM/DM37x
  OMAP3/4: Increase console I/O buffer size
  PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE
  PXA: Fix CSB226, fix monitor length
  PXA: Fix Lubbock, remove redundant parenthesis
  armv7: cache: remove flush on un-aligned invalidate
  armv7: stronger barrier for cache-maintenance operations
  omap: enable caches at system start-up
  arm: do not force d-cache enable on all boards
  ORIGEN: Add MMC SPL support
  ARMV7: Add support for Samsung ORIGEN board
  i2c:gpio:s5p: Enable I2C GPIO on the GONI target
  i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
  Tegra2: Use clock and pinmux functions to simplify code
  Tegra2: Add additional pin multiplexing features
  Tegra2: Add more clock support
  Tegra2: Add microsecond timer function
  ARM: remove broken "at91rm9200dk" board
  ARM: remove broken "m501sk" board
  ARM: remove broken "kb9202" board
  ARM: remove broken "csb637" board
  ARM: remove broken "cmc_pu2" board
  ARM: remove broken "at91cap9adk" board
  ARM: remove broken "voiceblue" board
  ARM: remove broken "smdk2400" board
  ARM: remove broken "sbc2410x" board
  ARM: remove broken "netstar" board
  ARM: remove broken "mx1fs2" board
  ARM: remove broken "lpd7a40x" boards
  ARM: remove broken "edb93xx" boards
  ARM: remove broken "B2" board
  ARM: remove broken "armadillo" board
  ARM: remove broken "assabet" board
  ARM: versatile: drop warnings
  IMX: scb9328: drop warnings
  MX31: imx31_litekit: make use of GPIO framework
  MX31: mx31ads: make use of GPIO framework
  MX5: mx51evk: make use of GPIO framework
  MX35: mx35pdk: make use of GPIO framework
  MX5: mx53loco: make use of GPIO framework
  MX5: mx53evk: make use of GPIO framework
  MX5: vision2: make use of GPIO framework
  MX5: mx53smd: make use of GPIO framework
  MX5: mx53ard: make use of GPIO framework
  MX25: zmx25: make use of GPIO framework
  MX5: efikamx: make use of GPIO framework
  MX31: QONG: make use of GPIO framework
  MX35: make use of GPIO framework for MX35 processor
  MX5: make use of GPIO framework for MX5 processor
  MX31: make use of GPIO framework for MX31 processor
  MX25: make use of GPIO framework for MX25 processor
  IMX: uniform GPIO interface using GPIO framework
  MX: MX35 / MX5: uniform clock command with powerpc
  MX35: MX35PDK: support additional RAM on CSD1
  mx53: ddr3: Update DD3 initialization
  ARM: MX51: PLL errata workaround
  ARM: versatilepb : drop warnings due to double definitions
  omap4: increase SRAM budget to fix build error
  omap4: fix build warning due to signed unsigned comparison
  mkimage: Fix 'Unknown OMAP image type - 5'
  omap: fix gpio related build breaks
  gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal)
  SMDKV310: MMC SPL: Remove unwanted dummy functions
  SMDKV310: Fix undefined reference error
  SMDKV310: Fix build error for smdkv310 board
  gpio:samsung s5p_ suffix add for GPIO functions
  mmc: S5P: Support DMA restarts at buffer boundaries
  SMDKV310: Fix host compilation of mkv310_image
  arm: fix bd pointer dereference prior initialization
  arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize
  mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
  MX31: removed warnings due to clock.h
  integrator: convert to new build system
  integratorcp: make the board compile
  integratorap: remove hardcoded 32MB memory cmdline
  ...
This commit is contained in:
Wolfgang Denk 2011-09-04 21:12:18 +02:00
commit 6dfbf49c6d
275 changed files with 5025 additions and 16972 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
MAINTAINERS
View file

@ -564,10 +564,6 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
Rowel Atienza <rowel@diwalabs.com>
armadillo ARM720T
Stefano Babic <sbabic@denx.de>
ea20 davinci
@ -632,7 +628,6 @@ Eric Cooper <ecc@cmu.edu>
George G. Davis <gdavis@mvista.com>
assabet SA1100
gcplus SA1100
Wolfgang Denk <wd@denx.de>
@ -690,10 +685,6 @@ Grazvydas Ignotas <notasas@gmail.com>
omap3_pandora ARM ARMV7 (OMAP3xx SoC)
Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
@ -716,6 +707,7 @@ Minkyu Kang <mk7.kang@samsung.com>
Chander Kashyap <k.chander@samsung.com>
origen ARM ARMV7 (S5PC210 SoC)
SMDKV310 ARM ARMV7 (S5PC210 SoC)
Torsten Koschorrek <koschorrek@synertronixx.de>
@ -797,7 +789,6 @@ Manikandan Pillai <mani.pillai@ti.com>
Stelian Pop <stelian.pop@leadtechdesign.com>
at91cap9adk ARM926EJS (AT91CAP9 SoC)
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
@ -850,10 +841,6 @@ Michael Schwingen <michael@schwingen.org>
actux4 xscale/ixp
dvlhost xscale/ixp
Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)

69
MAKEALL
View file

@ -301,14 +301,9 @@ LIST_SA="$(boards_by_cpu sa1100)"
#########################################################################
LIST_ARM7=" \
ap7 \
ap720t \
armadillo \
B2 \
ep7312 \
evb4510 \
impa7 \
integratorap \
lpc2292sodimm \
modnet50 \
SMN42 \
@ -320,38 +315,17 @@ LIST_ARM7=" \
LIST_ARM9=" \
a320evb \
ap920t \
ap922_XA10 \
ap926ejs \
ap946es \
ap966 \
aspenite \
cp920t \
cp922_XA10 \
cp926ejs \
cp946es \
cp966 \
da830evm \
da850evm \
edb9301 \
edb9302 \
edb9302a \
edb9307 \
edb9307a \
edb9312 \
edb9315 \
edb9315a \
edminiv2 \
guruplug \
imx27lite \
jadecpu \
km_kirkwood \
lpd7a400 \
magnesium \
mv88f6281gtw_ge \
mx1ads \
mx1fs2 \
netstar \
nhk8815 \
nhk8815_onenand \
omap1510inn \
@ -364,10 +338,8 @@ LIST_ARM9=" \
openrd_ultimate \
portl2 \
rd6281a \
sbc2410x \
scb9328 \
sheevaplug \
smdk2400 \
smdk2410 \
spear300 \
spear310 \
@ -377,7 +349,6 @@ LIST_ARM9=" \
versatile \
versatileab \
versatilepb \
voiceblue \
davinci_dvevm \
davinci_schmoogie \
davinci_sffsdr \
@ -388,19 +359,10 @@ LIST_ARM9=" \
davinci_dm6467evm \
"
#########################################################################
## ARM10 Systems
#########################################################################
LIST_ARM10=" \
integratorcp \
cp1026 \
"
#########################################################################
## ARM11 Systems
#########################################################################
LIST_ARM11=" \
cp1136 \
omap2420h4 \
apollon \
imx31_litekit \
@ -417,39 +379,14 @@ LIST_ARM11=" \
#########################################################################
## ARMV7 Systems
#########################################################################
LIST_ARMV7=" \
am3517_crane \
am3517_evm \
ca9x4_ct_vxp \
devkit8000 \
dig297 \
igep0020 \
igep0030 \
mx51evk \
omap3_beagle \
omap3_overo \
omap3_evm \
omap3_pandora \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
omap4_panda \
omap4_sdp4430 \
s5p_goni \
smdkc100 \
"
LIST_ARMV7="$(boards_by_cpu armv7)"
#########################################################################
## AT91 Systems
#########################################################################
LIST_at91="$(boards_by_soc at91)\
at91sam9m10g45ek \
pm9g45 \
SBC35_A9G20 \
TNY_A9260 \
TNY_A9G20 \
"
LIST_at91="$(boards_by_soc at91)"
#########################################################################
## Xscale Systems

84
Makefile
View file

@ -798,78 +798,6 @@ M5485HFE_config : unconfig
# ARM
#========================================================================
#########################################################################
## ARM926EJ-S Systems
#########################################################################
at91sam9m10g45ek_nandflash_config \
at91sam9m10g45ek_dataflash_config \
at91sam9m10g45ek_dataflash_cs0_config \
at91sam9m10g45ek_config \
at91sam9g45ekes_nandflash_config \
at91sam9g45ekes_dataflash_config \
at91sam9g45ekes_dataflash_cs0_config \
at91sam9g45ekes_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring 9m10,$@)" ] ; then \
echo "#define CONFIG_AT91SAM9M10G45EK 1" >>$(obj)include/config.h ; \
else \
echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \
fi;
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
else \
echo "#define CONFIG_ATMEL_SPI 1" >>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
pm9g45_config : unconfig
@mkdir -p $(obj)include
@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
SBC35_A9G20_NANDFLASH_config \
SBC35_A9G20_EEPROM_config \
SBC35_A9G20_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
TNY_A9G20_NANDFLASH_config \
TNY_A9G20_EEPROM_config \
TNY_A9G20_config \
TNY_A9260_NANDFLASH_config \
TNY_A9260_EEPROM_config \
TNY_A9260_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a tny_a9260 arm arm926ejs tny_a9260 calao at91
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
integratorap_config \
ap_config \
ap966_config \
ap922_config \
ap922_XA10_config \
ap7_config \
ap720t_config \
ap920t_config \
ap926ejs_config \
ap946es_config: unconfig
@board/armltd/integrator/split_by_variant.sh ap $@
integratorcp_config \
cp_config \
cp920t_config \
cp926ejs_config \
cp946es_config \
cp1136_config \
cp966_config \
cp922_config \
cp922_XA10_config \
cp1026_config: unconfig
@board/armltd/integrator/split_by_variant.sh cp $@
xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))
omap1610inn_config \
@ -923,16 +851,6 @@ tx25_config : unconfig
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
@$(MKCONFIG) $@ arm arm926ejs tx25 karo mx25
edb9301_config \
edb9302_config \
edb9302a_config \
edb9307_config \
edb9307a_config \
edb9312_config \
edb9315_config \
edb9315a_config: unconfig
@$(MKCONFIG) -n $@ -t $(@:_config=) edb93xx arm arm920t edb93xx - ep93xx
#########################################################################
## XScale Systems
#########################################################################
@ -1014,9 +932,7 @@ clean:
$(obj)tools/ncb $(obj)tools/ubsha1
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/voiceblue/eeprom \
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
$(obj)u-boot.lds \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}

4
arch/arm/cpu/arm1136/mx35/generic.c
View file

@ -417,8 +417,8 @@ int do_mx35_showclocks(cmd_tbl_t *cmdtp,
}
U_BOOT_CMD(
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks\n",
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks",
""
);

5
arch/arm/cpu/arm720t/cpu.c
View file

@ -82,9 +82,4 @@ static void cache_flush (void)
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific cache setup for IntegratorAP/CM720T as yet */
void icache_enable (void)
{
}
#endif

114
arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
View file

@ -26,135 +26,131 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/io.h>
/*
* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
* peripheral pins. Good to have if hardware is soldered optionally
* or in case of SPI no slave is selected. Avoid lines to float
* needlessly. Use a short local PUP define.
*
* Due to errata "TXD floats when CTS is inactive" pullups are always
* on for TXD pins.
*/
#ifdef CONFIG_AT91_GPIO_PULLUP
# define PUP CONFIG_AT91_GPIO_PULLUP
#else
# define PUP 0
#endif
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */
writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */
writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */
writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_serial0_hw_init();
#endif
#ifdef CONFIG_USART1
at91_serial1_hw_init();
#endif
#ifdef CONFIG_USART2
at91_serial2_hw_init();
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_serial3_hw_init();
#endif
}
#ifdef CONFIG_ATMEL_SPI
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
/* Enable clock */
writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
}
}

30
arch/arm/cpu/arm926ejs/davinci/cpu.c
View file

@ -37,6 +37,7 @@
#define PLLC_PLLDIV4 0x160
#define PLLC_PLLDIV5 0x164
#define PLLC_PLLDIV6 0x168
#define PLLC_PLLDIV7 0x16c
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
@ -61,11 +62,9 @@
#endif
#ifdef CONFIG_SOC_DA8XX
const dv_reg * const sysdiv[7] = {
&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
&davinci_pllc_regs->plldiv7
unsigned int sysdiv[9] = {
PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
};
int clk_get(enum davinci_clk_ids id)
@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id)
int pllm;
int post_div;
int pll_out;
unsigned int pll_base;
pll_out = CONFIG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID)
goto out;
if ((id >> 16) == 1)
pll_base = (unsigned int)davinci_pllc1_regs;
else
pll_base = (unsigned int)davinci_pllc0_regs;
id &= 0xFFFF;
/*
* Lets keep this simple. Combining operations can result in
* unexpected approximations
*/
pre_div = (readl(&davinci_pllc_regs->prediv) &
DAVINCI_PLLC_DIV_MASK) + 1;
pllm = readl(&davinci_pllc_regs->pllm) + 1;
pre_div = (readl(pll_base + PLLC_PREDIV) &
DAVINCI_PLLC_DIV_MASK) + 1;
pllm = readl(pll_base + PLLC_PLLM) + 1;
pll_out /= pre_div;
pll_out *= pllm;
@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id)
if (id == DAVINCI_PLLM_CLKID)
goto out;
post_div = (readl(&davinci_pllc_regs->postdiv) &
DAVINCI_PLLC_DIV_MASK) + 1;
post_div = (readl(pll_base + PLLC_POSTDIV) &
DAVINCI_PLLC_DIV_MASK) + 1;
pll_out /= post_div;
if (id == DAVINCI_PLLC_CLKID)
goto out;
pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
pll_out /= (readl(pll_base + sysdiv[id - 1]) &
DAVINCI_PLLC_DIV_MASK) + 1;
out:
return pll_out;

26
arch/arm/cpu/armv7/cache_v7.c
View file

@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
: : "r" (setway));
}
}
/* DMB to make sure the operation is complete */
CP15DMB;
/* DSB to make sure the operation is complete */
CP15DSB;
}
static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
: : "r" (setway));
}
}
/* DMB to make sure the operation is complete */
CP15DMB;
/* DSB to make sure the operation is complete */
CP15DSB;
}
static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
u32 mva;
/*
* If start address is not aligned to cache-line flush the first
* line to prevent affecting somebody else's buffer
* If start address is not aligned to cache-line do not
* invalidate the first cache-line
*/
if (start & (line_len - 1)) {
v7_dcache_clean_inval_range(start, start + 1, line_len);
printf("ERROR: %s - start address is not aligned - 0x%08x\n",
__func__, start);
/* move to next cache line */
start = (start + line_len - 1) & ~(line_len - 1);
}
/*
* If stop address is not aligned to cache-line flush the last
* line to prevent affecting somebody else's buffer
* If stop address is not aligned to cache-line do not
* invalidate the last cache-line
*/
if (stop & (line_len - 1)) {
v7_dcache_clean_inval_range(stop, stop + 1, line_len);
printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
__func__, stop);
/* align to the beginning of this cache line */
stop &= ~(line_len - 1);
}
@ -227,8 +229,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
break;
}
/* DMB to make sure the operation is complete */
CP15DMB;
/* DSB to make sure the operation is complete */
CP15DSB;
}
/* Invalidate TLB */

4
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -288,7 +288,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/***************************************************/
U_BOOT_CMD(
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
"display clocks\n",
clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
"display clocks",
""
);

38
arch/arm/cpu/armv7/mx5/lowlevel_init.S
View file

@ -121,6 +121,35 @@
beq 1b
.endm
.macro setup_pll_errata pll, freq
ldr r2, =\pll
mov r1, #0x0
str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
ldr r1, =0x00001236
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
ands r1, r1, #0x1
beq 1b
ldr r5, \freq
str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
str r5, [r2, #PLL_DP_HFS_MFN]
mov r1, #0x1
str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
2: ldr r1, [r2, #PLL_DP_CONFIG]
tst r1, #1
bne 2b
ldr r1, =100 /* Wait at least 4 us */
3: subs r1, r1, #1
bge 3b
mov r1, #0x2
str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm
.macro init_clock
ldr r0, =CCM_BASE_ADDR
@ -157,7 +186,12 @@
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51_PLL_ERRATA)
setup_pll PLL1_BASE_ADDR, 864
setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
setup_pll PLL1_BASE_ADDR, 800
#endif
#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
@ -287,6 +321,10 @@ lowlevel_init:
mov pc,lr
/* Board level setting value */
W_DP_OP_864: .word DP_OP_864
W_DP_MFD_864: .word DP_MFD_864
W_DP_MFN_864: .word DP_MFN_864
W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_800: .word DP_MFN_800

2
arch/arm/cpu/armv7/omap-common/gpio.c
View file

@ -36,7 +36,7 @@
* published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/omap_gpio.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/errno.h>

10
arch/arm/cpu/armv7/omap3/board.c
View file

@ -38,7 +38,7 @@
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/omap_gpio.h>
#include <asm/arch/gpio.h>
/* Declarations */
extern omap3_sysinfo sysinfo;
@ -402,3 +402,11 @@ void v7_outer_cache_disable(void)
omap3_update_aux_cr(0, 0x2);
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

17
arch/arm/cpu/armv7/omap3/clock.c
View file

@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
/* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
/* GFX */
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
/* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
@ -579,6 +579,7 @@ void prcm_init(void)
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
dpll5_init_34xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
@ -607,7 +608,9 @@ void prcm_init(void)
dpll3_init_34xx(sil_index, clk_index);
dpll4_init_34xx(sil_index, clk_index);
dpll5_init_34xx(sil_index, clk_index);
iva_init_34xx(sil_index, clk_index);
if (get_cpu_family() != CPU_AM35XX)
iva_init_34xx(sil_index, clk_index);
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
@ -674,7 +677,9 @@ void per_clocks_enable(void)
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
if (get_cpu_family() != CPU_AM35XX)
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
@ -682,8 +687,10 @@ void per_clocks_enable(void)
sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
if (get_cpu_family() != CPU_AM35XX) {
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
}
sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);

10
arch/arm/cpu/armv7/omap4/board.c
View file

@ -33,7 +33,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/arch/emif.h>
#include <asm/omap_gpio.h>
#include <asm/arch/gpio.h>
#include "omap4_mux_data.h"
DECLARE_GLOBAL_DATA_PTR;
@ -299,3 +299,11 @@ void v7_outer_cache_disable(void)
set_pl310_ctrl_reg(0);
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

2
arch/arm/cpu/armv7/tegra2/Makefile
View file

@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
COBJS := ap20.o board.o sys_info.o timer.o
COBJS := ap20.o board.o clock.o pinmux.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

91
arch/arm/cpu/armv7/tegra2/ap20.c
View file

@ -25,6 +25,7 @@
#include <asm/io.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/scu.h>
@ -35,33 +36,32 @@ u32 s_first_boot = 1;
void init_pllx(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU];
u32 reg;
/* If PLLX is already enabled, just return */
reg = readl(&clkrst->crc_pllx_base);
if (reg & PLL_ENABLE)
if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
return;
/* Set PLLX_MISC */
reg = CPCON; /* CPCON[11:8] = 0001 */
writel(reg, &clkrst->crc_pllx_misc);
writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
/* Use 12MHz clock here */
reg = (PLL_BYPASS | PLL_DIVM);
reg |= (1000 << 8); /* DIVN = 0x3E8 */
writel(reg, &clkrst->crc_pllx_base);
reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
reg |= 1000 << PLL_DIVN_SHIFT;
writel(reg, &pll->pll_base);
reg |= PLL_ENABLE;
writel(reg, &clkrst->crc_pllx_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
reg &= ~PLL_BYPASS;
writel(reg, &clkrst->crc_pllx_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
}
static void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg, clk;
u32 clk;
/*
* NOTE:
@ -83,27 +83,19 @@ static void enable_cpu_clock(int enable)
writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
}
/* Fetch the register containing the main CPU complex clock enable */
reg = readl(&clkrst->crc_clk_out_enb_l);
reg |= CLK_ENB_CPU;
/*
* Read the register containing the individual CPU clock enables and
* always stop the clock to CPU 1.
*/
clk = readl(&clkrst->crc_clk_cpu_cmplx);
clk |= CPU1_CLK_STP;
if (enable) {
/* Unstop the CPU clock */
clk &= ~CPU0_CLK_STP;
} else {
/* Stop the CPU clock */
clk |= CPU0_CLK_STP;
}
clk |= 1 << CPU1_CLK_STP_SHIFT;
/* Stop/Unstop the CPU clock */
clk &= ~CPU0_CLK_STP_MASK;
clk |= !enable << CPU0_CLK_STP_SHIFT;
writel(clk, &clkrst->crc_clk_cpu_cmplx);
writel(reg, &clkrst->crc_clk_out_enb_l);
clock_enable(PERIPH_ID_CPU);
}
static int is_cpu_powered(void)
@ -178,9 +170,6 @@ static void enable_cpu_power_rail(void)
static void reset_A9_cpu(int reset)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg, cpu;
/*
* NOTE: Regardless of whether the request is to hold the CPU in reset
* or take it out of reset, every processor in the CPU complex
@ -189,48 +178,22 @@ static void reset_A9_cpu(int reset)
* are multiple processors in the CPU complex.
*/
/* Hold CPU 1 in reset */
cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
writel(cpu, &clkrst->crc_cpu_cmplx_set);
/* Hold CPU 1 in reset, and CPU 0 if asked */
reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
reset);
reg = readl(&clkrst->crc_rst_dev_l);
if (reset) {
/* Now place CPU0 into reset */
cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
writel(cpu, &clkrst->crc_cpu_cmplx_set);
/* Enable master CPU reset */
reg |= SWR_CPU_RST;
} else {
/* Take CPU0 out of reset */
cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
writel(cpu, &clkrst->crc_cpu_cmplx_clr);
/* Disable master CPU reset */
reg &= ~SWR_CPU_RST;
}
writel(reg, &clkrst->crc_rst_dev_l);
/* Enable/Disable master CPU reset */
reset_set_enable(PERIPH_ID_CPU, reset);
}
static void clock_enable_coresight(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 rst, clk, src;
u32 rst, src;
rst = readl(&clkrst->crc_rst_dev_u);
clk = readl(&clkrst->crc_clk_out_enb_u);
if (enable) {
rst &= ~SWR_CSITE_RST;
clk |= CLK_ENB_CSITE;
} else {
rst |= SWR_CSITE_RST;
clk &= ~CLK_ENB_CSITE;
}
writel(clk, &clkrst->crc_clk_out_enb_u);
writel(rst, &clkrst->crc_rst_dev_u);
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
if (enable) {
/*

158
arch/arm/cpu/armv7/tegra2/clock.c Normal file
View file

@ -0,0 +1,158 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 Clock control functions */
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/timer.h>
#include <asm/arch/tegra2.h>
#include <common.h>
#ifdef DEBUG
#define assert(x) \
({ if (!(x)) printf("Assertion failure '%s' %s line %d\n", \
#x, __FILE__, __LINE__); })
#else
#define assert(x)
#endif
/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 data;
struct clk_pll *pll;
assert(clock_pll_id_isvalid(clkid));
pll = &clkrst->crc_pll[clkid];
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* This works only because:
* - same fields are always mapped at same offsets, except DCCON
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
*/
data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
writel(data, &pll->pll_misc);
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
if (clkid == CLOCK_PLL_ID_USB)
data |= divp << PLLU_VCO_FREQ_SHIFT;
else
data |= divp << PLL_DIVP_SHIFT;
writel(data, &pll->pll_base);
/* calculate the stable time */
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
}
void clock_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
u32 reg;
/* Enable/disable the clock to this peripheral */
assert(clock_periph_id_isvalid(periph_id));
reg = readl(clk);
if (enable)
reg |= PERIPH_MASK(periph_id);
else
reg &= ~PERIPH_MASK(periph_id);
writel(reg, clk);
}
void clock_enable(enum periph_id clkid)
{
clock_set_enable(clkid, 1);
}
void clock_disable(enum periph_id clkid)
{
clock_set_enable(clkid, 0);
}
void reset_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
u32 reg;
/* Enable/disable reset to the peripheral */
assert(clock_periph_id_isvalid(periph_id));
reg = readl(reset);
if (enable)
reg |= PERIPH_MASK(periph_id);
else
reg &= ~PERIPH_MASK(periph_id);
writel(reg, reset);
}
void reset_periph(enum periph_id periph_id, int us_delay)
{
/* Put peripheral into reset */
reset_set_enable(periph_id, 1);
udelay(us_delay);
/* Remove reset */
reset_set_enable(periph_id, 0);
udelay(us_delay);
}
void reset_cmplx_set_enable(int cpu, int which, int reset)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 mask;
/* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
assert(cpu >= 0 && cpu < 2);
mask = which << cpu;
/* either enable or disable those reset for that CPU */
if (reset)
writel(mask, &clkrst->crc_cpu_cmplx_set);
else
writel(mask, &clkrst->crc_cpu_cmplx_clr);
}

45
board/atmel/at91cap9adk/led.c → arch/arm/cpu/armv7/tegra2/pinmux.c
View file

@ -1,8 +1,5 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
@ -22,22 +19,34 @@
* MA 02111-1307 USA
*/
/* Tegra2 pin multiplexing functions */
#include <asm/io.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/pinmux.h>
#include <common.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
void pinmux_set_tristate(enum pmux_pin pin, int enable)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
u32 reg;
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_output(CONFIG_RED_LED, 0);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
reg = readl(tri);
if (enable)
reg |= TRISTATE_MASK(pin);
else
reg &= ~TRISTATE_MASK(pin);
writel(reg, tri);
}
void pinmux_tristate_enable(enum pmux_pin pin)
{
pinmux_set_tristate(pin, 1);
}
void pinmux_tristate_disable(enum pmux_pin pin)
{
pinmux_set_tristate(pin, 0);
}

18
arch/arm/cpu/armv7/tegra2/timer.c
View file

@ -38,13 +38,12 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/timer.h>
DECLARE_GLOBAL_DATA_PTR;
struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
/* counter runs at 1MHz */
#define TIMER_CLK (1000000)
#define TIMER_CLK 1000000
#define TIMER_LOAD_VAL 0xffffffff
/* timer without interrupts */
@ -57,10 +56,10 @@ ulong get_timer(ulong base)
void __udelay(unsigned long usec)
{
long tmo = usec * (TIMER_CLK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->cntr_1us);
unsigned long now, last = timer_get_us();
while (tmo > 0) {
now = readl(&timer_base->cntr_1us);
now = timer_get_us();
if (last > now) /* count up timer overflow */
tmo -= TIMER_LOAD_VAL - last + now;
else
@ -74,7 +73,7 @@ ulong get_timer_masked(void)
ulong now;
/* current tick value */
now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
if (now >= gd->lastinc) /* normal mode (non roll) */
/* move stamp forward with absolute diff ticks */
@ -103,3 +102,10 @@ ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
unsigned long timer_get_us(void)
{
struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
return readl(&timer_base->cntr_1us);
}

16
arch/arm/include/asm/arch-at91/at91sam9g45.h
View file

@ -128,11 +128,25 @@
#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */
#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */
/*
* External memory
*/
#define ATMEL_BASE_CS0 0x10000000
#define ATMEL_BASE_CS1 0x20000000
#define ATMEL_BASE_CS2 0x30000000
#define ATMEL_BASE_CS3 0x40000000
#define ATMEL_BASE_CS4 0x50000000
#define ATMEL_BASE_CS5 0x60000000
#define ATMEL_BASE_CS6 0x70000000
#define ATMEL_BASE_CS7 0x80000000
/*
* Other misc defines
*/
#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* Cpu Name
*/

194
arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
View file

@ -15,139 +15,81 @@
#ifndef AT91SAM9G45_MATRIX_H
#define AT91SAM9G45_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0)
#ifndef __ASSEMBLY__
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
struct at91_matrix {
u32 mcfg[16];
u32 scfg[16];
u32 pras[16][2];
u32 mrcr; /* 0x100 Master Remap Control */
u32 filler[3];
u32 tcmr;
u32 filler2;
u32 ddrmpr;
u32 filler3[3];
u32 ebicsa;
u32 filler4[47];
u32 wpmr;
u32 wpsr;
};
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
#endif /* __ASSEMBLY__ */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
#define AT91C_VDEC_SEL_OFF (0 << 0)
#define AT91C_VDEC_SEL_ON (1 << 0)
#define AT91_MATRIX_M0PR_SHIFT 0
#define AT91_MATRIX_M1PR_SHIFT 4
#define AT91_MATRIX_M2PR_SHIFT 8
#define AT91_MATRIX_M3PR_SHIFT 12
#define AT91_MATRIX_M4PR_SHIFT 16
#define AT91_MATRIX_M5PR_SHIFT 20
#define AT91_MATRIX_M6PR_SHIFT 24
#define AT91_MATRIX_M7PR_SHIFT 28
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
#define AT91_MATRIX_RCB0 (1 << 0)
#define AT91_MATRIX_RCB1 (1 << 1)
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
#define AT91_MATRIX_WPSR_WPV (1 << 0)
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#endif

12
arch/arm/include/asm/arch-davinci/hardware.h
View file

@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_TIMER1_BASE 0x01c21000
#define DAVINCI_WDOG_BASE 0x01c21000
#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
#define DAVINCI_PSC0_BASE 0x01c10000
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
@ -152,8 +153,16 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
#define DAVINCI_L3CBARAM_BASE 0x80000000
#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
@ -387,7 +396,8 @@ struct davinci_pllc_regs {
dv_reg emucnt1;
};
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
#define ASYNC3 get_async3_src()

42
include/mxc_gpio.h → arch/arm/include/asm/arch-mx25/gpio.h
View file

@ -1,6 +1,6 @@
/*
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -21,37 +21,25 @@
* MA 02111-1307 USA
*/
#ifndef __MXC_GPIO_H
#define __MXC_GPIO_H
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
/* Converts a GPIO port number and the internal bit position
* to the GPIO number
*/
#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
MXC_GPIO_DIRECTION_OUT,
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
#ifdef CONFIG_MXC_GPIO
extern int mxc_gpio_direction(unsigned int gpio,
enum mxc_gpio_direction direction);
extern void mxc_gpio_set(unsigned int gpio, unsigned int value);
extern int mxc_gpio_get(unsigned int gpio);
#else
static inline int mxc_gpio_direction(unsigned int gpio,
enum mxc_gpio_direction direction)
{
return 1;
}
static inline int mxc_gpio_get(unsigned int gpio)
{
return 1;
}
static inline void mxc_gpio_set(unsigned int gpio, unsigned int value)
{
}
#endif
#endif

12
arch/arm/include/asm/arch-mx25/imx-regs.h
View file

@ -84,18 +84,6 @@ struct esdramc_regs {
u32 cdlyl; /* delay line cycle length debug */
};
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
u32 ctrl; /* control */

2
arch/arm/include/asm/arch-mx31/clock.h
View file

@ -32,7 +32,7 @@ enum mxc_clock {
};
unsigned int mxc_get_clock(enum mxc_clock clk);
extern u32 imx_get_uartclk();
extern u32 imx_get_uartclk(void);
extern void mx31_gpio_mux(unsigned long mode);
extern void mx31_set_pad(enum iomux_pins pin, u32 config);

23
board/edb93xx/early_udelay.h → arch/arm/include/asm/arch-mx31/gpio.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -20,15 +21,15 @@
* MA 02111-1307 USA
*/
#include <common.h>
/* delay execution before timers are initialized */
static inline void early_udelay(uint32_t usecs)
{
/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
register uint32_t loops = usecs * (1000 / 20);
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/* GPIO Registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
#endif

7
arch/arm/include/asm/arch-mx31/imx-regs.h
View file

@ -57,13 +57,6 @@ struct clock_control_regs {
u32 pdr2;
};
/* GPIO Registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
struct cspi_regs {
u32 rxdata;
u32 txdata;

37
board/atmel/at91cap9adk/partition.c → arch/arm/include/asm/arch-mx35/gpio.h
View file

@ -1,6 +1,9 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -16,24 +19,22 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
#endif

35
arch/arm/include/asm/arch-mx5/gpio.h Normal file
View file

@ -0,0 +1,35 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
#endif

12
arch/arm/include/asm/arch-mx5/imx-regs.h
View file

@ -235,6 +235,11 @@
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
#define DP_MFD_864 (180 - 1) /* PL Dither mode */
#define DP_MFN_864 180
#define DP_MFN_800_DIT 60 /* PL Dither mode */
#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
#define DP_MFD_850 (48 - 1)
#define DP_MFN_850 41
@ -404,13 +409,6 @@ struct iomuxc {
};
#endif
/* GPIO Registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
/* System Reset Controller (SRC) */
struct src {
u32 scr;

1
arch/arm/include/asm/arch-omap3/clocks_omap3.h
View file

@ -39,6 +39,7 @@
#define CORE_L4_DIV 2 /* 83MHz : L4 */
#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
/* PER DPLL */

174
arch/arm/include/asm/arch-omap3/dss.h Normal file
View file

@ -0,0 +1,174 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* Referred to Linux Kernel DSS driver files for OMAP3 by
* Tomi Valkeinen from drivers/video/omap2/dss/
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 and any
* later version the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef DSS_H
#define DSS_H
/*
* DSS Base Registers
*/
#define OMAP3_DSS_BASE 0x48050040
#define OMAP3_DISPC_BASE 0x48050440
#define OMAP3_VENC_BASE 0x48050C00
/* DSS Registers */
struct dss_regs {
u32 control; /* 0x40 */
u32 sdi_control; /* 0x44 */
u32 pll_control; /* 0x48 */
};
/* DISPC Registers */
struct dispc_regs {
u32 control; /* 0x40 */
u32 config; /* 0x44 */
u32 reserve_2; /* 0x48 */
u32 default_color0; /* 0x4C */
u32 default_color1; /* 0x50 */
u32 trans_color0; /* 0x54 */
u32 trans_color1; /* 0x58 */
u32 line_status; /* 0x5C */
u32 line_number; /* 0x60 */
u32 timing_h; /* 0x64 */
u32 timing_v; /* 0x68 */
u32 pol_freq; /* 0x6C */
u32 divisor; /* 0x70 */
u32 global_alpha; /* 0x74 */
u32 size_dig; /* 0x78 */
u32 size_lcd; /* 0x7C */
};
/* VENC Registers */
struct venc_regs {
u32 rev_id; /* 0x00 */
u32 status; /* 0x04 */
u32 f_control; /* 0x08 */
u32 reserve_1; /* 0x0C */
u32 vidout_ctrl; /* 0x10 */
u32 sync_ctrl; /* 0x14 */
u32 reserve_2; /* 0x18 */
u32 llen; /* 0x1C */
u32 flens; /* 0x20 */
u32 hfltr_ctrl; /* 0x24 */
u32 cc_carr_wss_carr; /* 0x28 */
u32 c_phase; /* 0x2C */
u32 gain_u; /* 0x30 */
u32 gain_v; /* 0x34 */
u32 gain_y; /* 0x38 */
u32 black_level; /* 0x3C */
u32 blank_level; /* 0x40 */
u32 x_color; /* 0x44 */
u32 m_control; /* 0x48 */
u32 bstamp_wss_data; /* 0x4C */
u32 s_carr; /* 0x50 */
u32 line21; /* 0x54 */
u32 ln_sel; /* 0x58 */
u32 l21__wc_ctl; /* 0x5C */
u32 htrigger_vtrigger; /* 0x60 */
u32 savid__eavid; /* 0x64 */
u32 flen__fal; /* 0x68 */
u32 lal__phase_reset; /* 0x6C */
u32 hs_int_start_stop_x; /* 0x70 */
u32 hs_ext_start_stop_x; /* 0x74 */
u32 vs_int_start_x; /* 0x78 */
u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
u32 vs_ext_stop_y; /* 0x88 */
u32 reserve_3; /* 0x8C */
u32 avid_start_stop_x; /* 0x90 */
u32 avid_start_stop_y; /* 0x94 */
u32 reserve_4; /* 0x98 */
u32 reserve_5; /* 0x9C */
u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
u32 reserve_6; /* 0xAC */
u32 tvdetgp_int_start_stop_x; /* 0xB0 */
u32 tvdetgp_int_start_stop_y; /* 0xB4 */
u32 gen_ctrl; /* 0xB8 */
u32 reserve_7; /* 0xBC */
u32 reserve_8; /* 0xC0 */
u32 output_control; /* 0xC4 */
u32 dac_b__dac_c; /* 0xC8 */
u32 height_width; /* 0xCC */
};
/* Few Register Offsets */
#define FRAME_MODE_SHIFT 1
#define TFTSTN_SHIFT 3
#define DATALINES_SHIFT 8
/* Enabling Display controller */
#define LCD_ENABLE 1
#define DIG_ENABLE (1 << 1)
#define GO_LCD (1 << 5)
#define GO_DIG (1 << 6)
#define GP_OUT0 (1 << 15)
#define GP_OUT1 (1 << 16)
#define DISPC_ENABLE (LCD_ENABLE | \
DIG_ENABLE | \
GO_LCD | \
GO_DIG | \
GP_OUT0| \
GP_OUT1)
/* Configure VENC DSS Params */
#define VENC_CLK_ENABLE (1 << 3)
#define DAC_DEMEN (1 << 4)
#define DAC_POWERDN (1 << 5)
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
DAC_DEMEN | \
DAC_POWERDN | \
VENC_OUT_SEL)
/*
* Panel Configuration
*/
struct panel_config {
u32 timing_h;
u32 timing_v;
u32 pol_freq;
u32 divisor;
u32 lcd_size;
u32 panel_type;
u32 data_lines;
u32 load_mode;
u32 panel_color;
};
/*
* Generic DSS Functions
*/
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width);
void omap3_dss_panel_config(const struct panel_config *panel_cfg);
void omap3_dss_enable(void);
#endif /* DSS_H */

50
arch/arm/include/asm/arch-omap3/gpio.h Normal file
View file

@ -0,0 +1,50 @@
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _GPIO_OMAP3_H
#define _GPIO_OMAP3_H
#include <asm/omap_gpio.h>
#define OMAP34XX_GPIO1_BASE 0x48310000
#define OMAP34XX_GPIO2_BASE 0x49050000
#define OMAP34XX_GPIO3_BASE 0x49052000
#define OMAP34XX_GPIO4_BASE 0x49054000
#define OMAP34XX_GPIO5_BASE 0x49056000
#define OMAP34XX_GPIO6_BASE 0x49058000
#endif /* _GPIO_OMAP3_H */

8
arch/arm/include/asm/arch-omap3/omap3.h
View file

@ -100,14 +100,6 @@ struct s32ktimer {
#endif /* __ASSEMBLY__ */
/* OMAP3 GPIO registers */
#define OMAP34XX_GPIO1_BASE 0x48310000
#define OMAP34XX_GPIO2_BASE 0x49050000
#define OMAP34XX_GPIO3_BASE 0x49052000
#define OMAP34XX_GPIO4_BASE 0x49054000
#define OMAP34XX_GPIO5_BASE 0x49056000
#define OMAP34XX_GPIO6_BASE 0x49058000
#ifndef __ASSEMBLY__
struct gpio {
unsigned char res1[0x34];

12
arch/arm/include/asm/arch-omap4/clocks.h
View file

@ -679,12 +679,12 @@ struct dpll_regs {
struct dpll_params {
u32 m;
u32 n;
u8 m2;
u8 m3;
u8 m4;
u8 m5;
u8 m6;
u8 m7;
s8 m2;
s8 m3;
s8 m4;
s8 m5;
s8 m6;
s8 m7;
};
#endif /* _CLOCKS_OMAP4_H_ */

50
arch/arm/include/asm/arch-omap4/gpio.h Normal file
View file

@ -0,0 +1,50 @@
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _GPIO_OMAP4_H
#define _GPIO_OMAP4_H
#include <asm/omap_gpio.h>
#define OMAP44XX_GPIO1_BASE 0x4A310000
#define OMAP44XX_GPIO2_BASE 0x48055000
#define OMAP44XX_GPIO3_BASE 0x48057000
#define OMAP44XX_GPIO4_BASE 0x48059000
#define OMAP44XX_GPIO5_BASE 0x4805B000
#define OMAP44XX_GPIO6_BASE 0x4805D000
#endif /* _GPIO_OMAP4_H */

8
arch/arm/include/asm/arch-omap4/omap4.h
View file

@ -153,12 +153,4 @@ struct s32ktimer {
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
/* GPIO */
#define OMAP44XX_GPIO1_BASE 0x4A310000
#define OMAP44XX_GPIO2_BASE 0x48055000
#define OMAP44XX_GPIO3_BASE 0x48057000
#define OMAP44XX_GPIO4_BASE 0x48059000
#define OMAP44XX_GPIO5_BASE 0x4805B000
#define OMAP44XX_GPIO6_BASE 0x4805D000
#endif

29
arch/arm/include/asm/arch-s5pc1xx/gpio.h
View file

@ -126,14 +126,27 @@ struct s5pc110_gpio {
};
/* functions */
void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
static inline unsigned int s5p_gpio_base(int nr)
{
return S5PC110_GPIO_BASE;
}
#define s5pc110_gpio_get_nr(bank, pin) \
((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#endif
/* Pin configurations */

45
arch/arm/include/asm/arch-s5pc2xx/gpio.h
View file

@ -80,14 +80,43 @@ struct s5pc210_gpio_part3 {
};
/* functions */
void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define s5pc210_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct s5pc210_gpio_part1 *) \
S5PC210_GPIO_PART1_BASE)->bank)) \
- S5PC210_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define GPIO_PART1_MAX ((sizeof(struct s5pc210_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define s5pc210_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct s5pc210_gpio_part2 *) \
S5PC210_GPIO_PART2_BASE)->bank)) \
- S5PC210_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
static inline unsigned int s5p_gpio_base(int nr)
{
if (nr < GPIO_PART1_MAX)
return S5PC210_GPIO_PART1_BASE;
else
return S5PC210_GPIO_PART2_BASE;
return 0;
}
#endif
/* Pin configurations */

127
arch/arm/include/asm/arch-tegra2/clk_rst.h
View file

@ -24,15 +24,34 @@
#ifndef _CLK_RST_H_
#define _CLK_RST_H_
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
uint pll_out; /* output control */
uint reserved;
uint pll_misc; /* other misc things */
};
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll_simple {
uint pll_base; /* the control register */
uint pll_misc; /* other misc things */
};
/*
* Most PLLs use the clk_pll structure, but some have a simpler two-member
* structure for which we use clk_pll_simple. The reason for this non-
* othogonal setup is not stated.
*/
#define TEGRA_CLK_PLLS 6
#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */
#define TEGRA_CLK_REGS 3 /* Number of clock enable registers */
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
struct clk_rst_ctlr {
uint crc_rst_src; /* _RST_SOURCE_0, 0x00 */
uint crc_rst_dev_l; /* _RST_DEVICES_L_0, 0x04 */
uint crc_rst_dev_h; /* _RST_DEVICES_H_0, 0x08 */
uint crc_rst_dev_u; /* _RST_DEVICES_U_0, 0x0C */
uint crc_clk_out_enb_l; /* _CLK_OUT_ENB_L_0, 0x10 */
uint crc_clk_out_enb_h; /* _CLK_OUT_ENB_H_0, 0x14 */
uint crc_clk_out_enb_u; /* _CLK_OUT_ENB_U_0, 0x18 */
uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
uint crc_reserved0; /* reserved_0, 0x1C */
uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */
uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
@ -52,44 +71,11 @@ struct clk_rst_ctlr {
uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
uint crc_pllc_base; /* _PLLC_BASE_0, 0x80 */
uint crc_pllc_out; /* _PLLC_OUT_0, 0x84 */
uint crc_reserved3; /* reserved_3, 0x88 */
uint crc_pllc_misc; /* _PLLC_MISC_0, 0x8C */
struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
uint crc_pllm_base; /* _PLLM_BASE_0, 0x90 */
uint crc_pllm_out; /* _PLLM_OUT_0, 0x94 */
uint crc_reserved4; /* reserved_4, 0x98 */
uint crc_pllm_misc; /* _PLLM_MISC_0, 0x9C */
/* PLLs from 0xe0 to 0xf4 */
struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
uint crc_pllp_base; /* _PLLP_BASE_0, 0xA0 */
uint crc_pllp_outa; /* _PLLP_OUTA_0, 0xA4 */
uint crc_pllp_outb; /* _PLLP_OUTB_0, 0xA8 */
uint crc_pllp_misc; /* _PLLP_MISC_0, 0xAC */
uint crc_plla_base; /* _PLLA_BASE_0, 0xB0 */
uint crc_plla_out; /* _PLLA_OUT_0, 0xB4 */
uint crc_reserved5; /* reserved_5, 0xB8 */
uint crc_plla_misc; /* _PLLA_MISC_0, 0xBC */
uint crc_pllu_base; /* _PLLU_BASE_0, 0xC0 */
uint crc_reserved6; /* _reserved_6, 0xC4 */
uint crc_reserved7; /* _reserved_7, 0xC8 */
uint crc_pllu_misc; /* _PLLU_MISC_0, 0xCC */
uint crc_plld_base; /* _PLLD_BASE_0, 0xD0 */
uint crc_reserved8; /* _reserved_8, 0xD4 */
uint crc_reserved9; /* _reserved_9, 0xD8 */
uint crc_plld_misc; /* _PLLD_MISC_0, 0xDC */
uint crc_pllx_base; /* _PLLX_BASE_0, 0xE0 */
uint crc_pllx_misc; /* _PLLX_MISC_0, 0xE4 */
uint crc_plle_base; /* _PLLE_BASE_0, 0xE8 */
uint crc_plle_misc; /* _PLLE_MISC_0, 0xEC */
uint crc_plls_base; /* _PLLS_BASE_0, 0xF0 */
uint crc_plls_misc; /* _PLLS_MISC_0, 0xF4 */
uint crc_reserved10; /* _reserved_10, 0xF8 */
uint crc_reserved11; /* _reserved_11, 0xFC */
@ -154,46 +140,37 @@ struct clk_rst_ctlr {
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
};
#define PLL_BYPASS (1 << 31)
#define PLL_ENABLE (1 << 30)
#define PLL_BASE_OVRRIDE (1 << 28)
#define PLL_DIVP (1 << 20) /* post divider, b22:20 */
#define PLL_DIVM 0x0C /* input divider, b4:0 */
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
#define CPU1_CLK_STP_SHIFT 9
#define SWR_UARTD_RST (1 << 1)
#define CLK_ENB_UARTD (1 << 1)
#define SWR_UARTA_RST (1 << 6)
#define CLK_ENB_UARTA (1 << 6)
#define CPU0_CLK_STP_SHIFT 8
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
#define SWR_CPU_RST (1 << 0)
#define CLK_ENB_CPU (1 << 0)
#define SWR_CSITE_RST (1 << 9)
#define CLK_ENB_CSITE (1 << 9)
/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
#define PLL_BYPASS_SHIFT 31
#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
#define SET_CPURESET0 (1 << 0)
#define SET_DERESET0 (1 << 4)
#define SET_DBGRESET0 (1 << 12)
#define PLL_ENABLE_SHIFT 30
#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
#define SET_CPURESET1 (1 << 1)
#define SET_DERESET1 (1 << 5)
#define SET_DBGRESET1 (1 << 13)
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
#define CLR_CPURESET0 (1 << 0)
#define CLR_DERESET0 (1 << 4)
#define CLR_DBGRESET0 (1 << 12)
#define PLL_DIVP_SHIFT 20
#define CLR_CPURESET1 (1 << 1)
#define CLR_DERESET1 (1 << 5)
#define CLR_DBGRESET1 (1 << 13)
#define PLL_DIVN_SHIFT 8
#define CPU0_CLK_STP (1 << 8)
#define CPU1_CLK_STP (1 << 9)
#define PLL_DIVM_SHIFT 0
#define CPCON (1 << 8)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
#define SWR_SDMMC4_RST (1 << 15)
#define CLK_ENB_SDMMC4 (1 << 15)
#define SWR_SDMMC3_RST (1 << 5)
#define CLK_ENB_SDMMC3 (1 << 5)
#define PLL_LFCON_SHIFT 4
#define PLLU_VCO_FREQ_SHIFT 20
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
#endif /* CLK_RST_H */

263
arch/arm/include/asm/arch-tegra2/clock.h Normal file
View file

@ -0,0 +1,263 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 clock control functions */
#ifndef _CLOCK_H
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
CLOCK_OSC_FREQ_13_0,
CLOCK_OSC_FREQ_19_2,
CLOCK_OSC_FREQ_12_0,
CLOCK_OSC_FREQ_26_0,
CLOCK_OSC_FREQ_COUNT,
};
/* The PLLs supported by the hardware */
enum clock_pll_id {
CLOCK_PLL_ID_FIRST,
CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST,
CLOCK_PLL_ID_MEMORY,
CLOCK_PLL_ID_PERIPH,
CLOCK_PLL_ID_AUDIO,
CLOCK_PLL_ID_USB,
CLOCK_PLL_ID_DISPLAY,
/* now the simple ones */
CLOCK_PLL_ID_FIRST_SIMPLE,
CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE,
CLOCK_PLL_ID_EPCI,
CLOCK_PLL_ID_SFROM32KHZ,
CLOCK_PLL_ID_COUNT,
};
/* The clocks supported by the hardware */
enum periph_id {
PERIPH_ID_FIRST,
/* Low word: 31:0 */
PERIPH_ID_CPU = PERIPH_ID_FIRST,
PERIPH_ID_RESERVED1,
PERIPH_ID_RESERVED2,
PERIPH_ID_AC97,
PERIPH_ID_RTC,
PERIPH_ID_TMR,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
/* 8 */
PERIPH_ID_GPIO,
PERIPH_ID_SDMMC2,
PERIPH_ID_SPDIF,
PERIPH_ID_I2S1,
PERIPH_ID_I2C1,
PERIPH_ID_NDFLASH,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC4,
/* 16 */
PERIPH_ID_TWC,
PERIPH_ID_PWC,
PERIPH_ID_I2S2,
PERIPH_ID_EPP,
PERIPH_ID_VI,
PERIPH_ID_2D,
PERIPH_ID_USBD,
PERIPH_ID_ISP,
/* 24 */
PERIPH_ID_3D,
PERIPH_ID_IDE,
PERIPH_ID_DISP2,
PERIPH_ID_DISP1,
PERIPH_ID_HOST1X,
PERIPH_ID_VCP,
PERIPH_ID_RESERVED30,
PERIPH_ID_CACHE2,
/* Middle word: 63:32 */
PERIPH_ID_MEM,
PERIPH_ID_AHBDMA,
PERIPH_ID_APBDMA,
PERIPH_ID_RESERVED35,
PERIPH_ID_KBC,
PERIPH_ID_STAT_MON,
PERIPH_ID_PMC,
PERIPH_ID_FUSE,
/* 40 */
PERIPH_ID_KFUSE,
PERIPH_ID_SBC1,
PERIPH_ID_SNOR,
PERIPH_ID_SPI1,
PERIPH_ID_SBC2,
PERIPH_ID_XIO,
PERIPH_ID_SBC3,
PERIPH_ID_DVC_I2C,
/* 48 */
PERIPH_ID_DSI,
PERIPH_ID_TVO,
PERIPH_ID_MIPI,
PERIPH_ID_HDMI,
PERIPH_ID_CSI,
PERIPH_ID_TVDAC,
PERIPH_ID_I2C2,
PERIPH_ID_UART3,
/* 56 */
PERIPH_ID_RESERVED56,
PERIPH_ID_EMC,
PERIPH_ID_USB2,
PERIPH_ID_USB3,
PERIPH_ID_MPE,
PERIPH_ID_VDE,
PERIPH_ID_BSEA,
PERIPH_ID_BSEV,
/* Upper word 95:64 */
PERIPH_ID_SPEEDO,
PERIPH_ID_UART4,
PERIPH_ID_UART5,
PERIPH_ID_I2C3,
PERIPH_ID_SBC4,
PERIPH_ID_SDMMC3,
PERIPH_ID_PCIE,
PERIPH_ID_OWR,
/* 72 */
PERIPH_ID_AFI,
PERIPH_ID_CORESIGHT,
PERIPH_ID_RESERVED74,
PERIPH_ID_AVPUCQ,
PERIPH_ID_RESERVED76,
PERIPH_ID_RESERVED77,
PERIPH_ID_RESERVED78,
PERIPH_ID_RESERVED79,
/* 80 */
PERIPH_ID_RESERVED80,
PERIPH_ID_RESERVED81,
PERIPH_ID_RESERVED82,
PERIPH_ID_RESERVED83,
PERIPH_ID_IRAMA,
PERIPH_ID_IRAMB,
PERIPH_ID_IRAMC,
PERIPH_ID_IRAMD,
/* 88 */
PERIPH_ID_CRAM2,
PERIPH_ID_COUNT,
};
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
#define PERIPH_REG(id) ((id) >> 5)
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
/* return 1 if a PLL ID is in range */
#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \
(id) < CLOCK_PLL_ID_COUNT)
/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
(id) < PERIPH_ID_COUNT)
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
/* return the current oscillator clock frequency */
enum clock_osc_freq clock_get_osc_freq(void);
/*
* Start PLL using the provided configuration parameters.
*
* @param id clock id
* @param divm input divider
* @param divn feedback divider
* @param divp post divider 2^n
* @param cpcon charge pump setup control
* @param lfcon loop filter setup control
*
* @returns monotonic time in us that the PLL will be stable
*/
unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon);
/*
* Enable a clock
*
* @param id clock id
*/
void clock_enable(enum periph_id clkid);
/*
* Set whether a clock is enabled or disabled.
*
* @param id clock id
* @param enable 1 to enable, 0 to disable
*/
void clock_set_enable(enum periph_id clkid, int enable);
/*
* Reset a peripheral. This puts it in reset, waits for a delay, then takes
* it out of reset and waits for th delay again.
*
* @param periph_id peripheral to reset
* @param us_delay time to delay in microseconds
*/
void reset_periph(enum periph_id periph_id, int us_delay);
/*
* Put a peripheral into or out of reset.
*
* @param periph_id peripheral to reset
* @param enable 1 to put into reset, 0 to take out of reset
*/
void reset_set_enable(enum periph_id periph_id, int enable);
/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
crc_rst_de = 1 << 2, /* What is de? */
crc_rst_watchdog = 1 << 3,
crc_rst_debug = 1 << 4,
};
/*
* Put parts of the CPU complex into or out of reset.\
*
* @param cpu cpu number (0 or 1 on Tegra2)
* @param which which parts of the complex to affect (OR of crc_reset_id)
* @param reset 1 to assert reset, 0 to de-assert
*/
void reset_cmplx_set_enable(int cpu, int which, int reset);
#endif

161
arch/arm/include/asm/arch-tegra2/pinmux.h
View file

@ -24,6 +24,142 @@
#ifndef _PINMUX_H_
#define _PINMUX_H_
/* Pins which we can set to tristate or normal */
enum pmux_pin {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
PIN_ATA,
PIN_ATB,
PIN_ATC,
PIN_ATD,
PIN_CDEV1,
PIN_CDEV2,
PIN_CSUS,
PIN_DAP1,
PIN_DAP2,
PIN_DAP3,
PIN_DAP4,
PIN_DTA,
PIN_DTB,
PIN_DTC,
PIN_DTD,
PIN_DTE,
PIN_GPU,
PIN_GPV,
PIN_I2CP,
PIN_IRTX,
PIN_IRRX,
PIN_KBCB,
PIN_KBCA,
PIN_PMC,
PIN_PTA,
PIN_RM,
PIN_KBCE,
PIN_KBCF,
PIN_GMA,
PIN_GMC,
PIN_SDMMC1,
PIN_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
PIN_GME,
PIN_SDC,
PIN_SDD,
PIN_RESERVED0,
PIN_SLXA,
PIN_SLXC,
PIN_SLXD,
PIN_SLXK,
PIN_SPDI,
PIN_SPDO,
PIN_SPIA,
PIN_SPIB,
PIN_SPIC,
PIN_SPID,
PIN_SPIE,
PIN_SPIF,
PIN_SPIG,
PIN_SPIH,
PIN_UAA,
PIN_UAB,
PIN_UAC,
PIN_UAD,
PIN_UCA,
PIN_UCB,
PIN_RESERVED1,
PIN_ATE,
PIN_KBCC,
PIN_RESERVED2,
PIN_RESERVED3,
PIN_GMB,
PIN_GMD,
PIN_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
PIN_LD0,
PIN_LD1,
PIN_LD2,
PIN_LD3,
PIN_LD4,
PIN_LD5,
PIN_LD6,
PIN_LD7,
PIN_LD8,
PIN_LD9,
PIN_LD10,
PIN_LD11,
PIN_LD12,
PIN_LD13,
PIN_LD14,
PIN_LD15,
PIN_LD16,
PIN_LD17,
PIN_LHP0,
PIN_LHP1,
PIN_LHP2,
PIN_LVP0,
PIN_LVP1,
PIN_HDINT,
PIN_LM0,
PIN_LM1,
PIN_LVS,
PIN_LSC0,
PIN_LSC1,
PIN_LSCK,
PIN_LDC,
PIN_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
PIN_LSPI,
PIN_LSDA,
PIN_LSDI,
PIN_LPW0,
PIN_LPW1,
PIN_LPW2,
PIN_LDI,
PIN_LHS,
PIN_LPP,
PIN_RESERVED4,
PIN_KBCD,
PIN_GPU7,
PIN_DTF,
PIN_UDA,
PIN_CRTP,
PIN_SDB,
};
#define TEGRA_TRISTATE_REGS 4
/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
@ -31,10 +167,7 @@ struct pmux_tri_ctlr {
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */
uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */
uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */
uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */
uint pmt_tri[TEGRA_TRISTATE_REGS]; /* _TRI_STATE_REG_A/B/C/D_0 14-20 */
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
@ -48,14 +181,16 @@ struct pmux_tri_ctlr {
uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
};
#define Z_GMC (1 << 29)
#define Z_IRRX (1 << 20)
#define Z_IRTX (1 << 19)
#define Z_GMA (1 << 28)
#define Z_GME (1 << 0)
#define Z_ATB (1 << 1)
#define Z_SDB (1 << 15)
#define Z_SDC (1 << 1)
#define Z_SDD (1 << 2)
/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */
#define TRISTATE_REG(id) ((id) >> 5)
/* Mask value for a tristate (within TRISTATE_REG(id)) */
#define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
/* Set a pin to tristate */
void pinmux_tristate_enable(enum pmux_pin pin);
/* Set a pin to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pin pin);
#endif /* PINMUX_H */

22
board/edb93xx/flash_cfg.c → arch/arm/include/asm/arch-tegra2/timer.h
View file

@ -1,8 +1,5 @@
/*
* Flash setup for Cirrus edb93xx boards
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
@ -22,17 +19,12 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
/* Tegra2 timer functions */
#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
1 << SMC_BCR_MW_SHIFT)
#ifndef _TEGRA2_TIMER_H
#define _TEGRA2_TIMER_H
void flash_cfg(void)
{
struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);
writel(SMC_BCR6_VALUE, &smc->bcr6);
}
#endif

19
arch/arm/lib/board.c
View file

@ -275,10 +275,6 @@ void board_init_f(ulong bootflag)
gd->mon_len = _bss_end_ofs;
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
@ -376,6 +372,11 @@ void board_init_f(ulong bootflag)
gd->bd = bd;
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof (bd_t), addr_sp);
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
@ -451,11 +452,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = _end_ofs;
/*
* Enable D$:
* I$, if needed, must be already enabled in start.S
*/
dcache_enable();
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
@ -626,7 +625,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif

15
arch/arm/lib/cache-pl310.c
View file

@ -26,6 +26,7 @@
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <config.h>
#include <common.h>
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)
u32 pa, line_size = 32;
/*
* If start address is not aligned to cache-line flush the first
* line to prevent affecting somebody else's buffer
* If start address is not aligned to cache-line do not
* invalidate the first cache-line
*/
if (start & (line_size - 1)) {
v7_outer_cache_flush_range(start, start + 1);
printf("ERROR: %s - start address is not aligned - 0x%08x\n",
__func__, start);
/* move to next cache line */
start = (start + line_size - 1) & ~(line_size - 1);
}
/*
* If stop address is not aligned to cache-line flush the last
* line to prevent affecting somebody else's buffer
* If stop address is not aligned to cache-line do not
* invalidate the last cache-line
*/
if (stop & (line_size - 1)) {
v7_outer_cache_flush_range(stop, stop + 1);
printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
__func__, stop);
/* align to the beginning of this cache line */
stop &= ~(line_size - 1);
}

12
arch/arm/lib/cache.c
View file

@ -53,3 +53,15 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
/*
* Default implementation of enable_caches()
* Real implementation should be in platform code
*/
void __enable_caches(void)
{
puts("WARNING: Caches not enabled\n");
}
void enable_caches(void)
__attribute__((weak, alias("__enable_caches")));

3
arch/arm/lib/memcpy.S
View file

@ -60,6 +60,9 @@
.globl memcpy
memcpy:
cmp r0, r1
moveq pc, lr
enter r4, lr
subs r2, r2, #4

72
board/armadillo/armadillo.c
View file

@ -1,72 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
* Armadillo board HT1070
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <clps7111.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* Activate LED flasher */
IO_LEDFLSH = 0x40;
/* arch number MACH_TYPE_ARMADILLO - not official*/
gd->bd->bi_arch_number = 83;
/* location of boot parameters */
gd->bd->bi_boot_params = 0xc0000100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_CS8900
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
#endif
return rc;
}
#endif

29
board/armadillo/config.mk
View file

@ -1,29 +0,0 @@
#
# (C) Copyright 2000
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#address where u-boot will be relocated
CONFIG_SYS_TEXT_BASE = 0xc0f80000

340
board/armadillo/flash.c
View file

@ -1,340 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
* Flash driver for armadillo board HT1070
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#define FLASH_BANK_SIZE 0x400000
/*value used by hermit is 0x200*/
/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/
#define MAIN_SECT_SIZE 0x10000
#define UNALIGNED_MASK (3)
#define FL_WORD(addr) (*(volatile unsigned short*)(addr))
#define FLASH_TIMEOUT 20000000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
*/
ulong flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK);
/*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
panic ("configured too many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] =
flashbase + j * MAIN_SECT_SIZE;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (FUJ_MANUFACT & FLASH_VENDMASK):
printf ("Fujitsu: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
/*
switch (info->flash_id & FLASH_TYPEMASK) {
case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
printf ("28F128J3 (128Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
break;
}
*/
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
/*
Done: ;
*/
}
/*
* * Loop until both write state machines complete.
* */
static unsigned short flash_status_wait (unsigned long addr,
unsigned short value)
{
unsigned short status;
long timeout = FLASH_TIMEOUT;
while (((status = (FL_WORD (addr))) != value) && timeout > 0) {
timeout--;
}
return status;
}
/*
* Loop until the Write State machine is ready, then do a full error
* check. Clear status and leave the flash in Read Array mode; return
* 0 for no error, -1 for error.
*/
static int flash_status_full_check (unsigned long addr, unsigned short value1,
unsigned short value2)
{
unsigned short status1, status2;
status1 = flash_status_wait (addr, value1);
status2 = flash_status_wait (addr + 2, value2);
return (status1 != value1 || status2 != value2) ? -1 : 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
int rc = ERR_OK;
unsigned long base;
unsigned long addr;
ulong start;
if ((info->flash_id & FLASH_VENDMASK) !=
(FUJ_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts ();
printf ("Erasing %d sectors starting at sector %2d.\n"
"This make take some time ... ",
s_last - s_first, sect);
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
/* ARM simple, non interrupt dependent timer */
start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
addr = sect * MAIN_SECT_SIZE;
addr &= ~(unsigned long) UNALIGNED_MASK; /* word align */
base = addr & 0xF0000000;
FL_WORD (base + (0x555 << 1)) = 0xAA;
FL_WORD (base + (0x2AA << 1)) = 0x55;
FL_WORD (base + (0x555 << 1)) = 0x80;
FL_WORD (base + (0x555 << 1)) = 0xAA;
FL_WORD (base + (0x2AA << 1)) = 0x55;
FL_WORD (addr) = 0x30;
if (flash_status_full_check (addr, 0xFFFF, 0xFFFF))
return ERR_PROTECTED;
}
}
printf ("\nDone.\n");
if (ctrlc ())
printf ("User Interrupt!\n");
/* allow flash to settle - wait 10 ms */
udelay_masked (10000);
if (flag)
enable_interrupts ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash
*/
static int write_word (flash_info_t * info, ulong dest, ushort data)
{
int flag;
unsigned long base;
ulong start;
/* Check if Flash is (sufficiently) erased
*/
if ((FL_WORD (dest) & data) != data)
return ERR_NOT_ERASED;
/*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts ();
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
base = dest & 0xF0000000;
FL_WORD (base + (0x555 << 1)) = 0xAA;
FL_WORD (base + (0x2AA << 1)) = 0x55;
FL_WORD (base + (0x555 << 1)) = 0xA0;
FL_WORD (dest) = data;
/*printf("writing 0x%p = 0x%x\n",dest,data); */
if (flash_status_wait (dest, data) != data)
return ERR_PROG_ERROR;
if (flag)
enable_interrupts ();
return ERR_OK;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
ushort data;
int l;
int i, rc;
wp = (addr & ~1); /* get lower word aligned address */
printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src);
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
for (; i < 2 && cnt > 0; ++i) {
data = (data >> 8) | (*src++ << 8);
--cnt;
++cp;
}
for (; cnt == 0 && i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 2;
}
/*
* handle word aligned part
*/
while (cnt >= 2) {
data = *((vu_short *) src);
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 0) {
printf ("\nDone.\n");
return ERR_OK;
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
data = (data >> 8) | (*src++ << 8);
--cnt;
}
for (; i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
return write_word (info, wp, data);
}

66
board/armadillo/lowlevel_init.S
View file

@ -1,66 +0,0 @@
/*
* Initialization stuff - taken from hermit
* (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
* Armadillo board HT1070
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
/* some parameters for the board */
/* setting up the memory */
#define SRAM_START 0x60000000
#define SRAM_SIZE 0x0000c000
.globl lowlevel_init
lowlevel_init:
mov r0, #0x70 /* 32-bit code + data, MMU mandatory */
mcr p15, 0, r0, c1, c0, 0 /* MMU init */
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov r0, #0x80000000 /* I/O base */
mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */
add r2, r0, #0x2200 /* address of SYSCON3 in r2 */
str r1, [r2] /* set clock speed to 73.728 MHz */
mov r1, #0x81 /* 64KHz DRAM refresh period */
str r1, [r0, #0x200] /* set DRFPR */
mov r1, #0x500 /* permanent enable, 16bits wide */
add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */
add r2, r0, #0x2300 /* load address in r2 */
str r1, [r2]
mov r1, #0x100 /* SDRAM refresh rate */
add r2, r0, #0x2340 /* load address in r2 */
str r1, [r2]
mov sp, #SRAM_START /* init stack pointer */
add sp, sp, #SRAM_SIZE
/* everything is fine now */
mov pc, lr

15
board/armltd/integrator/integrator.c
View file

@ -86,15 +86,9 @@ int misc_init_r (void)
return (0);
}
/******************************
Routine:
Description:
******************************/
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
@ -118,8 +112,13 @@ extern void dram_query(void);
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
0x01000000 << sdram_shift);
}
#else
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
return 0;

2
board/armltd/integrator/lowlevel_init.S
View file

@ -199,7 +199,7 @@ cm_remap:
/* Now 0x00000000 is writeable, replace the vectors */
ldr r0, =_start /* r0 <- start of vectors */
ldr r2, =_armboot_start /* r2 <- past vectors */
ldr r2, =_TEXT_BASE /* r2 <- past vectors */
sub r1,r1,r1 /* destination 0x00000000 */
copy_vec:

220
board/armltd/integrator/split_by_variant.sh
View file

@ -1,220 +0,0 @@
#!/bin/sh
mkdir -p ${obj}include
mkdir -p ${obj}board/armltd/integrator
config_file=${obj}include/config.h
if [ "$1" = "ap" ]
then
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
cat > ${config_file} << _EOF
/* Integrator configuration implied by Makefile target */
#define CONFIG_INTEGRATOR /* Integrator board */
#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */
_EOF
# ---------------------------------------------------------
# Set the core module defines according to Core Module
# ---------------------------------------------------------
cpu="arm_intcm"
variant="unknown core module"
if [ "$2" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
case "$2" in
ap7_config)
cpu="arm_intcm"
variant="unported core module CM7TDMI"
;;
ap966)
cpu="arm_intcm"
variant="unported core module CM966E-S"
;;
ap922_config)
cpu="arm_intcm"
variant="unported core module CM922T"
;;
integratorap_config | \
ap_config)
cpu="arm_intcm"
variant="unspecified core module"
;;
ap720t_config)
cpu="arm720t"
echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \
>> ${config_file}
variant="Core module CM720T"
;;
ap922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
>> ${config_file}
;;
ap920t_config)
cpu="arm920t"
variant="Core module CM920T"
echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
>> ${config_file}
;;
ap926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
>> ${config_file}
;;
ap946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
>> ${config_file}
;;
*)
echo "$0:: Unknown core module"
variant="unknown core module"
cpu="arm_intcm"
;;
esac
fi
case "$cpu" in
arm_intcm)
cat >> ${config_file} << _EOF
/* Core module undefined/not ported */
#define CONFIG_ARM_INTCM 1
#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
#undef CONFIG_CM_REMAP /* CM may not support remapping */
#undef CONFIG_CM_INIT /* CM may not have initialization reg */
#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
/* May not be processor without cache support */
#define CONFIG_SYS_ICACHE_OFF 1
#define CONFIG_SYS_DCACHE_OFF 1
_EOF
;;
arm720t)
cat >> ${config_file} << _EOF
/* May not be processor without cache support */
#define CONFIG_SYS_ICACHE_OFF 1
#define CONFIG_SYS_DCACHE_OFF 1
_EOF
;;
esac
else
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
cat >> ${config_file} << _EOF
/* Integrator configuration implied by Makefile target */
#define CONFIG_INTEGRATOR /* Integrator board */
#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP */
_EOF
cpu="arm_intcm"
variant="unknown core module"
if [ "$2" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
case "$2" in
ap966)
cpu="arm_intcm"
variant="unported core module CM966E-S"
;;
ap922_config)
cpu="arm_intcm"
variant="unported core module CM922T"
;;
integratorcp_config | \
cp_config)
cpu="arm_intcm"
variant="unspecified core module"
;;
cp922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
>> ${config_file}
;;
cp920t_config)
cpu="arm920t"
variant="Core module CM920T"
echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
>> ${config_file}
;;
cp926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
>> ${config_file}
;;
cp946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
>> ${config_file}
;;
cp1136_config)
cpu="arm1136"
variant="Core module CM1136EJF-S"
echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \
>> ${config_file}
;;
*)
echo "$0:: Unknown core module"
variant="unknown core module"
cpu="arm_intcm"
;;
esac
fi
if [ "$cpu" = "arm_intcm" ]
then
cat >> ${config_file} << _EOF
/* Core module undefined/not ported */
#define CONFIG_ARM_INTCM 1
#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
#undef CONFIG_CM_REMAP /* CM may not support remapping */
#undef CONFIG_CM_INIT /* CM may not have initialization reg */
#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
_EOF
fi
fi # ap
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
$MKCONFIG -a -n "${2%%_config}" integrator$1 arm $cpu integrator armltd
echo "Variant: $variant with core $cpu"

2
board/armltd/versatile/versatile.c
View file

@ -94,7 +94,7 @@ int misc_init_r (void)
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}

53
board/assabet/Makefile
View file

@ -1,53 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# 2004 (c) MontaVista Software, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := assabet.o
SOBJS := setup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

131
board/assabet/assabet.c
View file

@ -1,131 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* 2004 (c) MontaVista Software, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Board dependent initialisation
*/
#define ECOR 0x8000
#define ECOR_RESET 0x80
#define ECOR_LEVEL_IRQ 0x40
#define ECOR_WR_ATTRIB 0x04
#define ECOR_ENABLE 0x01
#define ECSR 0x8002
#define ECSR_IOIS8 0x20
#define ECSR_PWRDWN 0x04
#define ECSR_INT 0x02
#define SMC_IO_SHIFT 2
#define NCR_0 (*((volatile u_char *)(0x100000a0)))
#define NCR_ENET_OSC_EN (1<<3)
static inline u8
readb(volatile u8 * p)
{
return *p;
}
static inline void
writeb(u8 v, volatile u8 * p)
{
*p = v;
}
static void
smc_init(void)
{
u8 ecor;
u8 ecsr;
volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
NCR_0 |= NCR_ENET_OSC_EN;
udelay(100);
ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
udelay(100);
/*
* The device will ignore all writes to the enable bit while
* reset is asserted, even if the reset bit is cleared in the
* same write. Must clear reset first, then enable the device.
*/
writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
/*
* Set the appropriate byte/word mode.
*/
ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
ecsr |= ECSR_IOIS8;
writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
udelay(100);
}
static void
neponset_init(void)
{
smc_init();
}
int
board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
gd->bd->bi_boot_params = 0xc0000100;
neponset_init();
return 0;
}
int
dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_LAN91C96
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
#endif
return rc;
}
#endif

7
board/assabet/config.mk
View file

@ -1,7 +0,0 @@
#
# SA-1110 based Intel Assabet board
#
# The Intel Assabet 1 bank of 32 MiB SDRAM
#
CONFIG_SYS_TEXT_BASE = 0xc1f00000

136
board/assabet/setup.S
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@ -1,136 +0,0 @@
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
* 2004 (c) MontaVista Software, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "config.h"
#include "version.h"
/*-----------------------------------------------------------------------
* Board defines:
*/
#define MDCNFG 0x00
#define MDCAS00 0x04
#define MDCAS01 0x08
#define MDCAS02 0x0C
#define MSC0 0x10
#define MSC1 0x14
#define MECR 0x18
#define MDREFR 0x1C
#define MDCAS20 0x20
#define MDCAS21 0x24
#define MDCAS22 0x28
#define MSC2 0x2C
#define SMCNFG 0x30
#define ASSABET_BCR (0x12000000)
#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17))
#define ASSABET_SCR_nNEPONSET (1 << 9)
#define NEPONSET_LEDS (0x10000010)
/*-----------------------------------------------------------------------
* Setup parameters for the board:
*/
MEM_BASE: .long 0xa0000000
MEM_START: .long 0xc0000000
mdcnfg: .long 0x72547254
mdcas00: .long 0xaaaaaa7f
mdcas01: .long 0xaaaaaaaa
mdcas02: .long 0xaaaaaaaa
msc0: .long 0x4b384370
msc1: .long 0x22212419
mecr: .long 0x994a994a
mdrefr: .long 0x04340327
mdcas20: .long 0xaaaaaa7f
mdcas21: .long 0xaaaaaaaa
mdcas22: .long 0xaaaaaaaa
msc2: .long 0x42196669
smcnfg: .long 0x00000000
BCR: .long ASSABET_BCR
BCR_DB1110: .long ASSABET_BCR_DB1110
LEDS: .long NEPONSET_LEDS
.globl lowlevel_init
lowlevel_init:
/* Setting up the memory and stuff */
ldr r0, MEM_BASE
ldr r1, mdcas00
str r1, [r0, #MDCAS00]
ldr r1, mdcas01
str r1, [r0, #MDCAS01]
ldr r1, mdcas02
str r1, [r0, #MDCAS02]
ldr r1, mdcas20
str r1, [r0, #MDCAS20]
ldr r1, mdcas21
str r1, [r0, #MDCAS21]
ldr r1, mdcas22
str r1, [r0, #MDCAS22]
ldr r1, mdrefr
str r1, [r0, #MDREFR]
ldr r1, mecr
str r1, [r0, #MECR]
ldr r1, msc0
str r1, [r0, #MSC0]
ldr r1, msc1
str r1, [r0, #MSC1]
ldr r1, msc2
str r1, [r0, #MSC2]
ldr r1, smcnfg
str r1, [r0, #SMCNFG]
ldr r1, mdcnfg
str r1, [r0, #MDCNFG]
/* Load something to activate bank */
ldr r2, MEM_START
.rept 8
ldr r3, [r2]
.endr
/* Enable SDRAM */
orr r1, r1, #0x00000001
str r1, [r0, #MDCNFG]
ldr r1, BCR
ldr r2, BCR_DB1110
str r2, [r1]
ldr r1, LEDS
mov r0, #0x3
str r0, [r1]
/* All done... */
mov pc, lr

56
board/atmel/at91cap9adk/Makefile
View file

@ -1,56 +0,0 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += at91cap9adk.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

352
board/atmel/at91cap9adk/at91cap9adk.c
View file

@ -1,352 +0,0 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91cap9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>
#define MP_BLOCK_3_BASE 0xFDF00000
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91cap9_slowclock_hw_init(void)
{
/*
* On AT91CAP9 revC CPUs, the slow clock can be based on an
* internal impreciseRC oscillator or an external 32kHz oscillator.
* Switch to the latter.
*/
#define ARCH_ID_AT91CAP9_REVB 0x399
#define ARCH_ID_AT91CAP9_REVC 0x601
if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
unsigned i, tmp = at91_sys_read(AT91_SCKCR);
if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
timer_init();
tmp |= AT91CAP9_SCKCR_OSC32EN;
at91_sys_write(AT91_SCKCR, tmp);
for (i = 0; i < 1200; i++)
udelay(1000);
tmp |= AT91CAP9_SCKCR_OSCSEL_32;
at91_sys_write(AT91_SCKCR, tmp);
udelay(200);
tmp &= ~AT91CAP9_SCKCR_RCEN;
at91_sys_write(AT91_SCKCR, tmp);
}
}
}
static void at91cap9_nor_hw_init(void)
{
unsigned long csa;
/* Ensure EBI supply is 3.3V */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* Configure SMC CS0 for parallel flash */
at91_sys_write(AT91_SMC_SETUP(0),
AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
at91_sys_write(AT91_SMC_PULSE(0),
AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
at91_sys_write(AT91_SMC_CYCLE(0),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(0),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
}
#ifdef CONFIG_CMD_NAND
static void at91cap9_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
/* RDY/BSY is not connected */
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void at91cap9_macb_hw_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PB22) => PHY normal mode (not Test mode)
* ERX0 (PB25) => PHY ADDR0
* ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
pin_to_mask(AT91_PIN_PB26),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0 << 8)) |
AT91_RSTC_URSTEN);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
pin_to_mask(AT91_PIN_PB26),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
at91_macb_hw_init();
/* Unlock EMAC, 3 0 2 1 sequence */
#define MP_MAC_KEY0 0x5969cb2a
#define MP_MAC_KEY1 0xb4a1872e
#define MP_MAC_KEY2 0x05683fbc
#define MP_MAC_KEY3 0x3634fba4
#define UNLOCK_MAC 0x00000008
writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
}
#endif
#ifdef CONFIG_USB_OHCI_NEW
static void at91cap9_uhp_hw_init(void)
{
/* Unlock USB OHCI, 3 2 0 1 sequence */
#define MP_OHCI_KEY0 0x896c11ca
#define MP_OHCI_KEY1 0x68ebca21
#define MP_OHCI_KEY2 0x4823efbc
#define MP_OHCI_KEY3 0x8651aae4
#define UNLOCK_OHCI 0x00000010
writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91CAP9_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
}
static void at91cap9_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
gd->fb_base = 0;
}
#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>
void lcd_show_board_info(void)
{
ulong dram_size, nand_size;
int i;
char temp[32];
lcd_printf ("%s\n", U_BOOT_VERSION);
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
}
#endif /* CONFIG_LCD_INFO */
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91CAP9ADK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91_serial_hw_init();
at91cap9_slowclock_hw_init();
at91cap9_nor_hw_init();
#ifdef CONFIG_CMD_NAND
at91cap9_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
at91cap9_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91cap9_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91cap9_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
#endif
return rc;
}

1
board/atmel/at91cap9adk/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x73000000

56
board/atmel/at91rm9200dk/Makefile
View file

@ -1,56 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += flash.o
COBJS-y += led.o
ifdef CONFIG_HAS_DATAFLASH
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
COBJS-y += partition.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

167
board/atmel/at91rm9200dk/at91rm9200dk.c
View file

@ -1,167 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <exports.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* Enable Ctrlc */
console_init_f ();
/* Correct IRDA resistor problem */
/* Set PA23_TXD in Output */
((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of AT91RM9200DK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
void board_reset (void)
{
AT91PS_PIO pio = AT91C_BASE_PIOA;
/* Clear PA19 to trigger the hard reset */
writel(0x00080000, pio->PIO_CODR);
writel(0x00080000, pio->PIO_OER);
writel(0x00080000, pio->PIO_PER);
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space
*/
#if defined(CONFIG_CMD_NAND)
extern ulong nand_probe (ulong physadr);
#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
void nand_init (void)
{
/* Setup Smart Media, fitst enable the address range of CS3 */
*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
/* set the bus interface characteristics based on
tDS Data Set up Time 30 - ns
tDH Data Hold Time 20 - ns
tALS ALE Set up Time 20 - ns
16ns at 60 MHz ~= 3 */
/*memory mapping structures */
#define SM_ID_RWH (5 << 28)
#define SM_RWH (1 << 28)
#define SM_RWS (0 << 24)
#define SM_TDF (1 << 8)
#define SM_NWS (3)
AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
AT91C_PC3_BFBAA_SMWE;
*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
AT91C_PC3_BFBAA_SMWE;
/* Configure PC2 as input (signal READY of the SmartMedia) */
*AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
*AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
*AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
*AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
/* PIOB and PIOC clock enabling */
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
printf (" No SmartMedia card inserted\n");
#ifdef DEBUG
printf (" SmartMedia card inserted\n");
printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
#endif
printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
}
#endif

1
board/atmel/at91rm9200dk/config.mk
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@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x21f00000

504
board/atmel/at91rm9200dk/flash.c
View file

@ -1,504 +0,0 @@
/*
* (C) Copyright 2002
* Lineo, Inc. <www.lineo.com>
* Bernhard Kuhn <bkuhn@lineo.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
ulong myflush(void);
/* Flash Organization Structure */
typedef struct OrgDef
{
unsigned int sector_number;
unsigned int sector_size;
} OrgDef;
/* Flash Organizations */
OrgDef OrgAT49BV16x4[] =
{
{ 8, 8*1024 }, /* 8 * 8 kBytes sectors */
{ 2, 32*1024 }, /* 2 * 32 kBytes sectors */
{ 30, 64*1024 }, /* 30 * 64 kBytes sectors */
};
OrgDef OrgAT49BV16x4A[] =
{
{ 8, 8*1024 }, /* 8 * 8 kBytes sectors */
{ 31, 64*1024 }, /* 31 * 64 kBytes sectors */
};
OrgDef OrgAT49BV6416[] =
{
{ 8, 8*1024 }, /* 8 * 8 kBytes sectors */
{ 127, 64*1024 }, /* 127 * 64 kBytes sectors */
};
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/* AT49BV1614A Codes */
#define FLASH_CODE1 0xAA
#define FLASH_CODE2 0x55
#define ID_IN_CODE 0x90
#define ID_OUT_CODE 0xF0
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
#define CMD_ERASE_SETUP 0x0080
#define CMD_ERASE_CONFIRM 0x0030
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
#define CMD_SECTOR_UNLOCK 0x0070
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00005555<<1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00002AAA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#define BIT_PROGRAM_ERROR 0x0020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define READY 1
#define ERR 2
#define TMO 4
/*-----------------------------------------------------------------------
*/
void flash_identification (flash_info_t * info)
{
volatile u16 manuf_code, device_code, add_device_code;
MEM_FLASH_ADDR1 = FLASH_CODE1;
MEM_FLASH_ADDR2 = FLASH_CODE2;
MEM_FLASH_ADDR1 = ID_IN_CODE;
manuf_code = *(volatile u16 *) CONFIG_SYS_FLASH_BASE;
device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + 2);
add_device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + (3 << 1));
MEM_FLASH_ADDR1 = FLASH_CODE1;
MEM_FLASH_ADDR2 = FLASH_CODE2;
MEM_FLASH_ADDR1 = ID_OUT_CODE;
/* Vendor type */
info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
printf ("Atmel: ");
if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
if ((add_device_code & FLASH_TYPEMASK) ==
(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
printf ("AT49BV1614A (16Mbit)\n");
} else { /* AT49BV1614 Flash */
info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
printf ("AT49BV1614 (16Mbit)\n");
}
} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
printf ("AT49BV6416 (64Mbit)\n");
}
}
ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
{
int i, nb_sectors = 0;
for (i=0; i<nb_blocks; i++){
nb_sectors += pOrgDef[i].sector_number;
}
return nb_sectors;
}
void flash_unlock_sector(flash_info_t * info, unsigned int sector)
{
volatile u16 *addr = (volatile u16 *) (info->start[sector]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
*addr = CMD_SECTOR_UNLOCK;
}
ulong flash_init (void)
{
int i, j, k;
unsigned int flash_nb_blocks, sector;
unsigned int start_address;
OrgDef *pOrgDef;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_identification (&flash_info[i]);
if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
pOrgDef = OrgAT49BV16x4;
flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
(ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */
pOrgDef = OrgAT49BV16x4A;
flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
(ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */
pOrgDef = OrgAT49BV6416;
flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
} else {
flash_nb_blocks = 0;
pOrgDef = OrgAT49BV16x4;
}
flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
memset (flash_info[i].protect, 0, flash_info[i].sector_count);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
panic ("configured too many flash banks!\n");
sector = 0;
start_address = flashbase;
flash_info[i].size = 0;
for (j = 0; j < flash_nb_blocks; j++) {
for (k = 0; k < pOrgDef[j].sector_number; k++) {
flash_info[i].start[sector++] = start_address;
start_address += pOrgDef[j].sector_size;
flash_info[i].size += pOrgDef[j].sector_size;
}
}
size += flash_info[i].size;
if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
(ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */
/* Unlock all sectors at reset */
for (j=0; j<flash_info[i].sector_count; j++){
flash_unlock_sector(&flash_info[i], j);
}
}
}
/* Protect binary boot image */
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + CONFIG_SYS_BOOT_SIZE - 1, &flash_info[0]);
/* Protect environment variables */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
/* Protect U-Boot gzipped image */
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_U_BOOT_BASE,
CONFIG_SYS_U_BOOT_BASE + CONFIG_SYS_U_BOOT_SIZE - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (ATM_MANUFACT & FLASH_VENDMASK):
printf ("Atmel: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (ATM_ID_BV1614 & FLASH_TYPEMASK):
printf ("AT49BV1614 (16Mbit)\n");
break;
case (ATM_ID_BV1614A & FLASH_TYPEMASK):
printf ("AT49BV1614A (16Mbit)\n");
break;
case (ATM_ID_BV6416 & FLASH_TYPEMASK):
printf ("AT49BV6416 (64Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
return;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
ulong result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1;
ulong start;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(ATM_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr = (volatile u16 *) (info->start[sect]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
chip1 = 0;
do {
result = *addr;
/* check timeout */
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
}
if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
chip1 = READY;
} while (!chip1);
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
if (chip1 == ERR) {
rc = ERR_PROG_ERROR;
goto outahere;
}
if (chip1 == TMO) {
rc = ERR_TIMOUT;
goto outahere;
}
printf ("ok.\n");
} else { /* it was protected */
printf ("protected!\n");
}
}
if (ctrlc ())
printf ("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay_masked (10000);
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash
*/
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
int rc = ERR_OK;
int cflag, iflag;
int chip1;
ulong start;
/*
* Check if Flash is (sufficiently) erased
*/
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait until flash is ready */
chip1 = 0;
do {
result = *addr;
/* check timeout */
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
if (!chip1 && ((result & 0x80) == (data & 0x80)))
chip1 = READY;
} while (!chip1);
*addr = CMD_READ_ARRAY;
if (chip1 == ERR || *addr != data)
rc = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp, data;
int rc;
if (addr & 1) {
printf ("unaligned destination not supported\n");
return ERR_ALIGN;
};
if ((int) src & 1) {
printf ("unaligned source not supported\n");
return ERR_ALIGN;
};
wp = addr;
while (cnt >= 2) {
data = *((volatile u16 *) src);
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 1) {
data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) <<
8);
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 1;
wp += 1;
cnt -= 1;
};
return ERR_OK;
}

80
board/atmel/at91rm9200dk/led.c
View file

@ -1,80 +0,0 @@
/*
* (C) Copyright 2006
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#define GREEN_LED AT91C_PIO_PB0
#define YELLOW_LED AT91C_PIO_PB1
#define RED_LED AT91C_PIO_PB2
void green_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
PIOB->PIO_CODR = GREEN_LED;
}
void yellow_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
PIOB->PIO_CODR = YELLOW_LED;
}
void red_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
PIOB->PIO_CODR = RED_LED;
}
void green_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
PIOB->PIO_SODR = GREEN_LED;
}
void yellow_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
PIOB->PIO_SODR = YELLOW_LED;
}
void red_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
PIOB->PIO_SODR = RED_LED;
}
void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;
PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */
/* Disable peripherals on LEDs */
PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
/* Enable pins as outputs */
PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
/* Turn all LEDs OFF */
PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
}

29
board/atmel/at91rm9200dk/mux.c
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@ -1,29 +0,0 @@
#include <config.h>
#include <common.h>
#include <asm/hardware.h>
#include <dataflash.h>
int AT91F_GetMuxStatus(void) {
AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */
AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */
if(AT91C_BASE_PIOB->PIO_ODSR & CONFIG_SYS_DATAFLASH_MMC_PIO)
return 1;
return 0;
}
void AT91F_SelectMMC(void) {
AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */
AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */
/* Set Output */
AT91C_BASE_PIOB->PIO_SODR = CONFIG_SYS_DATAFLASH_MMC_PIO;
}
void AT91F_SelectSPI(void) {
AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */
AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */
/* Clear Output */
AT91C_BASE_PIOB->PIO_CODR = CONFIG_SYS_DATAFLASH_MMC_PIO;
}

40
board/atmel/at91rm9200dk/partition.c
View file

@ -1,40 +0,0 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

117
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View file

@ -23,17 +23,14 @@
*/
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9g45.h>
#include <asm/arch/at91sam9_matrix.h>
#include <asm/io.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#ifdef CONFIG_CMD_NAND
static void at91sam9m10g45ek_nand_hw_init(void)
void at91sam9m10g45ek_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_TDF_(3));
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void)
#ifdef CONFIG_CMD_USB
static void at91sam9m10g45ek_usb_hw_init(void)
{
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
at91_set_gpio_output(AT91_PIN_PD1, 0);
at91_set_gpio_output(AT91_PIN_PD3, 0);
@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void)
#ifdef CONFIG_MACB
static void at91sam9m10g45ek_macb_hw_init(void)
{
unsigned long rstc;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
* RXDV (PA15) => PHY normal mode (not Test mode)
* ERX0 (PA12) => PHY ADDR0
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
* RXDV (PA15) => PHY normal mode (not Test mode)
* ERX0 (PA12) => PHY ADDR0
* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA12) |
pin_to_mask(AT91_PIN_PA13),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
&pioa->pudr);
rstc = at91_sys_read(AT91_RSTC_MR);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(rstc) |
AT91_RSTC_URSTEN);
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
&rstc->mr);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA15) |
pin_to_mask(AT91_PIN_PA12) |
pin_to_mask(AT91_PIN_PA13),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
&pioa->puer);
/* And the pins. */
at91_macb_hw_init();
}
#endif
@ -161,7 +166,7 @@ vidinfo_t panel_info = {
vl_vsync_len: 1,
vl_upper_margin:40,
vl_lower_margin:1,
mmio: AT91SAM9G45_LCDC_BASE,
mmio : ATMEL_BASE_LCDC,
};
@ -177,6 +182,8 @@ void lcd_disable(void)
static void at91sam9m10g45ek_lcd_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void)
at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
}
@ -227,7 +234,7 @@ void lcd_show_board_info(void)
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
CONFIG_SYS_AT91_CPU_NAME,
ATMEL_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
@ -243,6 +250,12 @@ void lcd_show_board_info(void)
#endif /* CONFIG_LCD_INFO */
#endif
int board_early_init_f(void)
{
at91_seriald_hw_init();
return 0;
}
int board_init(void)
{
/* Enable Ctrlc */
@ -254,10 +267,10 @@ int board_init(void)
#elif defined CONFIG_AT91SAM9G45EKES
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91_serial_hw_init();
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9m10g45ek_nand_hw_init();
#endif
@ -270,11 +283,9 @@ int board_init(void)
#ifdef CONFIG_ATMEL_SPI
at91_spi0_hw_init(1 << 4);
#endif
#ifdef CONFIG_MACB
at91sam9m10g45ek_macb_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9m10g45ek_lcd_hw_init();
#endif
@ -283,8 +294,8 @@ int board_init(void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
@ -298,7 +309,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
#endif
return rc;
}

6
board/atmel/at91sam9m10g45ek/led.c
View file

@ -23,15 +23,17 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9g45.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);

88
board/calao/sbc35_a9g20/sbc35_a9g20.c
View file

@ -26,15 +26,14 @@
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@ -50,33 +49,36 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void sbc35_a9g20_nand_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_TDF_(2));
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@ -89,10 +91,13 @@ static void sbc35_a9g20_nand_hw_init(void)
#ifdef CONFIG_MACB
static void sbc35_a9g20_macb_hw_init(void)
{
unsigned long rstc;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
/* Enable EMAC clock */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
/*
* Disable pull-up on:
@ -111,24 +116,23 @@ static void sbc35_a9g20_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
&pioa->pudr);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0D << 8)) |
AT91_RSTC_URSTEN);
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(rstc) |
AT91_RSTC_URSTEN);
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
&rstc->mr);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |
@ -137,7 +141,7 @@ static void sbc35_a9g20_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
pin_to_mask(AT91_PIN_PA28),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
&pioa->puer);
at91_macb_hw_init();
}
@ -150,9 +154,9 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
at91_serial_hw_init();
at91_seriald_hw_init();
sbc35_a9g20_nand_hw_init();
#ifdef CONFIG_ATMEL_SPI
at91_spi0_hw_init(1 << 4 | 1 << 5);
@ -166,11 +170,9 @@ int board_init(void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
return -1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
@ -184,7 +186,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
#endif
return rc;
}

55
board/calao/tny_a9260/tny_a9260.c
View file

@ -26,14 +26,12 @@
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@ -45,33 +43,36 @@ DECLARE_GLOBAL_DATA_PTR;
static void tny_a9260_nand_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Assign CS3 to NAND/SmartMedia Interface */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_TDF_(2));
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@ -91,9 +92,9 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
at91_serial_hw_init();
at91_seriald_hw_init();
tny_a9260_nand_hw_init();
at91_spi0_hw_init(1 << 5);
return 0;
@ -101,10 +102,8 @@ int board_init(void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
return -1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}

8
board/cm_t35/cm_t35.c
View file

@ -313,6 +313,14 @@ void set_muxconf_regs(void)
cm_t3730_set_muxconf();
}
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0);
return 0;
}
#endif
/*
* Routine: setup_net_chip_gmpc
* Description: Setting up the configuration GPMC registers specific to the

50
board/cmc_pu2/Makefile
View file

@ -1,50 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

192
board/cmc_pu2/cmc_pu2.c
View file

@ -1,192 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
* (2004) garyj@denx.de
*
* Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mach-types.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#include <netdev.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
#define CMC_HP_BASIC 1
#define CMC_PU2 2
#define CMC_BASIC 4
int hw_detect (void);
int board_init (void)
{
AT91PS_PIO piob = AT91C_BASE_PIOB;
AT91PS_PIO pioc = AT91C_BASE_PIOC;
/* Enable Ctrlc */
console_init_f ();
/* Correct IRDA resistor problem */
/* Set PA23_TXD in Output */
/* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* PIOB and PIOC clock enabling */
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
/*
* configure PC0-PC3 as input without pull ups, so RS485 driver enable
* (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated.
*/
pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
AT91C_PIO_PC2 | AT91C_PIO_PC3;
pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
AT91C_PIO_PC2 | AT91C_PIO_PC3;
pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
AT91C_PIO_PC2 | AT91C_PIO_PC3;
/*
* On CMC-PU2 board configure PB3-PB6 to input without pull ups to
* clear the duo LEDs (the external pull downs assure a proper
* signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and
* drive it high, to configure current measurement on AINx.
*/
if (hw_detect() & CMC_PU2) {
piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
}
else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) {
piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
}
piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
AT91C_PIO_PB5 | AT91C_PIO_PB6;
/*
* arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in
* the linuxarm kernel, yet.
*/
/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
gd->bd->bi_arch_number = 251;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
int checkboard (void)
{
if (hw_detect() & CMC_PU2)
puts ("Board: CMC-PU2 (Rittal GmbH)\n");
else if (hw_detect() & CMC_BASIC)
puts ("Board: CMC-BASIC (Rittal GmbH)\n");
else if (hw_detect() & CMC_HP_BASIC)
puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n");
else
puts ("Board: unknown\n");
return 0;
}
int hw_detect (void)
{
AT91PS_PIO pio = AT91C_BASE_PIOB;
/* PIOB clock enabling */
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
/* configure PB12 as input without pull up */
pio->PIO_ODR = AT91C_PIO_PB12;
pio->PIO_PPUDR = AT91C_PIO_PB12;
pio->PIO_PER = AT91C_PIO_PB12;
/* configure PB13 as input without pull up */
pio->PIO_ODR = AT91C_PIO_PB13;
pio->PIO_PPUDR = AT91C_PIO_PB13;
pio->PIO_PER = AT91C_PIO_PB13;
/* read board identification pin */
if (pio->PIO_PDSR & AT91C_PIO_PB12)
return ((pio->PIO_PDSR & AT91C_PIO_PB13)
? CMC_PU2 : 0);
else
return ((pio->PIO_PDSR & AT91C_PIO_PB13)
? CMC_HP_BASIC : CMC_BASIC);
}
#ifdef CONFIG_DRIVER_ETHER
#if defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

3
board/cmc_pu2/config.mk
View file

@ -1,3 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x20F00000
## For testing: load at 0x20100000 and "go" at 0x201000A4
#CONFIG_SYS_TEXT_BASE = 0x20100000

469
board/cmc_pu2/flash.c
View file

@ -1,469 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
* garyj@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#ifndef CONFIG_ENV_ADDR
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#endif
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x02AA
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_short *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data);
static flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
unsigned long size = 0;
ulong flashbase = CONFIG_SYS_FLASH_BASE;
/* Init: no FLASHes known */
memset(&flash_info[0], 0, sizeof(flash_info_t));
flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]);
size = flash_info[0].size;
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
flash_get_info(CONFIG_ENV_ADDR));
#endif
return size ? size : 1;
}
/*-----------------------------------------------------------------------
*/
static void flash_reset(flash_info_t *info)
{
vu_short *base = (vu_short *)(info->start[0]);
/* Put FLASH back in read mode */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
*base = 0x00FF; /* Intel Read Mode */
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
*base = 0x00F0; /* AMD Read Mode */
}
/*-----------------------------------------------------------------------
*/
static flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
info = NULL;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->size && info->start[0] <= base &&
base <= info->start[0] + info->size - 1)
break;
}
return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_S29GL064M:
printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (vu_short *addr, flash_info_t *info)
{
int i;
ushort value;
ulong base = (ulong)addr;
/* Write auto select command sequence */
addr[FLASH_CYCLE1] = 0x00AA; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE2] = 0x0055; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE1] = 0x0090; /* selects Intel or AMD */
/* read Manufacturer ID */
udelay(100);
value = addr[0];
debug ("Manufacturer ID: %04X\n", value);
switch (value) {
case (AMD_MANUFACT & 0xFFFF):
debug ("Manufacturer: AMD (Spansion)\n");
info->flash_id = FLASH_MAN_AMD;
break;
case (INTEL_MANUFACT & 0xFFFF):
debug ("Manufacturer: Intel (not supported yet)\n");
info->flash_id = FLASH_MAN_INTEL;
break;
default:
printf ("Unknown Manufacturer ID: %04X\n", value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
goto out;
}
value = addr[1];
debug ("Device ID: %04X\n", value);
switch (addr[1]) {
case (AMD_ID_MIRROR & 0xFFFF):
debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n",
addr[14], addr[15]);
switch(addr[14]) {
case (AMD_ID_GL064M_2 & 0xFFFF):
if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
printf ("Chip: S29GLxxxM -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
} else {
debug ("Chip: S29GL064M-R6\n");
info->flash_id += FLASH_S29GL064M;
info->sector_count = 128;
info->size = 0x00800000;
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += 0x10000;
}
}
break; /* => 16 MB */
default:
printf ("Chip: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
break;
default:
printf ("Unknown Device ID: %04X\n", value);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
out:
/* Put FLASH back in read mode */
flash_reset(info);
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_short *addr = (vu_short *)(info->start[0]);
int flag, prot, sect, ssect, l_sect;
ulong now, last, start;
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/*
* Start erase on unprotected sectors.
* Since the flash can erase multiple sectors with one command
* we take advantage of that by doing the erase in chunks of
* 3 sectors.
*/
for (sect = s_first; sect <= s_last; ) {
l_sect = -1;
addr[FLASH_CYCLE1] = 0x00AA;
addr[FLASH_CYCLE2] = 0x0055;
addr[FLASH_CYCLE1] = 0x0080;
addr[FLASH_CYCLE1] = 0x00AA;
addr[FLASH_CYCLE2] = 0x0055;
/* do the erase in chunks of at most 3 sectors */
for (ssect = 0; ssect < 3; ssect++) {
if ((sect + ssect) > s_last)
break;
if (info->protect[sect + ssect] == 0) { /* not protected */
addr = (vu_short *)(info->start[sect + ssect]);
addr[0] = 0x0030;
l_sect = sect + ssect;
}
}
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = 0;
addr = (vu_short *)(info->start[l_sect]);
while ((addr[0] & 0x0080) != 0x0080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
addr = (vu_short *)info->start[0];
addr[0] = 0x00F0; /* reset bank */
sect += ssect;
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
DONE:
/* reset to read mode */
addr = (vu_short *)info->start[0];
addr[0] = 0x00F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong wp, data;
int rc;
if (addr & 1) {
printf ("unaligned destination not supported\n");
return ERR_ALIGN;
};
if ((int) src & 1) {
printf ("unaligned source not supported\n");
return ERR_ALIGN;
};
wp = addr;
while (cnt >= 2) {
data = *((vu_short *)src);
if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 0) {
return (ERR_OK);
}
if (cnt == 1) {
data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8);
if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
return (rc);
}
src += 1;
wp += 1;
cnt -= 1;
}
return ERR_OK;
}
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data)
{
int flag;
vu_short *base; /* first address in flash bank */
ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
base = (vu_short *)(info->start[0]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = 0x00AA; /* unlock */
base[FLASH_CYCLE2] = 0x0055; /* unlock */
base[FLASH_CYCLE1] = 0x00A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer(0);
/* data polling for D7 */
while ((*dest & 0x0080) != (data & 0x0080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = 0x00F0; /* reset bank */
return (1);
}
}
return (0);
}

113
board/cmc_pu2/load_sernum_ethaddr.c
View file

@ -1,113 +0,0 @@
/*
* (C) Copyright 2000, 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* #define DEBUG */
#include <common.h>
#include <net.h>
#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */
#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */
#define I2C_OFFSET 0x0 /* start address of manufacturere data block
* in EEPROM */
/* 64 Byte manufacturer data block in EEPROM */
struct manufacturer_data {
unsigned int serial_number; /* serial number (0...999999) */
unsigned short hardware; /* hardware version (e.g. V1.02) */
unsigned short manuf_date; /* manufacture date (e.g. 25/02) */
unsigned char name[20]; /* device name (in CHIP.INI) */
unsigned char macadr[6]; /* MAC address */
signed char a_kal[4]; /* calibration value for U */
signed char i_kal[4]; /* calibration value for I */
unsigned char reserve[18]; /* reserved */
unsigned short save_nr; /* save count */
unsigned short chksum; /* checksum */
};
int i2c_read (unsigned char chip, unsigned int addr, int alen,
unsigned char *buffer, int len);
/*-----------------------------------------------------------------------
* Process manufacturer data block in EEPROM:
*
* If we boot on a system fresh from factory, check if the manufacturer data
* in the EEPROM is valid and save some information it contains.
*
* CMC manufacturer data is defined as follows:
*
* - located in the onboard EEPROM
* - starts at offset 0x0
* - size 0x00000040
*
* Internal structure: see struct definition
*/
int misc_init_r(void)
{
struct manufacturer_data data;
char serial [9];
unsigned short chksum;
unsigned char *p;
unsigned short i;
#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C)
#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C)
#endif
if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data,
sizeof(data)) != 0) {
puts ("Error reading manufacturer data from EEPROM\n");
return -1;
}
/* check if manufacturer data block is valid */
p = (unsigned char *)&data;
chksum = 0;
for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++)
chksum += *p++;
debug ("checksum of manufacturer data block: %#.4x\n", chksum);
if (chksum != data.chksum) {
puts ("Error: manufacturer data block has invalid checksum\n");
return -1;
}
/* copy serial number */
sprintf (serial, "%d", data.serial_number);
/* set serial# and ethaddr if not yet defined */
if (getenv("serial#") == NULL) {
setenv ("serial#", serial);
}
if (getenv("ethaddr") == NULL) {
eth_setenv_enetaddr("ethaddr", data.macadr);
}
return 0;
}

9
board/comelit/dig297/dig297.c
View file

@ -37,6 +37,7 @@
#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/omap3-regs.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
@ -145,6 +146,14 @@ void set_muxconf_regs(void)
MUX_DIG297();
}
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0);
return 0;
}
#endif
#ifdef CONFIG_CMD_NET
/*
* Routine: setup_net_chip

50
board/csb637/Makefile
View file

@ -1,50 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := csb637.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
board/csb637/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x23fc0000

94
board/csb637/csb637.c
View file

@ -1,94 +0,0 @@
/*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <netdev.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <bcm5221.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* Enable Ctrlc */
console_init_f ();
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of CSB637-Board */
gd->bd->bi_arch_number = MACH_TYPE_CSB637;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_DRIVER_ETHER
#if defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = bcm5221_InitPhy;
p_phyops->IsPhyConnected = bcm5221_IsPhyConnected;
p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed;
p_phyops->AutoNegotiate = bcm5221_AutoNegotiate;
}
#endif
#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
}
#endif

139
board/dave/B2/B2.c
View file

@ -1,139 +0,0 @@
/*
* (C) Copyright 2004
* DAVE Srl
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialization
*/
int board_init (void)
{
u32 temp;
/* Configuration Port Control Register*/
/* Port A */
PCONA = 0x3ff;
/* Port B */
PCONB = 0xff;
PDATB = 0xFFFF;
/* Port C */
/*
PCONC = 0xff55ff15;
PDATC = 0x0;
PUPC = 0xffff;
*/
/* Port D */
/*
PCOND = 0xaaaa;
PUPD = 0xff;
*/
/* Port E */
PCONE = 0x0001aaa9;
PDATE = 0x0;
PUPE = 0xff;
/* Port F */
PCONF = 0x124955;
PDATF = 0xff; /* B2-eth_reset tied high level */
/*
PUPF = 0x1e3;
*/
/* Port G */
PUPG = 0x1;
PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/
INTMSK = 0x03fffeff;
INTCON = 0x05;
/*
Configure chip ethernet interrupt as High level
Port G EINT 0-7 EINT0 -> CHIP ETHERNET
*/
temp = EXTINT;
temp &= ~0x7;
temp |= 0x1; /*LEVEL_HIGH*/
EXTINT = temp;
/*
Reset SMSC LAN91C96 chip
*/
temp= PCONF;
temp |= 0x00000040;
PCONF = temp;
/* Reset high */
temp = PDATF;
temp |= (1 << 3);
PDATF = temp;
/* Short delay */
for (temp=0;temp<10;temp++)
{
/* NOP */
}
/* Reset low */
temp = PDATF;
temp &= ~(1 << 3);
PDATF = temp;
/* arch number MACH_TYPE_MBA44B0 */
gd->bd->bi_arch_number = MACH_TYPE_S3C44B0;
/* location of boot parameters */
gd->bd->bi_boot_params = 0x0c000100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_LAN91C96
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
#endif
return rc;
}
#endif

55
board/dave/B2/Makefile
View file

@ -1,55 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := B2.o flash.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

30
board/dave/B2/config.mk
View file

@ -1,30 +0,0 @@
#
# (C) Copyright 2000
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0x0C100000
PLATFORM_CPPFLAGS += -Uarm

76
board/dave/B2/flash.c
View file

@ -1,76 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/hardware.h>
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
#ifdef __DEBUG_START_FROM_SRAM__
return CONFIG_SYS_DUMMY_FLASH_SIZE;
#else
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (0, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
#endif
}

167
board/dave/B2/lowlevel_init.S
View file

@ -1,167 +0,0 @@
/*
* (C) Copyright 2004
* DAVE Srl
*
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
* Modified By MATTO
*
* Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/*
* Documentation:
* Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
* Advanced Developer's manual, December 1999
*
* Intel has a very hard to find SDRAM configurator on their web site:
* http://appzone.intel.com/hcd/sa1110/memory/index.asp
*
* NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
* appears to be true, but it might be possible that somebody designs a
* board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
*
* 04-10-2001: SELETZ
* - separated memory config for multiple platform support
* - perform SA1110 Hardware Reset Procedure
*
*/
.equ B0_Tacs, 0x0 /* 0clk */
.equ B0_Tcos, 0x0 /* 0clk */
.equ B0_Tacc, 0x4 /* 6clk */
.equ B0_Tcoh, 0x0 /* 0clk */
.equ B0_Tah, 0x0 /* 0clk */
.equ B0_Tacp, 0x0 /* 0clk */
.equ B0_PMC, 0x0 /* normal(1data) */
/* Bank 1 parameter */
.equ B1_Tacs, 0x3 /* 4clk */
.equ B1_Tcos, 0x3 /* 4clk */
.equ B1_Tacc, 0x7 /* 14clkv */
.equ B1_Tcoh, 0x3 /* 4clk */
.equ B1_Tah, 0x3 /* 4clk */
.equ B1_Tacp, 0x3 /* 6clk */
.equ B1_PMC, 0x0 /* normal(1data) */
/* Bank 2 parameter - LAN91C96 */
.equ B2_Tacs, 0x3 /* 4clk */
.equ B2_Tcos, 0x3 /* 4clk */
.equ B2_Tacc, 0x7 /* 14clk */
.equ B2_Tcoh, 0x3 /* 4clk */
.equ B2_Tah, 0x3 /* 4clk */
.equ B2_Tacp, 0x3 /* 6clk */
.equ B2_PMC, 0x0 /* normal(1data) */
/* Bank 3 parameter */
.equ B3_Tacs, 0x3 /* 4clk */
.equ B3_Tcos, 0x3 /* 4clk */
.equ B3_Tacc, 0x7 /* 14clk */
.equ B3_Tcoh, 0x3 /* 4clk */
.equ B3_Tah, 0x3 /* 4clk */
.equ B3_Tacp, 0x3 /* 6clk */
.equ B3_PMC, 0x0 /* normal(1data) */
/* Bank 4 parameter */
.equ B4_Tacs, 0x3 /* 4clk */
.equ B4_Tcos, 0x3 /* 4clk */
.equ B4_Tacc, 0x7 /* 14clk */
.equ B4_Tcoh, 0x3 /* 4clk */
.equ B4_Tah, 0x3 /* 4clk */
.equ B4_Tacp, 0x3 /* 6clk */
.equ B4_PMC, 0x0 /* normal(1data) */
/* Bank 5 parameter */
.equ B5_Tacs, 0x3 /* 4clk */
.equ B5_Tcos, 0x3 /* 4clk */
.equ B5_Tacc, 0x7 /* 14clk */
.equ B5_Tcoh, 0x3 /* 4clk */
.equ B5_Tah, 0x3 /* 4clk */
.equ B5_Tacp, 0x3 /* 6clk */
.equ B5_PMC, 0x0 /* normal(1data) */
/* Bank 6(if SROM) parameter */
.equ B6_Tacs, 0x3 /* 4clk */
.equ B6_Tcos, 0x3 /* 4clk */
.equ B6_Tacc, 0x7 /* 14clk */
.equ B6_Tcoh, 0x3 /* 4clk */
.equ B6_Tah, 0x3 /* 4clk */
.equ B6_Tacp, 0x3 /* 6clk */
.equ B6_PMC, 0x0 /* normal(1data) */
/* Bank 7(if SROM) parameter */
.equ B7_Tacs, 0x3 /* 4clk */
.equ B7_Tcos, 0x3 /* 4clk */
.equ B7_Tacc, 0x7 /* 14clk */
.equ B7_Tcoh, 0x3 /* 4clk */
.equ B7_Tah, 0x3 /* 4clk */
.equ B7_Tacp, 0x3 /* 6clk */
.equ B7_PMC, 0x0 /* normal(1data) */
/* Bank 6 parameter */
.equ B6_MT, 0x3 /* SDRAM */
.equ B6_Trcd, 0x0 /* 2clk */
.equ B6_SCAN, 0x0 /* 10bit */
.equ B7_MT, 0x3 /* SDRAM */
.equ B7_Trcd, 0x0 /* 2clk */
.equ B7_SCAN, 0x0 /* 10bit */
/* REFRESH parameter */
.equ REFEN, 0x1 /* Refresh enable */
.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */
.equ Trp, 0x0 /* 2clk */
.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/
.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */
.equ REFCNT, 879
MEMORY_CONFIG:
.long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
.word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/
.word 0x20 /*MRSR6 CL=2clk*/
.word 0x20 /*MRSR7*/
.globl lowlevel_init
lowlevel_init:
/*
the next instruction fail due memory relocation...
we'll find the right MEMORY_CONFIG address with the next 3 lines...
*/
/*ldr r0, =MEMORY_CONFIG*/
mov r0, pc
ldr r1, =(0x38+4)
sub r0, r0, r1
ldmia r0, {r1-r13}
ldr r0, =0x01c80000
stmia r0, {r1-r13}
mov pc, lr

10
board/davedenx/qong/fpga.c
View file

@ -25,7 +25,7 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <mxc_gpio.h>
#include <asm/gpio.h>
#include <fpga.h>
#include <lattice.h>
#include "qong_fpga.h"
@ -41,22 +41,22 @@ static void qong_jtag_init(void)
static void qong_fpga_jtag_set_tdi(int value)
{
mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
gpio_set_value(QONG_FPGA_TDI_PIN, value);
}
static void qong_fpga_jtag_set_tms(int value)
{
mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
gpio_set_value(QONG_FPGA_TMS_PIN, value);
}
static void qong_fpga_jtag_set_tck(int value)
{
mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
gpio_set_value(QONG_FPGA_TCK_PIN, value);
}
static int qong_fpga_jtag_get_tdo(void)
{
return mxc_gpio_get(QONG_FPGA_TDO_PIN);
return gpio_get_value(QONG_FPGA_TDO_PIN);
}
lattice_board_specific_func qong_fpga_fns = {

36
board/davedenx/qong/qong.c
View file

@ -28,7 +28,7 @@
#include <asm/io.h>
#include <nand.h>
#include <fsl_pmic.h>
#include <mxc_gpio.h>
#include <asm/gpio.h>
#include "qong_fpga.h"
#include <watchdog.h>
@ -51,9 +51,9 @@ int dram_init (void)
static void qong_fpga_reset(void)
{
mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
gpio_set_value(QONG_FPGA_RST_PIN, 0);
udelay(30);
mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
gpio_set_value(QONG_FPGA_RST_PIN, 1);
udelay(300);
}
@ -76,21 +76,20 @@ int board_early_init_f (void)
/* FPGA reset Pin */
/* rstn = 0 */
mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
gpio_direction_output(QONG_FPGA_RST_PIN, 0);
/* set interrupt pin as input */
mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
gpio_direction_input(QONG_FPGA_IRQ_PIN);
/* FPGA JTAG Interface */
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
gpio_direction_input(QONG_FPGA_TDO_PIN);
#endif
/* setup pins for UART1 */
@ -263,27 +262,26 @@ static void board_nand_setup(void)
qong_fpga_reset();
/* Enable NAND flash */
mxc_gpio_set(15, 1);
mxc_gpio_set(14, 1);
mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
mxc_gpio_set(15, 0);
gpio_set_value(15, 1);
gpio_set_value(14, 1);
gpio_direction_output(15, 0);
gpio_direction_input(16);
gpio_direction_input(14);
}
int qong_nand_rdy(void *chip)
{
udelay(1);
return mxc_gpio_get(16);
return gpio_get_value(16);
}
void qong_nand_select_chip(struct mtd_info *mtd, int chip)
{
if (chip >= 0)
mxc_gpio_set(15, 0);
gpio_set_value(15, 0);
else
mxc_gpio_set(15, 1);
gpio_set_value(15, 1);
}

123
board/davinci/da8xxevm/da850evm.c
View file

@ -30,6 +30,7 @@
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <hwconfig.h>
DECLARE_GLOBAL_DATA_PTR;
@ -105,6 +106,57 @@ const struct pinmux_config nand_pins[] = {
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 }
};
#elif defined(CONFIG_USE_NOR)
/* NOR pin muxer settings */
const struct pinmux_config nor_pins[] = {
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
{ pinmux(5), 1, 6 },
{ pinmux(6), 1, 6 },
{ pinmux(7), 1, 0 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(8), 1, 0 },
{ pinmux(8), 1, 1 },
{ pinmux(8), 1, 2 },
{ pinmux(8), 1, 3 },
{ pinmux(8), 1, 4 },
{ pinmux(8), 1, 5 },
{ pinmux(8), 1, 6 },
{ pinmux(8), 1, 7 },
{ pinmux(9), 1, 0 },
{ pinmux(9), 1, 1 },
{ pinmux(9), 1, 2 },
{ pinmux(9), 1, 3 },
{ pinmux(9), 1, 4 },
{ pinmux(9), 1, 5 },
{ pinmux(9), 1, 6 },
{ pinmux(9), 1, 7 },
{ pinmux(10), 1, 0 },
{ pinmux(10), 1, 1 },
{ pinmux(10), 1, 2 },
{ pinmux(10), 1, 3 },
{ pinmux(10), 1, 4 },
{ pinmux(10), 1, 5 },
{ pinmux(10), 1, 6 },
{ pinmux(10), 1, 7 },
{ pinmux(11), 1, 0 },
{ pinmux(11), 1, 1 },
{ pinmux(11), 1, 2 },
{ pinmux(11), 1, 3 },
{ pinmux(11), 1, 4 },
{ pinmux(11), 1, 5 },
{ pinmux(11), 1, 6 },
{ pinmux(11), 1, 7 },
{ pinmux(12), 1, 0 },
{ pinmux(12), 1, 1 },
{ pinmux(12), 1, 2 },
{ pinmux(12), 1, 3 },
{ pinmux(12), 1, 4 },
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 },
{ pinmux(12), 1, 7 }
};
#endif
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
@ -114,6 +166,64 @@ const struct pinmux_config nand_pins[] = {
#endif
#endif /* CONFIG_DRIVER_TI_EMAC */
void dsp_lpsc_on(unsigned domain, unsigned int id)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
struct davinci_psc_regs *psc_regs;
psc_regs = davinci_psc0_regs;
mdstat = &psc_regs->psc0.mdstat[id];
mdctl = &psc_regs->psc0.mdctl[id];
ptstat = &psc_regs->ptstat;
ptcmd = &psc_regs->ptcmd;
while (*ptstat & (0x1 << domain))
;
if ((*mdstat & 0x1f) == 0x03)
return; /* Already on and enabled */
*mdctl |= 0x03;
*ptcmd = 0x1 << domain;
while (*ptstat & (0x1 << domain))
;
while ((*mdstat & 0x1f) != 0x03)
; /* Probably an overkill... */
}
static void dspwake(void)
{
unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
u32 val;
/* if the device is ARM only, return */
if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
return;
if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
return;
*resetvect++ = 0x1E000; /* DSP Idle */
/* clear out the next 10 words as NOP */
memset(resetvect, 0, sizeof(unsigned) *10);
/* setup the DSP reset vector */
writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
val = readl(PSC0_MDCTL + (15 * 4));
val |= 0x100;
writel(val, (PSC0_MDCTL + (15 * 4)));
}
int misc_init_r(void)
{
dspwake();
return 0;
}
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
@ -122,6 +232,8 @@ static const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(i2c_pins),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
#elif defined(CONFIG_USE_NOR)
PINMUX_ITEM(nor_pins),
#endif
};
@ -168,6 +280,7 @@ u32 get_board_rev(void)
int board_init(void)
{
u32 val;
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
@ -215,6 +328,16 @@ int board_init(void)
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */
val = readl(GPIO_BANK0_REG_SET_ADDR);
val |= (0x01 << 11);
writel(val, GPIO_BANK0_REG_CLR_ADDR);
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;

50
board/edb93xx/Makefile
View file

@ -1,50 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

33
board/edb93xx/config.mk
View file

@ -1,33 +0,0 @@
LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
ifdef CONFIG_EDB9301
CONFIG_SYS_TEXT_BASE = 0x05700000
endif
ifdef CONFIG_EDB9302
CONFIG_SYS_TEXT_BASE = 0x05700000
endif
ifdef CONFIG_EDB9302A
CONFIG_SYS_TEXT_BASE = 0xc5700000
endif
ifdef CONFIG_EDB9307
CONFIG_SYS_TEXT_BASE = 0x01f00000
endif
ifdef CONFIG_EDB9307A
CONFIG_SYS_TEXT_BASE = 0xc1f00000
endif
ifdef CONFIG_EDB9312
CONFIG_SYS_TEXT_BASE = 0x01f00000
endif
ifdef CONFIG_EDB9315
CONFIG_SYS_TEXT_BASE = 0x01f00000
endif
ifdef CONFIG_EDB9315A
CONFIG_SYS_TEXT_BASE = 0xc1f00000
endif

110
board/edb93xx/edb93xx.c
View file

@ -1,110 +0,0 @@
/*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* (C) Copyright 2002 2003
* Network Audio Technologies, Inc. <www.netaudiotech.com>
* Adam Bezanson <bezanson@netaudiotech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define MAX_BANK_SIZE 0x04000000 /* 64 MB */
static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = {
PHYS_SDRAM_1,
#ifdef PHYS_SDRAM_2
PHYS_SDRAM_2,
#endif
#ifdef PHYS_SDRAM_3
PHYS_SDRAM_3,
#endif
#ifdef PHYS_SDRAM_4
PHYS_SDRAM_4
#endif
};
int board_init(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
icache_enable();
#ifdef USE_920T_MMU
dcache_enable();
#endif
/*
* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
* 14.7456/2 MHz
*/
uint32_t value = readl(&syscon->pwrcnt);
value |= SYSCON_PWRCNT_UART_BAUD;
writel(value, &syscon->pwrcnt);
/* Enable the uart in devicecfg */
value = readl(&syscon->devicecfg);
value |= 1<<18 /* U1EN */;
writel(0xAA, &syscon->sysswlock);
writel(value, &syscon->devicecfg);
/* Machine number, as defined in linux/arch/arm/tools/mach-types */
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* adress of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* We have a console */
gd->have_console = 1;
return 0;
}
int board_eth_init(bd_t *bd)
{
return ep93xx_eth_initialize(0, MAC_BASE);
}
int dram_init(void)
{
unsigned int *src, *dst;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
const ulong bank_size = get_ram_size((long *)bank_addr[i],
MAX_BANK_SIZE);
if (bank_size) {
gd->bd->bi_dram[i].start = bank_addr[i];
gd->bd->bi_dram[i].size = bank_size;
}
}
/* copy exception vectors */
src = (unsigned int *)_armboot_start;
dst = (unsigned int *)PHYS_SDRAM_1;
memcpy(dst, src, 16 * sizeof(unsigned int));
return 0;
}

58
board/edb93xx/pll_cfg.c
View file

@ -1,58 +0,0 @@
/*
* PLL setup for Cirrus edb93xx boards
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include "pll_cfg.h"
#include "early_udelay.h"
void pll_cfg(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
/* setup PLL1 */
writel(CLKSET1_VAL, &syscon->clkset1);
/*
* flush the pipeline
* writing to CLKSET1 causes the EP93xx to enter standby for between
* 8 ms to 16 ms, until PLL1 stabilizes
*/
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
/* setup PLL2 */
writel(CLKSET2_VAL, &syscon->clkset2);
/*
* the user's guide recommends to wait at least 1 ms for PLL2 to
* stabilize
*/
early_udelay(1000);
}

72
board/edb93xx/pll_cfg.h
View file

@ -1,72 +0,0 @@
/*
* PLL register values for Cirrus edb93xx boards
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/ep93xx.h>
#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
defined(CONFIG_EDB9302A)
/*
* fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
* pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
* pll1_x2: 331776000.000000, pll1_out: 331776000.000000
*/
#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
SYSCON_CLKSET1_NBYP1 | \
1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
defined(CONFIG_EDB9315A)
/*
* fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
* pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
* pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
*/
#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
SYSCON_CLKSET1_NBYP1 | \
1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
#else
#error "Undefined board"
#endif
/*
* usb_div: 4, nbyp2: 1, pll2_en: 1
* pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
* pll2_x2: 384000000.000000, pll2_out: 192000000.000000
*/
#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
SYSCON_CLKSET2_PLL2_EN | \
SYSCON_CLKSET2_NBYP2 | \
3 << SYSCON_CLKSET2_USB_DIV_SHIFT)

146
board/edb93xx/sdram_cfg.c
View file

@ -1,146 +0,0 @@
/*
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/io.h>
#include "sdram_cfg.h"
#include "early_udelay.h"
#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
static void precharge_all_banks(void);
static void setup_refresh_timer(void);
static void program_mode_registers(void);
void sdram_cfg(void)
{
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
/* Issue continous NOP commands */
writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
early_udelay(200);
precharge_all_banks();
setup_refresh_timer();
program_mode_registers();
/* Select normal operation mode */
writel(GLCONFIG_CKE, &sdram->glconfig);
}
static void precharge_all_banks(void)
{
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
/* Issue PRECHARGE ALL commands */
writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
/*
* Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
* issued
*
* Cirrus proposes a workaround which consists in performing a read from
* each bank to force the precharge. This causes some boards to hang.
* Writing to the SDRAM banks instead of reading has the same
* side-effect (the SDRAM controller issues the necessary precharges),
* but is known to work on all supported boards
*/
PRECHARGE_BANK(0);
#if (CONFIG_NR_DRAM_BANKS >= 2)
PRECHARGE_BANK(1);
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
PRECHARGE_BANK(2);
#endif
#if (CONFIG_NR_DRAM_BANKS == 4)
PRECHARGE_BANK(3);
#endif
}
static void setup_refresh_timer(void)
{
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
/* Load refresh timer with 10 to issue refresh every 10 cycles */
writel(0x0a, &sdram->refrshtimr);
/*
* Wait at least 80 clock cycles to provide 8 refresh cycles
* to all SDRAMs
*/
early_udelay(1);
/*
* Program refresh timer with normal value
* We need 8192 refresh cycles every 64ms
* at 15ns (HCLK >= 66MHz) per cycle:
* 64ms / 8192 = 7.8125us
* 7.8125us / 15ns = 520 (0x208)
*/
/*
* TODO: redboot uses 0x1e0 for the slowest possible device
* but i don't understand how this value is calculated
*/
writel(0x208, &sdram->refrshtimr);
}
static void program_mode_registers(void)
{
struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
/* Select mode register update mode */
writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
/*
* The mode registers are programmed by performing a read from each
* SDRAM bank. The value of the address that is read defines the value
* that is written into the mode register
*/
PROGRAM_MODE_REG(0);
#if (CONFIG_NR_DRAM_BANKS >= 2)
PROGRAM_MODE_REG(1);
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
PROGRAM_MODE_REG(2);
#endif
#if (CONFIG_NR_DRAM_BANKS == 4)
PROGRAM_MODE_REG(3);
#endif
}

144
board/edb93xx/sdram_cfg.h
View file

@ -1,144 +0,0 @@
/*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/ep93xx.h>
#define SDRAM_BASE_ADDR PHYS_SDRAM_1
#ifdef CONFIG_EDB93XX_SDCS0
#define SDRAM_DEVCFG_REG devcfg0
#elif defined(CONFIG_EDB93XX_SDCS3)
#define SDRAM_DEVCFG_REG devcfg3
#else
#error "SDRAM bank configuration"
#endif
#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
defined(CONFIG_EDB9302A)
/*
* 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
*
* CLK cycle time min:
* @ CAS latency = 3: 7.5ns
* @ CAS latency = 2: 10ns
* We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
* so it's safe to use CAS latency = 2
*
* RAS-to-CAS delay min:
* 20ns
* At 15ns cycle time, we use RAS-to-CAS delay = 2
*
* SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
* as four blocks of 8MB size, instead of eight blocks of 4MB size:
*
* EDB9301/EDB9302:
*
* 0x00000000 - 0x007fffff
* 0x01000000 - 0x017fffff
* 0x04000000 - 0x047fffff
* 0x05000000 - 0x057fffff
*
*
* EDB9302a:
*
* 0xc0000000 - 0xc07fffff
* 0xc1000000 - 0xc17fffff
* 0xc4000000 - 0xc47fffff
* 0xc5000000 - 0xc57fffff
*
* BANKCOUNT = 1: This is a device with four banks
*/
#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
SDRAM_DEVCFG_SROMLL | \
SDRAM_DEVCFG_CASLAT_2 | \
SDRAM_DEVCFG_RASTOCAS_2 | \
SDRAM_DEVCFG_EXTBUSWIDTH)
/*
* 16 bit ext. bus
*
* A[22:09] is output as SYA[13:0]
* CAS latency: 2
* Burst type: sequential
* Burst length: 8 (required for 16 bit ext. bus)
* SYA[13:0] = 0x0023
*/
#define SDRAM_MODE_REG_VAL 0x4600
#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
defined(CONFIG_EDB9315A)
/*
* 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
*
* CLK cycle time min:
* @ CAS latency = 3: 7.5ns
* @ CAS latency = 2: 10ns
* We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
* so it's safe to use CAS latency = 2
*
* RAS-to-CAS delay min:
* 20ns
* At 10ns cycle time, we use RAS-to-CAS delay = 2
*
* EDB9307, EDB9312, EDB9315:
*
* 0x00000000 - 0x01ffffff
* 0x04000000 - 0x05ffffff
*
*
* EDB9307a, EDB9315a:
*
* 0xc0000000 - 0xc1ffffff
* 0xc4000000 - 0xc5ffffff
*/
#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
SDRAM_DEVCFG_SROMLL | \
SDRAM_DEVCFG_CASLAT_2 | \
SDRAM_DEVCFG_RASTOCAS_2)
/*
* 32 bit ext. bus
*
* A[23:10] is output as SYA[13:0]
* CAS latency: 2
* Burst type: sequential
* Burst length: 4
* SYA[13:0] = 0x0022
*/
#define SDRAM_MODE_REG_VAL 0x8800
#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
#endif

62
board/efikamx/efikamx.c
View file

@ -27,7 +27,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <mxc_gpio.h>
#include <asm/gpio.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
@ -76,28 +76,23 @@ u32 get_efika_rev(void)
* rev1.4: 1,0,0
*/
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
MXC_GPIO_DIRECTION_OUT);
/* set to 1 in order to get correct value on board rev1.1 */
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0),
MXC_GPIO_DIRECTION_IN);
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1),
MXC_GPIO_DIRECTION_IN);
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3),
MXC_GPIO_DIRECTION_IN);
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
return (~rev & 0x7) + 1;
}
@ -154,15 +149,11 @@ static void setup_iomux_spi(void)
/* Configure SS0 as a GPIO */
mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
MXC_GPIO_DIRECTION_OUT);
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
/* Configure SS1 as a GPIO */
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
MXC_GPIO_DIRECTION_OUT);
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
@ -282,9 +273,9 @@ int board_mmc_getcd(u8 *absent, struct mmc *mmc)
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
*absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
else
*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
*absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
return 0;
}
@ -307,10 +298,8 @@ int board_mmc_init(bd_t *bis)
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_SRE_FAST);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0),
MXC_GPIO_DIRECTION_IN);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1),
MXC_GPIO_DIRECTION_IN);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
@ -389,10 +378,8 @@ int board_mmc_init(bd_t *bis)
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_SRE_FAST);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8),
MXC_GPIO_DIRECTION_IN);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7),
MXC_GPIO_DIRECTION_IN);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
if (!ret)
@ -508,25 +495,24 @@ void setup_iomux_led(void)
{
/* Blue LED */
mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
MXC_GPIO_DIRECTION_OUT);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
/* Green LED */
mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
MXC_GPIO_DIRECTION_OUT);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
/* Red LED */
mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
MXC_GPIO_DIRECTION_OUT);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
}
void efikamx_toggle_led(uint32_t mask)
{
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
mask & EFIKAMX_LED_BLUE);
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
mask & EFIKAMX_LED_GREEN);
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
mask & EFIKAMX_LED_RED);
}

1
board/esd/meesc/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x21f00000

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