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am33xx: refactor emif4/ddr to support multiple EMIF instances

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The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Matt Porter 2013-03-15 10:07:03 +00:00 committed by Tom Rini
parent 81df2bab46
commit 3ba65f97cb
6 changed files with 144 additions and 76 deletions
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107
arch/arm/cpu/armv7/am33xx/ddr.c
View file

@ -24,15 +24,20 @@ http://www.ti.com/
/**
* Base address for EMIF instances
*/
static struct emif_reg_struct *emif_reg = {
(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
static struct emif_reg_struct *emif_reg[2] = {
(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
/**
* Base address for DDR instance
* Base addresses for DDR PHY cmd/data regs
*/
static struct ddr_regs *ddr_reg[2] = {
(struct ddr_regs *)DDR_PHY_BASE_ADDR,
(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
static struct ddr_data_regs *ddr_data_reg[2] = {
(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
/**
* Base address for ddr io control instances
@ -43,7 +48,7 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
/**
* Configure SDRAM
*/
void config_sdram(const struct emif_regs *regs)
void config_sdram(const struct emif_regs *regs, int nr)
{
if (regs->zq_config) {
/*
@ -51,71 +56,85 @@ void config_sdram(const struct emif_regs *regs)
* about 570us for a delay, which will be long enough
* to configure things.
*/
writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg->emif_zq_config);
writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}
/**
* Set SDRAM timings
*/
void set_sdram_timings(const struct emif_regs *regs)
void set_sdram_timings(const struct emif_regs *regs, int nr)
{
writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
/**
* Configure DDR PHY
*/
void config_ddr_phy(const struct emif_regs *regs)
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
}
/**
* Configure DDR CMD control registers
*/
void config_cmd_ctrl(const struct cmd_control *cmd)
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}
/**
* Configure DDR DATA registers
*/
void config_ddr_data(int macrono, const struct ddr_data *data)
void config_ddr_data(const struct ddr_data *data, int nr)
{
writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
int i;
for (i = 0; i < DDR_DATA_REGS_NR; i++) {
writel(data->datardsratio0,
&(ddr_data_reg[nr]+i)->dt0rdsratio0);
writel(data->datawdsratio0,
&(ddr_data_reg[nr]+i)->dt0wdsratio0);
writel(data->datawiratio0,
&(ddr_data_reg[nr]+i)->dt0wiratio0);
writel(data->datagiratio0,
&(ddr_data_reg[nr]+i)->dt0giratio0);
writel(data->datafwsratio0,
&(ddr_data_reg[nr]+i)->dt0fwsratio0);
writel(data->datawrsratio0,
&(ddr_data_reg[nr]+i)->dt0wrsratio0);
writel(data->datauserank0delay,
&(ddr_data_reg[nr]+i)->dt0rdelays0);
writel(data->datadldiff0,
&(ddr_data_reg[nr]+i)->dt0dldiff0);
}
}
void config_io_ctrl(unsigned long val)

40
arch/arm/cpu/armv7/am33xx/emif4.c
View file

@ -44,44 +44,48 @@ void dram_init_banksize(void)
#ifdef CONFIG_SPL_BUILD
static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
static struct vtp_reg *vtpreg[2] = {
(struct vtp_reg *)VTP0_CTRL_ADDR,
(struct vtp_reg *)VTP1_CTRL_ADDR};
#ifdef CONFIG_AM33XX
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
#endif
static void config_vtp(void)
static void config_vtp(int nr)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
&vtpreg->vtp0ctrlreg);
writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
&vtpreg->vtp0ctrlreg);
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
&vtpreg->vtp0ctrlreg);
writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
&vtpreg[nr]->vtp0ctrlreg);
writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
&vtpreg[nr]->vtp0ctrlreg);
writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
&vtpreg[nr]->vtp0ctrlreg);
/* Poll for READY */
while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
VTP_CTRL_READY)
;
}
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs)
const struct emif_regs *regs, int nr)
{
enable_emif_clocks();
ddr_pll_config(pll);
config_vtp();
config_cmd_ctrl(ctrl);
config_ddr_data(0, data);
config_ddr_data(1, data);
config_vtp(nr);
config_cmd_ctrl(ctrl, nr);
config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
config_io_ctrl(ioctrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
#endif
/* Program EMIF instance */
config_ddr_phy(regs);
set_sdram_timings(regs);
config_sdram(regs);
config_ddr_phy(regs, nr);
set_sdram_timings(regs, nr);
config_sdram(regs, nr);
}
#endif

52
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View file

@ -103,17 +103,57 @@
/**
* Configure SDRAM
*/
void config_sdram(const struct emif_regs *regs);
void config_sdram(const struct emif_regs *regs, int nr);
/**
* Set SDRAM timings
*/
void set_sdram_timings(const struct emif_regs *regs);
void set_sdram_timings(const struct emif_regs *regs, int nr);
/**
* Configure DDR PHY
*/
void config_ddr_phy(const struct emif_regs *regs);
void config_ddr_phy(const struct emif_regs *regs, int nr);
struct ddr_cmd_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv1[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv2[8];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv3[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv4[8];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv5[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv6[3];
};
struct ddr_data_regs {
unsigned int dt0rdsratio0; /* offset 0x0C8 */
unsigned int resv1[4];
unsigned int dt0wdsratio0; /* offset 0x0DC */
unsigned int resv2[4];
unsigned int dt0wiratio0; /* offset 0x0F0 */
unsigned int resv3;
unsigned int dt0wimode0; /* offset 0x0F8 */
unsigned int dt0giratio0; /* offset 0x0FC */
unsigned int resv4;
unsigned int dt0gimode0; /* offset 0x104 */
unsigned int dt0fwsratio0; /* offset 0x108 */
unsigned int resv5[4];
unsigned int dt0dqoffset; /* offset 0x11C */
unsigned int dt0wrsratio0; /* offset 0x120 */
unsigned int resv6[4];
unsigned int dt0rdelays0; /* offset 0x134 */
unsigned int dt0dldiff0; /* offset 0x138 */
unsigned int resv7[12];
};
/**
* This structure represents the DDR registers on AM33XX devices.
@ -194,12 +234,12 @@ struct ddr_data {
/**
* Configure DDR CMD control registers
*/
void config_cmd_ctrl(const struct cmd_control *cmd);
void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
/**
* Configure DDR DATA registers
*/
void config_ddr_data(int data_macrono, const struct ddr_data *data);
void config_ddr_data(const struct ddr_data *data, int nr);
/**
* This structure represents the DDR io control on AM33XX devices.
@ -227,6 +267,6 @@ struct ddr_ctrl {
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs);
const struct emif_regs *regs, int nr);
#endif /* _DDR_DEFS_H */

13
arch/arm/include/asm/arch-am33xx/hardware.h
View file

@ -3,7 +3,7 @@
*
* hardware specific header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -20,6 +20,11 @@
#define __AM33XX_HARDWARE_H
#include <asm/arch/omap.h>
#ifdef CONFIG_AM33XX
#include <asm/arch/hardware_am33xx.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/hardware_ti814x.h>
#endif
/* Module base addresses */
#define UART0_BASE 0x44E09000
@ -66,13 +71,13 @@
#define PRM_DEVICE 0x44E00F00
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
/* DDR Base address */
#define DDR_CTRL_ADDR 0x44E10E04
#define DDR_CONTROL_BASE_ADDR 0x44E11404
#define DDR_PHY_BASE_ADDR 0x44E12000
#define DDR_PHY_BASE_ADDR2 0x44E120A4
#define DDR_PHY_CMD_ADDR2 0x47C0C800
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
/* UART */
#define DEFAULT_UART_BASE UART0_BASE

2
board/phytec/pcm051/board.c
View file

@ -159,7 +159,7 @@ void s_init(void)
enable_board_pin_mux();
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}

6
board/ti/am335x/board.c
View file

@ -345,13 +345,13 @@ void s_init(void)
if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_evm_15_or_later())
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
#endif
}