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https://github.com/AsahiLinux/u-boot
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ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform. PLL and pinmux configurations for mmc/sd are configured in this patch. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Chandan Nath
Albert ARIBAUD
parent
750b4bfe10
commit
876bdd6d46
5 changed files with 205 additions and 0 deletions
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@ -64,3 +64,10 @@ void init_timer(void)
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/* Start the Timer */
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writel(0x1, (&timer_base->tclr));
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}
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#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0);
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}
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#endif
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@ -108,6 +108,11 @@ static void enable_per_clocks(void)
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writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
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while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
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;
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/* MMC0*/
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writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
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while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
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;
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}
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static void mpu_pll_config(void)
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164
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
Normal file
164
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
Normal file
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@ -0,0 +1,164 @@
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/*
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* mmc_host_def.h
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MMC_HOST_DEF_H
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#define MMC_HOST_DEF_H
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/*
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* OMAP HSMMC register definitions
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*/
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#define OMAP_HSMMC1_BASE 0x48060100
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#define OMAP_HSMMC2_BASE 0x481D8000
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#define OMAP_HSMMC3_BASE 0x47C24000
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typedef struct hsmmc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned char res2[0x14];
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unsigned int con; /* 0x2C */
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unsigned char res3[0xD4];
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unsigned int blk; /* 0x104 */
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unsigned int arg; /* 0x108 */
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unsigned int cmd; /* 0x10C */
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unsigned int rsp10; /* 0x110 */
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unsigned int rsp32; /* 0x114 */
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unsigned int rsp54; /* 0x118 */
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unsigned int rsp76; /* 0x11C */
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unsigned int data; /* 0x120 */
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unsigned int pstate; /* 0x124 */
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unsigned int hctl; /* 0x128 */
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unsigned int sysctl; /* 0x12C */
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unsigned int stat; /* 0x130 */
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unsigned int ie; /* 0x134 */
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unsigned char res4[0x8];
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unsigned int capa; /* 0x140 */
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} hsmmc_t;
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/*
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* OMAP HS MMC Bit definitions
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*/
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#define MMC_SOFTRESET (0x1 << 1)
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#define RESETDONE (0x1 << 0)
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#define NOOPENDRAIN (0x0 << 0)
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#define OPENDRAIN (0x1 << 0)
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#define OD (0x1 << 0)
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#define INIT_NOINIT (0x0 << 1)
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#define INIT_INITSTREAM (0x1 << 1)
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#define HR_NOHOSTRESP (0x0 << 2)
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#define STR_BLOCK (0x0 << 3)
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#define MODE_FUNC (0x0 << 4)
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#define DW8_1_4BITMODE (0x0 << 5)
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#define MIT_CTO (0x0 << 6)
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#define CDP_ACTIVEHIGH (0x0 << 7)
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#define WPP_ACTIVEHIGH (0x0 << 8)
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#define RESERVED_MASK (0x3 << 9)
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#define CTPL_MMC_SD (0x0 << 11)
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#define BLEN_512BYTESLEN (0x200 << 0)
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#define NBLK_STPCNT (0x0 << 16)
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#define DE_DISABLE (0x0 << 0)
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#define BCE_DISABLE (0x0 << 1)
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#define BCE_ENABLE (0x1 << 1)
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#define ACEN_DISABLE (0x0 << 2)
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#define DDIR_OFFSET (4)
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#define DDIR_MASK (0x1 << 4)
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#define DDIR_WRITE (0x0 << 4)
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#define DDIR_READ (0x1 << 4)
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#define MSBS_SGLEBLK (0x0 << 5)
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#define MSBS_MULTIBLK (0x1 << 5)
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#define RSP_TYPE_OFFSET (16)
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#define RSP_TYPE_MASK (0x3 << 16)
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#define RSP_TYPE_NORSP (0x0 << 16)
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#define RSP_TYPE_LGHT136 (0x1 << 16)
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#define RSP_TYPE_LGHT48 (0x2 << 16)
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#define RSP_TYPE_LGHT48B (0x3 << 16)
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#define CCCE_NOCHECK (0x0 << 19)
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#define CCCE_CHECK (0x1 << 19)
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#define CICE_NOCHECK (0x0 << 20)
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#define CICE_CHECK (0x1 << 20)
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#define DP_OFFSET (21)
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#define DP_MASK (0x1 << 21)
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#define DP_NO_DATA (0x0 << 21)
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#define DP_DATA (0x1 << 21)
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#define CMD_TYPE_NORMAL (0x0 << 22)
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#define INDEX_OFFSET (24)
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#define INDEX_MASK (0x3f << 24)
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#define INDEX(i) (i << 24)
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#define DATI_MASK (0x1 << 1)
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#define DATI_CMDDIS (0x1 << 1)
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#define DTW_1_BITMODE (0x0 << 1)
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#define DTW_4_BITMODE (0x1 << 1)
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#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
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#define SDBP_PWROFF (0x0 << 8)
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#define SDBP_PWRON (0x1 << 8)
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#define SDVS_1V8 (0x5 << 9)
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#define SDVS_3V0 (0x6 << 9)
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#define ICE_MASK (0x1 << 0)
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#define ICE_STOP (0x0 << 0)
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#define ICS_MASK (0x1 << 1)
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#define ICS_NOTREADY (0x0 << 1)
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#define ICE_OSCILLATE (0x1 << 0)
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#define CEN_MASK (0x1 << 2)
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#define CEN_DISABLE (0x0 << 2)
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#define CEN_ENABLE (0x1 << 2)
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#define CLKD_OFFSET (6)
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#define CLKD_MASK (0x3FF << 6)
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#define DTO_MASK (0xF << 16)
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#define DTO_15THDTO (0xE << 16)
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#define SOFTRESETALL (0x1 << 24)
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#define CC_MASK (0x1 << 0)
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#define TC_MASK (0x1 << 1)
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#define BWR_MASK (0x1 << 4)
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#define BRR_MASK (0x1 << 5)
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#define ERRI_MASK (0x1 << 15)
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#define IE_CC (0x01 << 0)
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#define IE_TC (0x01 << 1)
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#define IE_BWR (0x01 << 4)
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#define IE_BRR (0x01 << 5)
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#define IE_CTO (0x01 << 16)
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#define IE_CCRC (0x01 << 17)
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#define IE_CEB (0x01 << 18)
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#define IE_CIE (0x01 << 19)
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#define IE_DTO (0x01 << 20)
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#define IE_DCRC (0x01 << 21)
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#define IE_DEB (0x01 << 22)
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#define IE_CERR (0x01 << 28)
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#define IE_BADA (0x01 << 29)
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#define VS30_3V0SUP (1 << 25)
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#define VS18_1V8SUP (1 << 26)
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/* Driver definitions */
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#define MMCSD_SECTOR_SIZE 512
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#define MMC_CARD 0
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#define SD_CARD 1
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#define BYTE_MODE 0
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#define SECTOR_MODE 1
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#define CLK_INITSEQ 0
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#define CLK_400KHZ 1
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#define CLK_MISC 2
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#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
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#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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/* Clock Configurations and Macros */
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#define MMC_CLOCK_REFERENCE 96 /* MHz */
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#define mmc_reg_out(addr, mask, val)\
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writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
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int omap_mmc_init(int dev_index);
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#endif /* MMC_HOST_DEF_H */
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@ -258,6 +258,20 @@ static struct module_pin_mux uart0_pin_mux[] = {
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{-1},
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};
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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{-1},
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};
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#endif
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/*
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* Configure the pin mux for the module
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*/
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@ -276,3 +290,10 @@ void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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#ifdef CONFIG_MMC
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void enable_mmc0_pin_mux(void)
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{
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configure_module_pin_mux(mmc0_pin_mux);
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}
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#endif
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@ -76,6 +76,14 @@
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#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
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#define CONFIG_SYS_HZ 1000 /* 1ms clock */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_CMD_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
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