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EXYNOS5: Add pinmux support for SPI
This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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2 changed files with 56 additions and 0 deletions
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@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
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s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
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s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
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}
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return 0;
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}
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@ -240,6 +241,49 @@ static void exynos5_i2s_config(int peripheral)
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s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
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}
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void exynos5_spi_config(int peripheral)
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{
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int cfg = 0, pin = 0, i;
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struct s5p_gpio_bank *bank = NULL;
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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struct exynos5_gpio_part2 *gpio2 =
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(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
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switch (peripheral) {
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case PERIPH_ID_SPI0:
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bank = &gpio1->a2;
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cfg = GPIO_FUNC(0x2);
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pin = 0;
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break;
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case PERIPH_ID_SPI1:
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bank = &gpio1->a2;
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cfg = GPIO_FUNC(0x2);
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pin = 4;
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break;
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case PERIPH_ID_SPI2:
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bank = &gpio1->b1;
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cfg = GPIO_FUNC(0x5);
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pin = 1;
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break;
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case PERIPH_ID_SPI3:
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bank = &gpio2->f1;
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cfg = GPIO_FUNC(0x2);
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pin = 0;
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break;
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case PERIPH_ID_SPI4:
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for (i = 0; i < 2; i++) {
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s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
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s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
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}
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break;
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}
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if (peripheral != PERIPH_ID_SPI4) {
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for (i = pin; i < pin + 4; i++)
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s5p_gpio_cfg_pin(bank, i, cfg);
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}
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}
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static int exynos5_pinmux_config(int peripheral, int flags)
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{
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switch (peripheral) {
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@ -270,6 +314,13 @@ static int exynos5_pinmux_config(int peripheral, int flags)
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case PERIPH_ID_I2S1:
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exynos5_i2s_config(peripheral);
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break;
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case PERIPH_ID_SPI0:
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case PERIPH_ID_SPI1:
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case PERIPH_ID_SPI2:
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case PERIPH_ID_SPI3:
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case PERIPH_ID_SPI4:
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exynos5_spi_config(peripheral);
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break;
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default:
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debug("%s: invalid peripheral %d", __func__, peripheral);
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return -1;
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@ -45,6 +45,11 @@ enum periph_id {
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PERIPH_ID_SDMMC3,
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PERIPH_ID_SDMMC4,
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PERIPH_ID_SROMC,
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PERIPH_ID_SPI0,
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PERIPH_ID_SPI1,
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PERIPH_ID_SPI2,
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PERIPH_ID_SPI3,
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PERIPH_ID_SPI4,
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PERIPH_ID_UART0,
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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