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DaVinci DA850: UART2 clock ID comes from ASYNC3

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On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
This commit is contained in:
Laurence Withers 2012-07-30 23:30:35 +00:00 committed by Albert ARIBAUD
parent 8a54aa0da7
commit 88ac6b9d14
1 changed files with 3 additions and 1 deletions
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4
arch/arm/include/asm/arch-davinci/hardware.h
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@ -467,7 +467,6 @@ enum davinci_clk_ids {
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
/* special clock ID - output of PLL multiplier */
DAVINCI_PLLM_CLKID = 0x0FF,
@ -479,6 +478,9 @@ enum davinci_clk_ids {
DAVINCI_AUXCLK_CLKID = 0x101,
};
#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
: get_async3_src())
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
: get_async3_src())