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am33xx: CPSW init and definitions

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This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This commit is contained in:
Chandan Nath 2012-07-24 12:22:17 +00:00 committed by Albert ARIBAUD
parent 2b62997ce9
commit e79cd8eb9b
3 changed files with 23 additions and 1 deletions
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8
arch/arm/cpu/armv7/am33xx/clock.c
View file

@ -24,6 +24,7 @@
#define PRCM_MOD_EN 0x2
#define PRCM_FORCE_WAKEUP 0x2
#define PRCM_FUNCTL 0x0
#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
#define PRCM_L3_GCLK_ACTIVITY BIT(4)
@ -38,7 +39,7 @@
#define CLK_MODE_SEL 0x7
#define CLK_MODE_MASK 0xfffffff8
#define CLK_DIV_SEL 0xFFFFFFE0
#define CPGMAC0_IDLE 0x30000
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@ -138,6 +139,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
;
/* Ethernet */
writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
;
}
static void mpu_pll_config(void)

11
arch/arm/include/asm/arch-am33xx/cpu.h
View file

@ -255,6 +255,17 @@ struct ctrl_stat {
#define OMAP_GPIO_CLEARDATAOUT 0x0190
#define OMAP_GPIO_SETDATAOUT 0x0194
/* Control Device Register */
struct ctrl_dev {
unsigned int deviceid; /* offset 0x00 */
unsigned int resv1[11];
unsigned int macid0l; /* offset 0x30 */
unsigned int macid0h; /* offset 0x34 */
unsigned int macid1l; /* offset 0x38 */
unsigned int macid1h; /* offset 0x3c */
unsigned int resv2[4];
unsigned int miisel; /* offset 0x50 */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

5
arch/arm/include/asm/arch-am33xx/hardware.h
View file

@ -46,6 +46,7 @@
/* Control Module Base Address */
#define CTRL_BASE 0x44E10000
#define CTRL_DEVICE_BASE 0x44E10600
/* PRCM Base Address */
#define PRCM_BASE 0x44E00000
@ -78,4 +79,8 @@
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
/* CPSW Config space */
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
#endif /* __AM33XX_HARDWARE_H */