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ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
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commit
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4 changed files with 21 additions and 11 deletions
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@ -204,17 +204,22 @@ void init_omap_revision(void)
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*/
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unsigned int rev = cortex_rev();
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switch (rev) {
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case MIDR_CORTEX_A15_R0P0:
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP5430_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5430_ES1_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES1_0:
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default:
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*omap_si_rev = OMAP5432_ES1_0;
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break;
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}
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP5430_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5430_ES1_0;
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if (rev == MIDR_CORTEX_A15_R2P2)
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*omap_si_rev = OMAP5430_ES2_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5432_ES1_0;
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if (rev == MIDR_CORTEX_A15_R2P2)
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*omap_si_rev = OMAP5432_ES2_0;
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break;
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case OMAP5430_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP5430_ES2_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP5432_ES2_0;
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break;
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default:
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*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
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@ -57,7 +57,9 @@
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/* To be verified */
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#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
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#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
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#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
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#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
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/* STD_FUSE_PROD_ID_1 */
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#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
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@ -33,6 +33,7 @@
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/* Cortex-A15 revisions */
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#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
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#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
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/* CCSIDR */
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#define CCSIDR_LINE_SIZE_OFFSET 0
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@ -542,4 +542,6 @@ static inline u32 omap_revision(void)
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#define OMAP5430_SILICON_ID_INVALID 0
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#define OMAP5430_ES1_0 0x54300100
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#define OMAP5432_ES1_0 0x54320100
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#define OMAP5430_ES2_0 0x54300200
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#define OMAP5432_ES2_0 0x54320200
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#endif /* _OMAP_COMMON_H_ */
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