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Merge branch 'master' of git://git.denx.de/u-boot-video

Browse source 
* 'master' of git://git.denx.de/u-boot-video:
  video: atmel/lcd: add LCD driver for new Atmel SoC
  video: cfb_console: flush dcache for frame buffer in DRAM
  cfb_console: Ignore bell character
  cfb_console: Add console_clear_line function
  cfb_console: Fix function console_back
  omap3_dss: cosmetic changes
  omap3_dss: add optional framebuffer
  mx53loco: Add LCD support
  mx5: Rename mx51_fb_init()
  mx53: Allow IPUv3 driver to also work on mx53
  mx51evk: Add LCD support
  EXYNOS: display 32bpp bitmap TIZEN logo
  create lib/tizen directory
  LCD: display 32bpp decompressed bitmap image
  common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
  common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
  common/lcd.c: use ARRAY_SIZE
  cmd_bmp.c: make bmp_display() usable by drivers or board code
  LCD: support another s6e8ax0 panel type
  LCD: change s6e8ax0 panel gamma value
  include/video.h: drop unused video_printf()

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2012-06-07 23:42:17 +02:00
commit fedab338f3
32 changed files with 6123 additions and 122 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
Makefile
View file

@ -229,6 +229,9 @@ LIBS = lib/libgeneric.o
LIBS += lib/lzma/liblzma.o
LIBS += lib/lzo/liblzo.o
LIBS += lib/zlib/libz.o
ifeq ($(CONFIG_TIZEN),y)
LIBS += lib/tizen/libtizen.o
endif
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
"board/$(VENDOR)/common/lib$(VENDOR).o"; fi)
LIBS += $(CPUDIR)/lib$(CPU).o

1
arch/arm/include/asm/arch-exynos/mipi_dsim.h
View file

@ -329,6 +329,7 @@ struct mipi_dsim_lcd_device {
char *name;
int id;
int bus_id;
int reverse_panel;
struct mipi_dsim_device *master;
void *platform_data;

8
arch/arm/include/asm/arch-mx5/imx-regs.h
View file

@ -25,7 +25,8 @@
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_CTRL_BASE_ADDR 0x40000000
#define IPU_SOC_BASE_ADDR 0x40000000
#define IPU_SOC_OFFSET 0x1E000000
#define SPBA0_BASE_ADDR 0x70000000
#define AIPS1_BASE_ADDR 0x73F00000
#define AIPS2_BASE_ADDR 0x83F00000
@ -34,7 +35,8 @@
#define NFC_BASE_ADDR_AXI 0xCFFF0000
#define CS1_BASE_ADDR 0xB8000000
#elif defined(CONFIG_MX53)
#define IPU_CTRL_BASE_ADDR 0x18000000
#define IPU_SOC_BASE_ADDR 0x18000000
#define IPU_SOC_OFFSET 0x06000000
#define SPBA0_BASE_ADDR 0x50000000
#define AIPS1_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR 0x63F00000
@ -48,6 +50,8 @@
#error "CPU_TYPE not defined"
#endif
#define IPU_CTRL_BASE_ADDR IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET
#define IRAM_SIZE 0x00020000 /* 128 KB */
/*

61
arch/arm/include/asm/arch-omap3/dss.h
View file

@ -28,15 +28,19 @@
#ifndef DSS_H
#define DSS_H
/*
* DSS Base Registers
*/
#define OMAP3_DSS_BASE 0x48050040
#define OMAP3_DISPC_BASE 0x48050440
/* DSS Base Registers */
#define OMAP3_DSS_BASE 0x48050000
#define OMAP3_DISPC_BASE 0x48050400
#define OMAP3_VENC_BASE 0x48050C00
/* DSS Registers */
struct dss_regs {
u32 revision; /* 0x00 */
u8 res1[12]; /* 0x04 */
u32 sysconfig; /* 0x10 */
u32 sysstatus; /* 0x14 */
u32 irqstatus; /* 0x18 */
u8 res2[36]; /* 0x1C */
u32 control; /* 0x40 */
u32 sdi_control; /* 0x44 */
u32 pll_control; /* 0x48 */
@ -44,6 +48,13 @@ struct dss_regs {
/* DISPC Registers */
struct dispc_regs {
u32 revision; /* 0x00 */
u8 res1[12]; /* 0x04 */
u32 sysconfig; /* 0x10 */
u32 sysstatus; /* 0x14 */
u32 irqstatus; /* 0x18 */
u32 irqenable; /* 0x1C */
u8 res2[32]; /* 0x20 */
u32 control; /* 0x40 */
u32 config; /* 0x44 */
u32 reserve_2; /* 0x48 */
@ -60,6 +71,18 @@ struct dispc_regs {
u32 global_alpha; /* 0x74 */
u32 size_dig; /* 0x78 */
u32 size_lcd; /* 0x7C */
u32 gfx_ba0; /* 0x80 */
u32 gfx_ba1; /* 0x84 */
u32 gfx_position; /* 0x88 */
u32 gfx_size; /* 0x8C */
u8 unused[16]; /* 0x90 */
u32 gfx_attributes; /* 0xA0 */
u32 gfx_fifo_threshold; /* 0xA4 */
u32 gfx_fifo_size_status; /* 0xA8 */
u32 gfx_row_inc; /* 0xAC */
u32 gfx_pixel_inc; /* 0xB0 */
u32 gfx_window_skip; /* 0xB4 */
u32 gfx_table_ba; /* 0xB8 */
};
/* VENC Registers */
@ -123,6 +146,13 @@ struct venc_regs {
#define TFTSTN_SHIFT 3
#define DATALINES_SHIFT 8
#define GFX_ENABLE 1
#define GFX_FORMAT_SHIFT 1
#define LOADMODE_SHIFT 1
#define DSS_SOFTRESET (1 << 1)
#define DSS_RESETDONE 1
/* Enabling Display controller */
#define LCD_ENABLE 1
#define DIG_ENABLE (1 << 1)
@ -131,26 +161,14 @@ struct venc_regs {
#define GP_OUT0 (1 << 15)
#define GP_OUT1 (1 << 16)
#define DISPC_ENABLE (LCD_ENABLE | \
DIG_ENABLE | \
GO_LCD | \
GO_DIG | \
GP_OUT0| \
GP_OUT1)
/* Configure VENC DSS Params */
#define VENC_CLK_ENABLE (1 << 3)
#define DAC_DEMEN (1 << 4)
#define DAC_POWERDN (1 << 5)
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
DAC_DEMEN | \
DAC_POWERDN | \
VENC_OUT_SEL)
/*
* Panel Configuration
*/
/* Panel Configuration */
struct panel_config {
u32 timing_h;
u32 timing_v;
@ -161,11 +179,10 @@ struct panel_config {
u32 data_lines;
u32 load_mode;
u32 panel_color;
void *frame_buffer;
};
/*
* Generic DSS Functions
*/
/* Generic DSS Functions */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width);
void omap3_dss_panel_config(const struct panel_config *panel_cfg);

59
board/freescale/mx51evk/mx51evk.c
View file

@ -36,6 +36,12 @@
#include <fsl_pmic.h>
#include <mc13892.h>
#include <usb/ehci-fsl.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#define MX51EVK_LCD_3V3 (3 * 32 + 9) /* GPIO4_9 */
#define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */
#define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4) /* GPIO3_4 */
DECLARE_GLOBAL_DATA_PTR;
@ -453,6 +459,54 @@ int board_mmc_init(bd_t *bis)
}
#endif
static struct fb_videomode claa_wvga = {
.name = "CLAA07LC0ACW",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
void lcd_iomux(void)
{
/* DI2_PIN15 */
mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
/* Pad settings for MX51_PIN_DI2_DISP_CLK */
mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
/* Turn on 3.3V voltage for LCD */
mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
gpio_direction_output(MX51EVK_LCD_3V3, 1);
/* Turn on 5V voltage for LCD */
mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
gpio_direction_output(MX51EVK_LCD_5V, 1);
/* Turn on GPIO backlight */
mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
INPUT_CTL_PATH1);
gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
}
void lcd_enable(void)
{
int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
if (ret)
printf("LCD cannot be configured: %d\n", ret);
}
int board_early_init_f(void)
{
setup_iomux_uart();
@ -460,6 +514,7 @@ int board_early_init_f(void)
#ifdef CONFIG_USB_EHCI_MX5
setup_usb_h1();
#endif
lcd_iomux();
return 0;
}
@ -469,6 +524,8 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
lcd_enable();
return 0;
}
@ -479,6 +536,8 @@ int board_late_init(void)
setup_iomux_spi();
power_init();
#endif
setenv("stdout", "serial");
return 0;
}
#endif

72
board/freescale/mx53loco/mx53loco.c
View file

@ -39,6 +39,10 @@
#include <pmic.h>
#include <dialog_pmic.h>
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */
DECLARE_GLOBAL_DATA_PTR;
@ -402,10 +406,74 @@ static void clock_1GHz(void)
printf("CPU: Switch DDR clock to 400MHz failed\n");
}
static struct fb_videomode claa_wvga = {
.name = "CLAA07LC0ACW",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
void lcd_iomux(void)
{
mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
/* Turn on GPIO backlight */
mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
gpio_direction_output(MX53LOCO_LCD_POWER, 1);
/* Turn on display contrast */
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
}
void lcd_enable(void)
{
int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
if (ret)
printf("LCD cannot be configured: %d\n", ret);
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
lcd_iomux();
return 0;
}
@ -432,6 +500,8 @@ int board_late_init(void)
clock_1GHz();
print_cpuinfo();
setenv("stdout", "serial");
return 0;
}
#endif
@ -442,6 +512,8 @@ int board_init(void)
mxc_set_sata_internal_clock();
lcd_enable();
return 0;
}

16
board/samsung/trats/trats.c
View file

@ -37,6 +37,7 @@
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <max8997_pmic.h>
#include <libtizen.h>
#include "setup.h"
@ -53,6 +54,11 @@ u32 get_board_rev(void)
static void check_hw_revision(void);
static int hwrevision(int rev)
{
return (board_rev & 0xf) == rev;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@ -491,6 +497,16 @@ void init_panel_info(vidinfo_t *vid)
vid->reset_delay = 0;
vid->interface_mode = FIMD_RGB_INTERFACE;
vid->mipi_enabled = 1;
vid->logo_on = 1,
vid->resolution = HD_RESOLUTION,
vid->rgb_mode = MODE_RGB_P,
#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif
if (hwrevision(2))
mipi_lcd_device.reverse_panel = 1;
strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
s6e8ax0_platform_data.lcd_power = lcd_power;

2
board/ttcontrol/vision2/vision2.c
View file

@ -604,7 +604,7 @@ void lcd_enable(void)
gpio_set_value(2, 1);
mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
ret = mx51_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
if (ret)
puts("LCD cannot be configured\n");
}

3
common/cmd_bmp.c
View file

@ -33,7 +33,6 @@
#include <malloc.h>
static int bmp_info (ulong addr);
static int bmp_display (ulong addr, int x, int y);
/*
* Allocate and decompress a BMP image using gunzip().
@ -221,7 +220,7 @@ static int bmp_info(ulong addr)
* Return: None
*
*/
static int bmp_display(ulong addr, int x, int y)
int bmp_display(ulong addr, int x, int y)
{
int ret;
bmp_image_t *bmp = (bmp_image_t *)addr;

45
common/lcd.c
View file

@ -216,6 +216,10 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
uchar *dest;
ushort row;
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
y += BMP_LOGO_HEIGHT;
#endif
#if LCD_BPP == LCD_MONOCHROME
ushort off = x * (1 << LCD_BPP) % 8;
#endif
@ -271,22 +275,14 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
{
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen ((char *)s));
#else
lcd_drawchars (x, y, s, strlen ((char *)s));
#endif
lcd_drawchars(x, y, s, strlen((char *)s));
}
/*----------------------------------------------------------------------*/
static inline void lcd_putc_xy (ushort x, ushort y, uchar c)
{
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
lcd_drawchars (x, y+BMP_LOGO_HEIGHT, &c, 1);
#else
lcd_drawchars (x, y, &c, 1);
#endif
lcd_drawchars(x, y, &c, 1);
}
/************************************************************************/
@ -523,7 +519,7 @@ void bitmap_plot (int x, int y)
debug ("Logo: width %d height %d colors %d cmap %d\n",
BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS,
(int)(sizeof(bmp_logo_palette)/(sizeof(ushort))));
ARRAY_SIZE(bmp_logo_palette));
bmap = &bmp_logo_bitmap[0];
fb = (uchar *)(lcd_base + y * lcd_line_length + x);
@ -548,7 +544,7 @@ void bitmap_plot (int x, int y)
WATCHDOG_RESET();
/* Set color map */
for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
for (i = 0; i < ARRAY_SIZE(bmp_logo_palette); ++i) {
ushort colreg = bmp_logo_palette[i];
#ifdef CONFIG_ATMEL_LCD
uint lut_entry;
@ -598,6 +594,8 @@ void bitmap_plot (int x, int y)
WATCHDOG_RESET();
}
#else
static inline void bitmap_plot(int x, int y) {}
#endif /* CONFIG_LCD_LOGO */
/*----------------------------------------------------------------------*/
@ -645,14 +643,14 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
bpix = NBITS(panel_info.vl_bpix);
if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
if ((bpix != 1) && (bpix != 8) && (bpix != 16) && (bpix != 32)) {
printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
bpix, bmp_bpix);
return 1;
}
/* We support displaying 8bpp BMPs on 16bpp LCDs */
if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) {
if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16 || bpix != 32)) {
printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
bpix,
le16_to_cpu(bmp->header.bit_count));
@ -669,7 +667,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
#elif !defined(CONFIG_ATMEL_LCD)
#elif !defined(CONFIG_ATMEL_LCD) && !defined(CONFIG_EXYNOS_FB)
cmap = panel_info.cmap;
#endif
@ -791,6 +789,19 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
break;
#endif /* CONFIG_BMP_16BPP */
#if defined(CONFIG_BMP_32BPP)
case 32:
for (i = 0; i < height; ++i) {
for (j = 0; j < width; j++) {
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
}
fb -= (lcd_line_length + width * (bpix / 8));
}
break;
#endif /* CONFIG_BMP_32BPP */
default:
break;
};
@ -843,9 +854,7 @@ static void *lcd_logo (void)
}
#endif /* CONFIG_SPLASH_SCREEN */
#ifdef CONFIG_LCD_LOGO
bitmap_plot (0, 0);
#endif /* CONFIG_LCD_LOGO */
bitmap_plot(0, 0);
#ifdef CONFIG_LCD_INFO
console_col = LCD_INFO_X / VIDEO_FONT_WIDTH;

3
drivers/video/Makefile
View file

@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libvideo.o
COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
COBJS-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
@ -42,7 +43,7 @@ COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o

211
drivers/video/atmel_hlcdfb.c Normal file
View file

@ -0,0 +1,211 @@
/*
* Driver for AT91/AT32 MULTI LAYER LCD Controller
*
* Copyright (C) 2012 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <atmel_hlcdc.h>
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
void *lcd_base; /* Start of framebuffer memory */
void *lcd_console_address; /* Start of console buffer */
short console_col;
short console_row;
/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8
#ifndef ATMEL_LCDC_GUARD_TIME
#define ATMEL_LCDC_GUARD_TIME 1
#endif
#define ATMEL_LCDC_FIFO_SIZE 512
#define lcdc_readl(reg) __raw_readl((reg))
#define lcdc_writel(reg, val) __raw_writel((val), (reg))
void lcd_ctrl_init(void *lcdbase)
{
unsigned long value;
struct lcd_dma_desc *desc;
struct atmel_hlcd_regs *regs;
if (!has_lcdc())
return; /* No lcdc */
regs = (struct atmel_hlcd_regs *)panel_info.mmio;
/* Disable DISP signal */
lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
udelay(1);
/* Disable synchronization */
lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
udelay(1);
/* Disable pixel clock */
lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
udelay(1);
/* Disable PWM */
lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
udelay(1);
/* Set pixel clock */
value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
value++;
if (value < 1) {
/* Using system clock as pixel clock */
lcdc_writel(&regs->lcdc_lcdcfg0,
LCDC_LCDCFG0_CLKDIV(0)
| LCDC_LCDCFG0_CGDISHCR
| LCDC_LCDCFG0_CGDISHEO
| LCDC_LCDCFG0_CGDISOVR1
| LCDC_LCDCFG0_CGDISBASE
| panel_info.vl_clk_pol
| LCDC_LCDCFG0_CLKSEL);
} else {
lcdc_writel(&regs->lcdc_lcdcfg0,
LCDC_LCDCFG0_CLKDIV(value - 2)
| LCDC_LCDCFG0_CGDISHCR
| LCDC_LCDCFG0_CGDISHEO
| LCDC_LCDCFG0_CGDISOVR1
| LCDC_LCDCFG0_CGDISBASE
| panel_info.vl_clk_pol);
}
/* Initialize control register 5 */
value = 0;
value |= panel_info.vl_sync;
#ifndef LCD_OUTPUT_BPP
/* Output is 24bpp */
value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
#else
switch (LCD_OUTPUT_BPP) {
case 12:
value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
break;
case 16:
value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
break;
case 18:
value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
break;
case 24:
value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
break;
default:
BUG();
break;
}
#endif
value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
lcdc_writel(&regs->lcdc_lcdcfg5, value);
/* Vertical & Horizontal Timing */
value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
lcdc_writel(&regs->lcdc_lcdcfg1, value);
value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
lcdc_writel(&regs->lcdc_lcdcfg2, value);
value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
lcdc_writel(&regs->lcdc_lcdcfg3, value);
/* Display size */
value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
lcdc_writel(&regs->lcdc_lcdcfg4, value);
lcdc_writel(&regs->lcdc_basecfg0,
LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
switch (NBITS(panel_info.vl_bpix)) {
case 16:
lcdc_writel(&regs->lcdc_basecfg1,
LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
break;
default:
BUG();
break;
}
lcdc_writel(&regs->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
lcdc_writel(&regs->lcdc_basecfg3, 0);
lcdc_writel(&regs->lcdc_basecfg4, LCDC_BASECFG4_DMA);
/* Disable all interrupts */
lcdc_writel(&regs->lcdc_lcdidr, ~0UL);
lcdc_writel(&regs->lcdc_baseidr, ~0UL);
/* Setup the DMA descriptor, this descriptor will loop to itself */
desc = (struct lcd_dma_desc *)(lcdbase - 16);
desc->address = (u32)lcdbase;
/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
desc->next = (u32)desc;
lcdc_writel(&regs->lcdc_baseaddr, desc->address);
lcdc_writel(&regs->lcdc_basectrl, desc->control);
lcdc_writel(&regs->lcdc_basenext, desc->next);
lcdc_writel(&regs->lcdc_basecher, LCDC_BASECHER_CHEN |
LCDC_BASECHER_UPDATEEN);
/* Enable LCD */
value = lcdc_readl(&regs->lcdc_lcden);
lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
udelay(1);
value = lcdc_readl(&regs->lcdc_lcden);
lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
udelay(1);
value = lcdc_readl(&regs->lcdc_lcden);
lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
udelay(1);
value = lcdc_readl(&regs->lcdc_lcden);
lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
udelay(1);
}

89
drivers/video/cfb_console.c
View file

@ -360,6 +360,8 @@ void console_cursor(int state);
extern void video_get_info_str(int line_number, char *info);
#endif
DECLARE_GLOBAL_DATA_PTR;
/* Locals */
static GraphicDevice *pGD; /* Pointer to Graphic array */
@ -377,6 +379,8 @@ static int console_row; /* cursor row */
static u32 eorx, fgx, bgx; /* color pats */
static int cfb_do_flush_cache;
static const int video_font_draw_table8[] = {
0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
@ -553,6 +557,8 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count)
SWAP32((video_font_draw_table32
[bits & 15][3] & eorx) ^ bgx);
}
if (cfb_do_flush_cache)
flush_cache((ulong)dest0, 32);
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
@ -621,6 +627,8 @@ static void video_invertchar(int xx, int yy)
for (x = firstx; x < lastx; x++) {
u8 *dest = (u8 *)(video_fb_address) + x + y;
*dest = ~*dest;
if (cfb_do_flush_cache)
flush_cache((ulong)dest, 4);
}
}
}
@ -683,6 +691,43 @@ static void memcpyl(int *d, int *s, int c)
}
#endif
static void console_clear_line(int line, int begin, int end)
{
#ifdef VIDEO_HW_RECTFILL
video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
VIDEO_FONT_WIDTH * begin, /* dest pos x */
video_logo_height +
VIDEO_FONT_HEIGHT * line, /* dest pos y */
VIDEO_FONT_WIDTH * (end - begin + 1), /* fr. width */
VIDEO_FONT_HEIGHT, /* frame height */
bgx /* fill color */
);
#else
if (begin == 0 && (end + 1) == CONSOLE_COLS) {
memsetl(CONSOLE_ROW_FIRST +
CONSOLE_ROW_SIZE * line, /* offset of row */
CONSOLE_ROW_SIZE >> 2, /* length of row */
bgx /* fill color */
);
} else {
void *offset;
int i, size;
offset = CONSOLE_ROW_FIRST +
CONSOLE_ROW_SIZE * line + /* offset of row */
VIDEO_FONT_WIDTH *
VIDEO_PIXEL_SIZE * begin; /* offset of col */
size = VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE * (end - begin + 1);
size >>= 2; /* length to end for memsetl() */
/* fill at col offset of i'th line using bgx as fill color */
for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
memsetl(offset + i * VIDEO_LINE_LEN, size, bgx);
}
#endif
if (cfb_do_flush_cache)
flush_cache((ulong)CONSOLE_ROW_FIRST, CONSOLE_SIZE);
}
static void console_scrollup(void)
{
/* copy up rows ignoring the first one */
@ -703,25 +748,12 @@ static void console_scrollup(void)
memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
CONSOLE_SCROLL_SIZE >> 2);
#endif
/* clear the last one */
#ifdef VIDEO_HW_RECTFILL
video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
0, /* dest pos x */
VIDEO_VISIBLE_ROWS
- VIDEO_FONT_HEIGHT, /* dest pos y */
VIDEO_VISIBLE_COLS, /* frame width */
VIDEO_FONT_HEIGHT, /* frame height */
CONSOLE_BG_COL /* fill color */
);
#else
memsetl(CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL);
#endif
console_clear_line(CONSOLE_ROWS - 1, 0, CONSOLE_COLS - 1);
}
static void console_back(void)
{
CURSOR_OFF;
console_col--;
if (console_col < 0) {
@ -730,7 +762,6 @@ static void console_back(void)
if (console_row < 0)
console_row = 0;
}
CURSOR_SET;
}
static void console_newline(void)
@ -782,6 +813,9 @@ void video_putc(const char c)
console_back();
break;
case 7: /* bell */
break; /* ignored */
default: /* draw the char */
video_putchar(console_col * VIDEO_FONT_WIDTH,
console_row * VIDEO_FONT_HEIGHT, c);
@ -1651,6 +1685,29 @@ static void *video_logo(void)
}
#endif
static int cfb_fb_is_in_dram(void)
{
bd_t *bd = gd->bd;
#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) || defined(COFNIG_NDS32) || \
defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
ulong start, end;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
start = bd->bi_dram[i].start;
end = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
if ((ulong)video_fb_address >= start &&
(ulong)video_fb_address < end)
return 1;
}
#else
if ((ulong)video_fb_address >= bd->bi_memstart &&
(ulong)video_fb_address < bd->bi_memstart + bd->bi_memsize)
return 1;
#endif
return 0;
}
static int video_init(void)
{
unsigned char color8;
@ -1664,6 +1721,8 @@ static int video_init(void)
video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
#endif
cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status();
/* Init drawing pats */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:

19
drivers/video/exynos_fb.c
View file

@ -67,6 +67,18 @@ static void exynos_lcd_init(vidinfo_t *vid)
exynos_fimd_lcd_init(vid);
}
static void draw_logo(void)
{
int x, y;
ulong addr;
x = ((panel_width - panel_info.logo_width) >> 1);
y = ((panel_height - panel_info.logo_height) >> 1) - 4;
addr = panel_info.logo_addr;
bmp_display(addr, x, y);
}
static void lcd_panel_on(vidinfo_t *vid)
{
udelay(vid->init_delay);
@ -118,6 +130,13 @@ void lcd_ctrl_init(void *lcdbase)
void lcd_enable(void)
{
if (panel_info.logo_on) {
memset(lcd_base, 0, panel_width * panel_height *
(NBITS(panel_info.vl_bpix) >> 3));
draw_logo();
}
lcd_panel_on(&panel_info);
}

7
drivers/video/exynos_fb.h
View file

@ -27,13 +27,6 @@
#define MAX_CLOCK (86 * 1000000)
enum exynos_fb_rgb_mode_t {
MODE_RGB_P = 0,
MODE_BGR_P = 1,
MODE_RGB_S = 2,
MODE_BGR_S = 3,
};
enum exynos_cpu_auto_cmd_rate {
DISABLE_AUTO_FRM,
PER_TWO_FRM,

2
drivers/video/exynos_fimd.c
View file

@ -273,7 +273,7 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
/* store panel info to global variable */
pvid = vid;
rgb_mode = MODE_RGB_P;
rgb_mode = vid->rgb_mode;
if (vid->interface_mode == FIMD_RGB_INTERFACE) {
cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;

42
drivers/video/ipu_regs.h
View file

@ -33,27 +33,27 @@
#define IPU_DISP0_BASE 0x00000000
#define IPU_MCU_T_DEFAULT 8
#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
#define IPU_CM_REG_BASE 0x1E000000
#define IPU_STAT_REG_BASE 0x1E000200
#define IPU_IDMAC_REG_BASE 0x1E008000
#define IPU_ISP_REG_BASE 0x1E010000
#define IPU_DP_REG_BASE 0x1E018000
#define IPU_IC_REG_BASE 0x1E020000
#define IPU_IRT_REG_BASE 0x1E028000
#define IPU_CSI0_REG_BASE 0x1E030000
#define IPU_CSI1_REG_BASE 0x1E038000
#define IPU_DI0_REG_BASE 0x1E040000
#define IPU_DI1_REG_BASE 0x1E048000
#define IPU_SMFC_REG_BASE 0x1E050000
#define IPU_DC_REG_BASE 0x1E058000
#define IPU_DMFC_REG_BASE 0x1E060000
#define IPU_CPMEM_REG_BASE 0x1F000000
#define IPU_LUT_REG_BASE 0x1F020000
#define IPU_SRM_REG_BASE 0x1F040000
#define IPU_TPM_REG_BASE 0x1F060000
#define IPU_DC_TMPL_REG_BASE 0x1F080000
#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000
#define IPU_VDI_REG_BASE 0x1E068000
#define IPU_CM_REG_BASE 0x00000000
#define IPU_STAT_REG_BASE 0x00000200
#define IPU_IDMAC_REG_BASE 0x00008000
#define IPU_ISP_REG_BASE 0x00010000
#define IPU_DP_REG_BASE 0x00018000
#define IPU_IC_REG_BASE 0x00020000
#define IPU_IRT_REG_BASE 0x00028000
#define IPU_CSI0_REG_BASE 0x00030000
#define IPU_CSI1_REG_BASE 0x00038000
#define IPU_DI0_REG_BASE 0x00040000
#define IPU_DI1_REG_BASE 0x00048000
#define IPU_SMFC_REG_BASE 0x00050000
#define IPU_DC_REG_BASE 0x00058000
#define IPU_DMFC_REG_BASE 0x00060000
#define IPU_CPMEM_REG_BASE 0x01000000
#define IPU_LUT_REG_BASE 0x01020000
#define IPU_SRM_REG_BASE 0x01040000
#define IPU_TPM_REG_BASE 0x01060000
#define IPU_DC_TMPL_REG_BASE 0x01080000
#define IPU_ISP_TBPR_REG_BASE 0x010C0000
#define IPU_VDI_REG_BASE 0x00680000
extern u32 *ipu_dc_tmpl_reg;

2
drivers/video/mxc_ipuv3_fb.c
View file

@ -599,7 +599,7 @@ void video_set_lut(unsigned int index, /* color number */
return;
}
int mx51_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt)
int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt)
{
gmode = mode;
gdisp = disp;

77
drivers/video/omap3_dss.c
View file

@ -28,10 +28,9 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/dss.h>
#include <video_fb.h>
/*
* Configure VENC for a given Mode (NTSC / PAL)
*/
/* Configure VENC for a given Mode (NTSC / PAL) */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width)
{
@ -64,10 +63,8 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
writel(venc_cfg->savid__eavid, &venc->savid__eavid);
writel(venc_cfg->flen__fal, &venc->flen__fal);
writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
writel(venc_cfg->hs_int_start_stop_x,
&venc->hs_int_start_stop_x);
writel(venc_cfg->hs_ext_start_stop_x,
&venc->hs_ext_start_stop_x);
writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x);
writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x);
writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
&venc->vs_int_stop_x__vs_int_start_y);
@ -93,39 +90,79 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
/* Configure DSS for VENC Settings */
writel(VENC_DSS_CONFIG, &dss->control);
writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL,
&dss->control);
/* Configure height and width for Digital out */
writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig);
}
/*
* Configure Panel Specific Parameters
*/
/* Configure Panel Specific Parameters */
void omap3_dss_panel_config(const struct panel_config *panel_cfg)
{
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
writel(DSS_SOFTRESET, &dss->sysconfig);
while (!(readl(&dss->sysstatus) & DSS_RESETDONE))
;
writel(panel_cfg->timing_h, &dispc->timing_h);
writel(panel_cfg->timing_v, &dispc->timing_v);
writel(panel_cfg->pol_freq, &dispc->pol_freq);
writel(panel_cfg->divisor, &dispc->divisor);
writel(panel_cfg->lcd_size, &dispc->size_lcd);
writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
(panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
writel(panel_cfg->load_mode << FRAME_MODE_SHIFT, &dispc->config);
writel(panel_cfg->panel_type << TFTSTN_SHIFT |
panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
writel(panel_cfg->panel_color, &dispc->default_color0);
writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
if (!panel_cfg->frame_buffer)
return;
writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes);
writel(1, &dispc->gfx_row_inc);
writel(1, &dispc->gfx_pixel_inc);
writel(panel_cfg->lcd_size, &dispc->gfx_size);
}
/*
* Enable LCD and DIGITAL OUT in DSS
*/
/* Enable LCD and DIGITAL OUT in DSS */
void omap3_dss_enable(void)
{
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
u32 l = 0;
u32 l;
l = readl(&dispc->control);
l |= DISPC_ENABLE;
l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
writel(l, &dispc->control);
}
#ifdef CONFIG_CFB_CONSOLE
int __board_video_init(void)
{
return -1;
}
int board_video_init(void)
__attribute__((weak, alias("__board_video_init")));
void *video_hw_init(void)
{
static GraphicDevice dssfb;
GraphicDevice *pGD = &dssfb;
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
if (board_video_init() || !readl(&dispc->gfx_ba0))
return NULL;
pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
pGD->gdfBytesPP = 4;
pGD->gdfIndex = GDF_32BIT_X888RGB;
pGD->frameAdrs = readl(&dispc->gfx_ba0);
return pGD;
}
#endif

25
drivers/video/s6e8ax0.c
View file

@ -28,6 +28,7 @@
static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
{
struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
int reverse = dsim_dev->dsim_lcd_dev->reverse_panel;
const unsigned char data_to_send[] = {
0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c,
0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20,
@ -36,8 +37,22 @@ static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
0xff, 0xff, 0xc8
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
const unsigned char data_to_send_reverse[] = {
0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c,
0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20,
0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1,
0xf6, 0xf6, 0xc1
};
if (reverse) {
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
(unsigned int)data_to_send_reverse,
ARRAY_SIZE(data_to_send_reverse));
} else {
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
}
}
static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
@ -55,11 +70,11 @@ static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
{
struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
/* 7500K 2.2 Set (M3, 300cd) */
/* 7500K 2.2 Set : 30cd */
const unsigned char data_to_send[] = {
0xfa, 0x01, 0x0f, 0x00, 0x0f, 0xda, 0xc0, 0xe4, 0xc8,
0xc8, 0xc6, 0xd3, 0xd6, 0xd0, 0xab, 0xb2, 0xa6, 0xbf,
0xc2, 0xb9, 0x00, 0x93, 0x00, 0x86, 0x00, 0xd1
0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad,
0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1,
0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74,
};
ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,

231
include/atmel_hlcdc.h Normal file
View file

@ -0,0 +1,231 @@
/*
* Header file for AT91/AT32 MULTI LAYER LCD Controller
*
* Data structure and register user interface
*
* Copyright (C) 2012 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ATMEL_HLCDC_H__
#define __ATMEL_HLCDC_H__
/* Atmel multi layer lcdc hardware registers */
struct atmel_hlcd_regs {
u32 lcdc_lcdcfg0;
u32 lcdc_lcdcfg1;
u32 lcdc_lcdcfg2;
u32 lcdc_lcdcfg3;
u32 lcdc_lcdcfg4;
u32 lcdc_lcdcfg5;
u32 lcdc_lcdcfg6;
u32 res1;
u32 lcdc_lcden;
u32 lcdc_lcddis;
u32 lcdc_lcdsr;
u32 res2;
u32 lcdc_lcdidr;
u32 res3[3];
u32 lcdc_basecher;
u32 res4[3];
u32 lcdc_baseidr;
u32 res5[3];
u32 lcdc_baseaddr;
u32 lcdc_basectrl;
u32 lcdc_basenext;
u32 lcdc_basecfg0;
u32 lcdc_basecfg1;
u32 lcdc_basecfg2;
u32 lcdc_basecfg3;
u32 lcdc_basecfg4;
};
#define LCDC_LCDCFG0_CLKPOL (0x1 << 0)
#define LCDC_LCDCFG0_CLKSEL (0x1 << 2)
#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3)
#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8)
#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9)
#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11)
#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12)
#define LCDC_LCDCFG0_CLKDIV_Pos 16
#define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos)
#define LCDC_LCDCFG0_CLKDIV(value) \
((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
#define LCDC_LCDCFG1_HSPW_Pos 0
#define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos)
#define LCDC_LCDCFG1_HSPW(value) \
((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
#define LCDC_LCDCFG1_VSPW_Pos 16
#define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos)
#define LCDC_LCDCFG1_VSPW(value) \
((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
#define LCDC_LCDCFG2_VFPW_Pos 0
#define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos)
#define LCDC_LCDCFG2_VFPW(value) \
((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
#define LCDC_LCDCFG2_VBPW_Pos 16
#define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos)
#define LCDC_LCDCFG2_VBPW(value) \
((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
#define LCDC_LCDCFG3_HFPW_Pos 0
#define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos)
#define LCDC_LCDCFG3_HFPW(value) \
((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
#define LCDC_LCDCFG3_HBPW_Pos 16
#define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos)
#define LCDC_LCDCFG3_HBPW(value) \
((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
#define LCDC_LCDCFG4_PPL_Pos 0
#define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos)
#define LCDC_LCDCFG4_PPL(value) \
((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
#define LCDC_LCDCFG4_RPF_Pos 16
#define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos)
#define LCDC_LCDCFG4_RPF(value) \
((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
#define LCDC_LCDCFG5_HSPOL (0x1 << 0)
#define LCDC_LCDCFG5_VSPOL (0x1 << 1)
#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2)
#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3)
#define LCDC_LCDCFG5_DISPPOL (0x1 << 4)
#define LCDC_LCDCFG5_SERIAL (0x1 << 5)
#define LCDC_LCDCFG5_DITHER (0x1 << 6)
#define LCDC_LCDCFG5_DISPDLY (0x1 << 7)
#define LCDC_LCDCFG5_MODE_Pos 8
#define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos)
#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8)
#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8)
#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8)
#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8)
#define LCDC_LCDCFG5_VSPSU (0x1 << 12)
#define LCDC_LCDCFG5_VSPHO (0x1 << 13)
#define LCDC_LCDCFG5_GUARDTIME_Pos 16
#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
#define LCDC_LCDCFG5_GUARDTIME(value) \
((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
#define LCDC_LCDCFG6_PWMPS_Pos 0
#define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos)
#define LCDC_LCDCFG6_PWMPS(value) \
((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
#define LCDC_LCDCFG6_PWMPOL (0x1 << 4)
#define LCDC_LCDCFG6_PWMCVAL_Pos 8
#define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
#define LCDC_LCDCFG6_PWMCVAL(value) \
((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
#define LCDC_LCDEN_CLKEN (0x1 << 0)
#define LCDC_LCDEN_SYNCEN (0x1 << 1)
#define LCDC_LCDEN_DISPEN (0x1 << 2)
#define LCDC_LCDEN_PWMEN (0x1 << 3)
#define LCDC_LCDDIS_CLKDIS (0x1 << 0)
#define LCDC_LCDDIS_SYNCDIS (0x1 << 1)
#define LCDC_LCDDIS_DISPDIS (0x1 << 2)
#define LCDC_LCDDIS_PWMDIS (0x1 << 3)
#define LCDC_LCDDIS_CLKRST (0x1 << 8)
#define LCDC_LCDDIS_SYNCRST (0x1 << 9)
#define LCDC_LCDDIS_DISPRST (0x1 << 10)
#define LCDC_LCDDIS_PWMRST (0x1 << 11)
#define LCDC_LCDSR_CLKSTS (0x1 << 0)
#define LCDC_LCDSR_LCDSTS (0x1 << 1)
#define LCDC_LCDSR_DISPSTS (0x1 << 2)
#define LCDC_LCDSR_PWMSTS (0x1 << 3)
#define LCDC_LCDSR_SIPSTS (0x1 << 4)
#define LCDC_LCDIDR_SOFID (0x1 << 0)
#define LCDC_LCDIDR_DISID (0x1 << 1)
#define LCDC_LCDIDR_DISPID (0x1 << 2)
#define LCDC_LCDIDR_FIFOERRID (0x1 << 4)
#define LCDC_LCDIDR_BASEID (0x1 << 8)
#define LCDC_LCDIDR_OVR1ID (0x1 << 9)
#define LCDC_LCDIDR_HEOID (0x1 << 11)
#define LCDC_LCDIDR_HCRID (0x1 << 12)
#define LCDC_BASECHER_CHEN (0x1 << 0)
#define LCDC_BASECHER_UPDATEEN (0x1 << 1)
#define LCDC_BASECHER_A2QEN (0x1 << 2)
#define LCDC_BASEIDR_DMA (0x1 << 2)
#define LCDC_BASEIDR_DSCR (0x1 << 3)
#define LCDC_BASEIDR_ADD (0x1 << 4)
#define LCDC_BASEIDR_DONE (0x1 << 5)
#define LCDC_BASEIDR_OVR (0x1 << 6)
#define LCDC_BASECTRL_DFETCH (0x1 << 0)
#define LCDC_BASECTRL_LFETCH (0x1 << 1)
#define LCDC_BASECTRL_DMAIEN (0x1 << 2)
#define LCDC_BASECTRL_DSCRIEN (0x1 << 3)
#define LCDC_BASECTRL_ADDIEN (0x1 << 4)
#define LCDC_BASECTRL_DONEIEN (0x1 << 5)
#define LCDC_BASECFG0_BLEN_Pos 4
#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4)
#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4)
#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4)
#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4)
#define LCDC_BASECFG0_DLBO (0x1 << 8)
#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4)
#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4)
#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4)
#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4)
#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4)
#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4)
#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4)
#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4)
#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4)
#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4)
#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4)
#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4)
#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4)
#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4)
#define LCDC_BASECFG2_XSTRIDE_Pos 0
#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
#define LCDC_BASECFG2_XSTRIDE(value) \
((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
#define LCDC_BASECFG3_BDEF_Pos 0
#define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos)
#define LCDC_BASECFG3_BDEF(value) \
((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
#define LCDC_BASECFG3_GDEF_Pos 8
#define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos)
#define LCDC_BASECFG3_GDEF(value) \
((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
#define LCDC_BASECFG3_RDEF_Pos 16
#define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos)
#define LCDC_BASECFG3_RDEF(value) \
((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
#define LCDC_BASECFG4_DMA (0x1 << 8)
#define LCDC_BASECFG4_REP (0x1 << 9)
struct lcd_dma_desc {
u32 address;
u32 control;
u32 next;
};
#define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4))
#endif /* __ATMEL_HLCDC_H__ */

13
include/configs/mx51evk.h
View file

@ -51,7 +51,7 @@
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_LATE_INIT
@ -123,6 +123,17 @@
#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
/* Framebuffer and LCD */
#define CONFIG_PREBOOT
#define CONFIG_VIDEO
#define CONFIG_VIDEO_MX5
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1

13
include/configs/mx53loco.h
View file

@ -38,7 +38,7 @@
#define CONFIG_INITRD_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
@ -220,4 +220,15 @@
#define CONFIG_LIBATA
#endif
/* Framebuffer and LCD */
#define CONFIG_PREBOOT
#define CONFIG_VIDEO
#define CONFIG_VIDEO_MX5
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#endif /* __CONFIG_H */

6
include/configs/trats.h
View file

@ -34,6 +34,7 @@
#define CONFIG_S5P /* which is in a S5P Family */
#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
#define CONFIG_TRATS /* working with TRATS */
#define CONFIG_TIZEN /* TIZEN lib */
#include <asm/arch/cpu.h> /* get chip and board defs */
@ -217,9 +218,12 @@
/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_32BPP
#define CONFIG_FB_ADDR 0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1280 * 720 * 4)
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
#endif /* __CONFIG_H */

2
include/ipu_pixfmt.h
View file

@ -76,6 +76,6 @@
#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
int mx51_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
#endif

17
include/lcd.h
View file

@ -55,6 +55,7 @@ extern void lcd_initcolregs (void);
/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
extern int bmp_display(ulong addr, int x, int y);
#if defined CONFIG_MPC823
/*
@ -157,7 +158,7 @@ typedef struct vidinfo {
struct pxafb_info pxa;
} vidinfo_t;
#elif defined(CONFIG_ATMEL_LCD)
#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
@ -169,6 +170,7 @@ typedef struct vidinfo {
u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_long vl_tft; /* 0 = passive, 1 = TFT */
u_long vl_cont_pol_low; /* contrast polarity is low */
u_long vl_clk_pol; /* clock polarity */
/* Horizontal control register. */
u_long vl_hsync_len; /* Length of horizontal sync */
@ -190,6 +192,13 @@ enum {
FIMD_CPU_INTERFACE = 2,
};
enum exynos_fb_rgb_mode_t {
MODE_RGB_P = 0,
MODE_BGR_P = 1,
MODE_RGB_S = 2,
MODE_BGR_S = 3,
};
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
@ -235,6 +244,12 @@ typedef struct vidinfo {
unsigned int wr_setup;
unsigned int wr_act;
unsigned int wr_hold;
unsigned int logo_on;
unsigned int logo_width;
unsigned int logo_height;
unsigned long logo_addr;
unsigned int rgb_mode;
unsigned int resolution;
/* parent clock name(MPLL, EPLL or VPLL) */
unsigned int pclk_name;

29
include/libtizen.h Normal file
View file

@ -0,0 +1,29 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* aint with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _LIBTIZEN_H_
#define _LIBTIZEN_H_
#define HD_RESOLUTION 0
void get_tizen_logo_info(vidinfo_t *vid);
#endif /* _LIBTIZEN_H_ */

1
include/video.h
View file

@ -14,6 +14,5 @@
int video_init (void *videobase);
void video_putc (const char c);
void video_puts (const char *s);
void video_printf (const char *fmt, ...);
#endif

46
lib/tizen/Makefile Normal file
View file

@ -0,0 +1,46 @@
#
# (C) Copyright 2012 Samsung Electronics
# Donghwa Lee <dh09.lee@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)libtizen.o
SOBJS =
COBJS-$(CONFIG_TIZEN) += tizen.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

40
lib/tizen/tizen.c Normal file
View file

@ -0,0 +1,40 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* aint with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <lcd.h>
#include <libtizen.h>
#include "tizen_hd_logo.h"
#include "tizen_hd_logo_data.h"
void get_tizen_logo_info(vidinfo_t *vid)
{
switch (vid->resolution) {
case HD_RESOLUTION:
vid->logo_width = TIZEN_HD_LOGO_WIDTH;
vid->logo_height = TIZEN_HD_LOGO_HEIGHT;
vid->logo_addr = (ulong)tizen_hd_logo;
break;
default:
break;
}
}

5071
lib/tizen/tizen_hd_logo.h Normal file
View file

File diff suppressed because it is too large Load diff

29
lib/tizen/tizen_hd_logo_data.h Normal file
View file

@ -0,0 +1,29 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* aint with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _TIZEN_HD_LOGO_DATA_H_
#define _TIZEN_HD_LOGO_DATA_H_
#define TIZEN_HD_LOGO_WIDTH 520
#define TIZEN_HD_LOGO_HEIGHT 120
#define TIZEN_HD_LOGO_BPP 32
#endif /* _TIZEN_HD_LOGO_DATA_H_ */