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https://github.com/AsahiLinux/u-boot
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usb/ehci: Add USB support for the MX6Q
Currently, only USB Host 1 is supported. Cc: Remy Bohmer <linux@bohmer.net> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
This commit is contained in:
Wolfgang Grandegger
Albert ARIBAUD
parent
4e187fbcdf
commit
3f467529ca
5 changed files with 223 additions and 0 deletions
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@ -36,6 +36,19 @@ enum pll_clocks {
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struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
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void enable_usboh3_clk(unsigned char enable)
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{
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u32 reg;
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reg = __raw_readl(&imx_ccm->CCGR6);
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if (enable)
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reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
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else
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reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
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__raw_writel(reg, &imx_ccm->CCGR6);
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}
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static u32 decode_pll(enum pll_clocks pll, u32 infreq)
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{
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u32 div;
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@ -46,5 +46,6 @@ enum mxc_clock {
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u32 imx_get_uartclk(void);
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u32 imx_get_fecclk(void);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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void enable_usboh3_clk(unsigned char enable);
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#endif /* __ASM_ARCH_CLOCK_H */
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@ -111,6 +111,9 @@
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#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
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#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
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#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
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#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
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#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
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#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
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#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
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#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
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#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
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@ -44,6 +44,7 @@ endif
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COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
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COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
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COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
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COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
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COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
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COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
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COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
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205
drivers/usb/host/ehci-mx6.c
Normal file
205
drivers/usb/host/ehci-mx6.c
Normal file
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@ -0,0 +1,205 @@
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/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <common.h>
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#include <usb.h>
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#include <errno.h>
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#include <linux/compiler.h>
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#include <usb/ehci-fsl.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6x_pins.h>
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#include <asm/arch/iomux-v3.h>
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#include "ehci.h"
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#include "ehci-core.h"
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#define USB_OTGREGS_OFFSET 0x000
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#define USB_H1REGS_OFFSET 0x200
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#define USB_H2REGS_OFFSET 0x400
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#define USB_H3REGS_OFFSET 0x600
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#define USB_OTHERREGS_OFFSET 0x800
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#define USB_H1_CTRL_OFFSET 0x04
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#define USBPHY_CTRL 0x00000030
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#define USBPHY_CTRL_SET 0x00000034
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#define USBPHY_CTRL_CLR 0x00000038
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#define USBPHY_CTRL_TOG 0x0000003c
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#define USBPHY_PWD 0x00000000
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#define USBPHY_CTRL_SFTRST 0x80000000
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#define USBPHY_CTRL_CLKGATE 0x40000000
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#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
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#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
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#define ANADIG_USB2_CHRG_DETECT 0x00000210
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#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
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#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
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#define ANADIG_USB2_PLL_480_CTRL 0x00000020
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#define ANADIG_USB2_PLL_480_CTRL_SET 0x00000024
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#define ANADIG_USB2_PLL_480_CTRL_CLR 0x00000028
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#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
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#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
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#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
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#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
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#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
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#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
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/* USBCMD */
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#define UH1_USBCMD_OFFSET 0x140
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#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
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#define UCMD_RESET (1 << 1) /* controller reset */
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static void usbh1_internal_phy_clock_gate(int on)
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{
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void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
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phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
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__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
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}
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static void usbh1_power_config(void)
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{
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void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
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/*
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* Some phy and power's special controls for host1
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* 1. The external charger detector needs to be disabled
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* or the signal at DP will be poor
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* 2. The PLL's power and output to usb for host 1
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* is totally controlled by IC, so the Software only needs
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* to enable them at initializtion.
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*/
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__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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anatop_base + ANADIG_USB2_CHRG_DETECT);
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__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
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anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
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__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
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ANADIG_USB2_PLL_480_CTRL_POWER |
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ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
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anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
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}
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static int usbh1_phy_enable(void)
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{
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void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
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void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
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USB_H1REGS_OFFSET +
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UH1_USBCMD_OFFSET);
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u32 val;
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/* Stop then Reset */
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val = __raw_readl(usb_cmd);
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val &= ~UCMD_RUN_STOP;
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__raw_writel(val, usb_cmd);
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while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
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;
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val = __raw_readl(usb_cmd);
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val |= UCMD_RESET;
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__raw_writel(val, usb_cmd);
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while (__raw_readl(usb_cmd) & UCMD_RESET)
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;
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/* Reset USBPHY module */
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val = __raw_readl(phy_ctrl);
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val |= USBPHY_CTRL_SFTRST;
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__raw_writel(val, phy_ctrl);
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udelay(10);
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/* Remove CLKGATE and SFTRST */
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val = __raw_readl(phy_ctrl);
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val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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__raw_writel(val, phy_ctrl);
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udelay(10);
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/* Power up the PHY */
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__raw_writel(0, phy_reg + USBPHY_PWD);
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/* enable FS/LS device */
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val = __raw_readl(phy_reg + USBPHY_CTRL);
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val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
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__raw_writel(val, phy_reg + USBPHY_CTRL);
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return 0;
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}
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static void usbh1_oc_config(void)
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{
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void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
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void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
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u32 val;
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val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
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#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
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/* mx6qarm2 seems to required a different setting*/
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val &= ~UCTRL_OVER_CUR_POL;
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#else
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val |= UCTRL_OVER_CUR_POL;
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#endif
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__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
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val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
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val |= UCTRL_OVER_CUR_DIS;
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__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
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}
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int ehci_hcd_init(void)
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{
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struct usb_ehci *ehci;
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enable_usboh3_clk(1);
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mdelay(1);
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/* Do board specific initialization */
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board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
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#if CONFIG_MXC_USB_PORT == 1
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/* USB Host 1 */
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usbh1_power_config();
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usbh1_oc_config();
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usbh1_internal_phy_clock_gate(1);
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usbh1_phy_enable();
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#else
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#error "MXC USB port not yet supported"
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#endif
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ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
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(0x200 * CONFIG_MXC_USB_PORT));
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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hcor = (struct ehci_hcor *)((uint32_t)hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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setbits_le32(&ehci->usbmode, CM_HOST);
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__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mdelay(10);
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return 0;
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}
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int ehci_hcd_stop(void)
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{
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return 0;
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}
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