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ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
This commit is contained in:
SRICHARAN R
Tom Rini
parent
afc2f9dcf1
commit
47abc3df70
5 changed files with 254 additions and 189 deletions
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@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params)
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writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
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if (params->m7_h14 >= 0)
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writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
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if (params->h21 >= 0)
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writel(params->h21, &dpll_regs->cm_div_h21_dpll);
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if (params->h22 >= 0)
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writel(params->h22, &dpll_regs->cm_div_h22_dpll);
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if (params->h23 >= 0)
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writel(params->h23, &dpll_regs->cm_div_h23_dpll);
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if (params->h24 >= 0)
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writel(params->h24, &dpll_regs->cm_div_h24_dpll);
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}
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static inline void do_bypass_dpll(u32 const base)
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@ -319,11 +323,6 @@ void configure_mpu_dpll(void)
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CM_CLKSEL_DCC_EN_MASK);
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}
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setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
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setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
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params = get_mpu_dpll_params(*dplls_data);
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do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
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@ -49,115 +49,127 @@ struct omap_sys_ctrl_regs const **ctrl =
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* Please use this tool for creating the table for any new frequency.
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*/
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/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
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/*
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* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
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* OMAP4460 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
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{175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
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/*
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* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
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* OMAP4430 OPP_TURBO frequency
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*/
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
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/*
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* dpll locked at 1200 MHz - MPU clk at 600 MHz
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* OMAP4430 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
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{50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4460 OPP_NOM frequency */
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
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{619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
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{800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
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{125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4430 ES1 OPP_NOM frequency */
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
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{127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
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{762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
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{635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
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{635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
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{381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
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{254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
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{496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
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{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4430 ES2.X OPP_NOM frequency */
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static const struct dpll_params
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
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{200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
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{800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
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{619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
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{125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
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{400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
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{800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
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{125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
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{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
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{64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */
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{768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */
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{320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */
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{40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */
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{384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */
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{256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */
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{20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */
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{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
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{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
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{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
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{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
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{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
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{931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */
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{931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */
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{665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */
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{727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */
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{931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */
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{931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */
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{291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */
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{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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{49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with 32K clock as source */
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static const struct dpll_params abe_dpll_params_32k_196608khz = {
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750, 0, 1, 1, -1, -1, -1, -1, -1, -1
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750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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struct dplls omap4430_dplls_es1 = {
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|
|
@ -174,8 +186,8 @@ struct dplls omap4430_dplls_es1 = {
|
|||
};
|
||||
|
||||
struct dplls omap4430_dplls = {
|
||||
.mpu = mpu_dpll_params_1600mhz,
|
||||
.core = core_dpll_params_es2_1600mhz_ddr200mhz,
|
||||
.mpu = mpu_dpll_params_1200mhz,
|
||||
.core = core_dpll_params_1600mhz,
|
||||
.per = per_dpll_params_1536mhz,
|
||||
.iva = iva_dpll_params_1862mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
|
|
|
|||
|
|
@ -43,133 +43,160 @@ struct vcores_data const **omap_vcores =
|
|||
struct omap_sys_ctrl_regs const **ctrl =
|
||||
(struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
|
||||
|
||||
/* OPP HIGH FREQUENCY for ES2.0 */
|
||||
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
|
||||
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
|
||||
{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
|
||||
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
|
||||
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
/* OPP NOM FREQUENCY for ES1.0 */
|
||||
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
|
||||
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
/* OPP LOW FREQUENCY for ES1.0 */
|
||||
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
|
||||
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
|
||||
{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
/* OPP LOW FREQUENCY for ES2.0 */
|
||||
static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
|
||||
{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params
|
||||
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
|
||||
{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
|
||||
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
|
||||
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
|
||||
{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
|
||||
{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
|
||||
{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params
|
||||
core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
|
||||
{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
|
||||
{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
|
||||
{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params
|
||||
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
|
||||
{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
|
||||
{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
|
||||
{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
|
||||
{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
|
||||
{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
|
||||
{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params
|
||||
core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
|
||||
{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
|
||||
{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
|
||||
{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
|
||||
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
|
||||
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
|
||||
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
|
||||
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
|
||||
{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
|
||||
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
/* ABE M & N values with sys_clk as source */
|
||||
static const struct dpll_params
|
||||
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
|
||||
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
/* ABE M & N values with 32K clock as source */
|
||||
static const struct dpll_params abe_dpll_params_32k_196608khz = {
|
||||
750, 0, 1, 1, -1, -1, -1, -1, -1, -1
|
||||
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
|
||||
};
|
||||
|
||||
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
|
||||
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
|
||||
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
|
||||
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
|
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
|
||||
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
|
||||
};
|
||||
|
||||
struct dplls omap5_dplls_es1 = {
|
||||
|
|
@ -185,6 +212,19 @@ struct dplls omap5_dplls_es1 = {
|
|||
.usb = usb_dpll_params_1920mhz
|
||||
};
|
||||
|
||||
struct dplls omap5_dplls_es2 = {
|
||||
.mpu = mpu_dpll_params_1100mhz,
|
||||
.core = core_dpll_params_2128mhz_ddr532_es2,
|
||||
.per = per_dpll_params_768mhz_es2,
|
||||
.iva = iva_dpll_params_2330mhz,
|
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
.abe = abe_dpll_params_sysclk_196608khz,
|
||||
#else
|
||||
.abe = &abe_dpll_params_32k_196608khz,
|
||||
#endif
|
||||
.usb = usb_dpll_params_1920mhz
|
||||
};
|
||||
|
||||
struct pmic_data palmas = {
|
||||
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
|
||||
.step = 10000, /* 10 mV represented in uV */
|
||||
|
|
@ -209,16 +249,16 @@ struct vcores_data omap5430_volts = {
|
|||
.mm.pmic = &palmas,
|
||||
};
|
||||
|
||||
struct vcores_data omap5432_volts = {
|
||||
.mpu.value = VDD_MPU_5432,
|
||||
struct vcores_data omap5430_volts_es2 = {
|
||||
.mpu.value = VDD_MPU_ES2,
|
||||
.mpu.addr = SMPS_REG_ADDR_12_MPU,
|
||||
.mpu.pmic = &palmas,
|
||||
|
||||
.core.value = VDD_CORE_5432,
|
||||
.core.value = VDD_CORE_ES2,
|
||||
.core.addr = SMPS_REG_ADDR_8_CORE,
|
||||
.core.pmic = &palmas,
|
||||
|
||||
.mm.value = VDD_MM_5432,
|
||||
.mm.value = VDD_MM_ES2,
|
||||
.mm.addr = SMPS_REG_ADDR_45_IVA,
|
||||
.mm.pmic = &palmas,
|
||||
};
|
||||
|
|
@ -440,20 +480,17 @@ void hw_data_init(void)
|
|||
switch (omap_rev) {
|
||||
|
||||
case OMAP5430_ES1_0:
|
||||
case OMAP5432_ES1_0:
|
||||
*prcm = &omap5_es1_prcm;
|
||||
*dplls_data = &omap5_dplls_es1;
|
||||
*omap_vcores = &omap5430_volts;
|
||||
break;
|
||||
|
||||
case OMAP5432_ES1_0:
|
||||
*prcm = &omap5_es1_prcm;
|
||||
*dplls_data = &omap5_dplls_es1;
|
||||
*omap_vcores = &omap5432_volts;
|
||||
break;
|
||||
|
||||
case OMAP5430_ES2_0:
|
||||
case OMAP5432_ES2_0:
|
||||
*prcm = &omap5_es2_prcm;
|
||||
*dplls_data = &omap5_dplls_es2;
|
||||
*omap_vcores = &omap5430_volts_es2;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -176,9 +176,9 @@
|
|||
|
||||
/* CM_MPU_MPU_CLKCTRL */
|
||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
|
||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
|
||||
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
|
||||
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
|
||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
|
||||
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
|
||||
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
|
||||
|
||||
/* CM_WKUPAON_SCRM_CLKCTRL */
|
||||
#define OPTFCLKEN_SCRM_PER_SHIFT 9
|
||||
|
|
@ -201,12 +201,25 @@
|
|||
#define SMPS_REG_ADDR_8_CORE 0x37
|
||||
|
||||
/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
|
||||
#define VDD_MPU 1000
|
||||
#define VDD_MM 1000
|
||||
/* ES1.0 settings */
|
||||
#define VDD_MPU 1040
|
||||
#define VDD_MM 1040
|
||||
#define VDD_CORE 1040
|
||||
#define VDD_MPU_5432 1150
|
||||
#define VDD_MM_5432 1150
|
||||
#define VDD_CORE_5432 1150
|
||||
|
||||
#define VDD_MPU_LOW 890
|
||||
#define VDD_MM_LOW 890
|
||||
#define VDD_CORE_LOW 890
|
||||
|
||||
/* ES2.0 settings */
|
||||
#define VDD_MPU_ES2 1060
|
||||
#define VDD_MM_ES2 1025
|
||||
#define VDD_CORE_ES2 1040
|
||||
|
||||
#define VDD_MPU_ES2_HIGH 1250
|
||||
#define VDD_MM_ES2_OD 1120
|
||||
|
||||
#define VDD_MPU_ES2_LOW 880
|
||||
#define VDD_MM_ES2_LOW 880
|
||||
|
||||
/* Standard offset is 0.5v expressed in uv */
|
||||
#define PALMAS_SMPS_BASE_VOLT_UV 500000
|
||||
|
|
|
|||
|
|
@ -426,8 +426,10 @@ struct dpll_params {
|
|||
s8 m5_h12;
|
||||
s8 m6_h13;
|
||||
s8 m7_h14;
|
||||
s8 h21;
|
||||
s8 h22;
|
||||
s8 h23;
|
||||
s8 h24;
|
||||
};
|
||||
|
||||
struct dpll_regs {
|
||||
|
|
@ -441,9 +443,11 @@ struct dpll_regs {
|
|||
u32 cm_div_m5_h12_dpll;
|
||||
u32 cm_div_m6_h13_dpll;
|
||||
u32 cm_div_m7_h14_dpll;
|
||||
u32 reserved[3];
|
||||
u32 reserved[2];
|
||||
u32 cm_div_h21_dpll;
|
||||
u32 cm_div_h22_dpll;
|
||||
u32 cm_div_h23_dpll;
|
||||
u32 cm_div_h24_dpll;
|
||||
};
|
||||
|
||||
struct dplls {
|
||||
|
|
|
|||
Loading…
Reference in a new issue