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mx5: lowlevel_init.S: Split init_clock macro
init_clock is currently shared between mx51 and mx53 and it contains lots of ifdef's which makes it really hard to follow the code. Split the init_clock between mx51 and mx53 to allow easier readability. No functional changes are made. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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5676f598e7
commit
758c344945
1 changed files with 65 additions and 30 deletions
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@ -162,9 +162,9 @@ setup_pll_func:
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.endm
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.macro init_clock
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#if defined (CONFIG_MX51)
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ldr r0, =CCM_BASE_ADDR
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#if defined(CONFIG_MX51)
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/* Gate of clocks to the peripherals first */
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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@ -190,21 +190,6 @@ setup_pll_func:
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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#else
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r4, [r0, #CLKCTL_CCGR1]
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str r4, [r0, #CLKCTL_CCGR2]
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str r4, [r0, #CLKCTL_CCGR3]
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str r4, [r0, #CLKCTL_CCGR7]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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ldr r1, =0x00FFF030
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str r1, [r0, #CLKCTL_CCGR5]
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ldr r1, =0x0F00030F
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str r1, [r0, #CLKCTL_CCGR6]
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#endif
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/* Switch ARM to step clock */
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mov r1, #0x4
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@ -217,7 +202,6 @@ setup_pll_func:
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setup_pll PLL1_BASE_ADDR, 800
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#endif
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#if defined(CONFIG_MX51)
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setup_pll PLL3_BASE_ADDR, 665
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/* Switch peripheral to PLL 3 */
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@ -234,7 +218,7 @@ setup_pll_func:
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str r1, [r0, #CLKCTL_CBCDR]
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ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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#endif
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setup_pll PLL3_BASE_ADDR, 216
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/* Set the platform clock dividers */
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@ -244,21 +228,17 @@ setup_pll_func:
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ldr r0, =CCM_BASE_ADDR
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#if defined(CONFIG_MX51)
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/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
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ldr r3, [r4, #ROM_SI_REV]
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cmp r3, #0x10
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movls r1, #0x1
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movhi r1, #0
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#else
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mov r1, #0
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#endif
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str r1, [r0, #CLKCTL_CACRR]
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/* Switch ARM back to PLL 1 */
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str r4, [r0, #CLKCTL_CCSR]
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#if defined(CONFIG_MX51)
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/* setup the rest */
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/* Use lp_apm (24MHz) source for perclk */
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ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
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@ -266,7 +246,6 @@ setup_pll_func:
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/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
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ldr r1, =CONFIG_SYS_CLKTL_CBCDR
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str r1, [r0, #CLKCTL_CBCDR]
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#endif
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/* Restore the default values in the Gate registers */
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ldr r1, =0xFFFFFFFF
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@ -277,17 +256,72 @@ setup_pll_func:
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str r1, [r0, #CLKCTL_CCGR4]
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str r1, [r0, #CLKCTL_CCGR5]
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str r1, [r0, #CLKCTL_CCGR6]
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#if defined(CONFIG_MX53)
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str r1, [r0, #CLKCTL_CCGR7]
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#endif
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#if defined(CONFIG_MX51)
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/* Use PLL 2 for UART's, get 66.5MHz from it */
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ldr r1, =0xA5A2A020
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str r1, [r0, #CLKCTL_CSCMR1]
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ldr r1, =0x00C30321
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str r1, [r0, #CLKCTL_CSCDR1]
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#elif defined(CONFIG_MX53)
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/* make sure divider effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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str r4, [r0, #CLKCTL_CCDR]
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/* for cko - for ARM div by 8 */
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mov r1, #0x000A0000
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add r1, r1, #0x00000F0
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str r1, [r0, #CLKCTL_CCOSR]
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#else /* CONFIG_MX53 */
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ldr r0, =CCM_BASE_ADDR
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/* Gate of clocks to the peripherals first */
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r4, [r0, #CLKCTL_CCGR1]
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str r4, [r0, #CLKCTL_CCGR2]
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str r4, [r0, #CLKCTL_CCGR3]
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str r4, [r0, #CLKCTL_CCGR7]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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ldr r1, =0x00FFF030
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str r1, [r0, #CLKCTL_CCGR5]
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ldr r1, =0x0F00030F
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str r1, [r0, #CLKCTL_CCGR6]
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/* Switch ARM to step clock */
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mov r1, #0x4
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str r1, [r0, #CLKCTL_CCSR]
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setup_pll PLL1_BASE_ADDR, 800
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setup_pll PLL3_BASE_ADDR, 216
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/* Set the platform clock dividers */
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ldr r0, =ARM_BASE_ADDR
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ldr r1, =0x00000725
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str r1, [r0, #0x14]
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ldr r0, =CCM_BASE_ADDR
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mov r1, #0
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str r1, [r0, #CLKCTL_CACRR]
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/* Switch ARM back to PLL 1 */
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str r4, [r0, #CLKCTL_CCSR]
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/* Restore the default values in the Gate registers */
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ldr r1, =0xFFFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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str r1, [r0, #CLKCTL_CCGR4]
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str r1, [r0, #CLKCTL_CCGR5]
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str r1, [r0, #CLKCTL_CCGR6]
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str r1, [r0, #CLKCTL_CCGR7]
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/* Switch peripheral to PLL2 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x00808145
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@ -306,7 +340,7 @@ setup_pll_func:
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and r1, r1, #0xffffffc0
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orr r1, r1, #0x0a
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str r1, [r0, #CLKCTL_CSCDR1]
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#endif
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/* make sure divider effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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@ -318,6 +352,7 @@ setup_pll_func:
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mov r1, #0x000A0000
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add r1, r1, #0x00000F0
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str r1, [r0, #CLKCTL_CCOSR]
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#endif /* CONFIG_MX53 */
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.endm
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.macro setup_wdog
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