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17361 commits

Author SHA1 Message Date
Neil Armstrong
640192d04f ARM: meson: add support for Odroid Go Ultra
This adds initial support for the Hardkernel Odroid Go Ultra.

The Odroid Go Ultra is a portable gaming device with the following
characteristics:
- Amlogic S922X SoC
- RK817 & RK818 PMICs
- 2GiB LPDDR4
- On board 16GiB eMMC
- Micro SD Card slot
- 5inch 854×480 MIPI-DSI TFT LCD
- Earphone stereo jack, 0.5Watt 8Ω Mono speaker
- Li-Polymer 3.7V/4000mAh Battery
- USB-A 2.0 Host Connector
- x16 GPIO Input Buttons
- 2x ADC Analog Joysticks
- USB-C Port for USB2 Device and Charging

The following are not yet handled:
- Battery RK818 Gauge and Charging
- 5inch 854×480 MIPI-DSI TFT LCD

Link: https://lore.kernel.org/r/20230119-u-boot-odroid-go-ultra-v1-2-f96bab9db396@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20 16:27:40 +01:00
Neil Armstrong
2acbc33b3d ARM: dts: sync Amlogic ARM64 DT from v6.2-rc1
This syncs the Amlogic G12A, G12B & SM1 base DT + the
Odroid Go Ultra DT from Linux v6.2-rc1 from commmit [1].

[1] 1b929c02afd3 ("Linux 6.2-rc1")

Link: https://lore.kernel.org/r/20230119-u-boot-odroid-go-ultra-v1-1-f96bab9db396@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20 16:27:40 +01:00
Neil Armstrong
e327e2affd ARM: meson: switch AXG & GX dwc2 otg to DM
With CONFIG_DM_USB_GADGET=y, we no longer need any board_usb_*() logic
because:
* the dwc2 driver is DM compatible, and handles its own clock enabling
* the dwc3-meson-gxl glue drivers handles "force mode switching"

Remove all mach-meson gx & axg usb code and enable CONFIG_DM_USB_GADGET.

Note: Only configs having both CONFIG_USB_DWC3_MESON_GXL=y *and*
      USB_GADGET_DWC2_OTG=y have been updated.

Thanks for the original work from Mattijs at [1]

[1] https://lore.kernel.org/all/20221024-meson-dm-usb-v1-2-2ab077a503b9@baylibre.com/

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20230117-u-boot-usb-gxl-otg-dm-v1-2-2853f6d75b06@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-20 16:21:31 +01:00
Tom Rini
53c47c59e6 convert rockchip to use binman
patman fix for checkpatch
 binman optional entries, improved support for ELF symbols
 trace improvements
 minor fdt refactoring
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Merge tag 'dm-pull-18jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm

convert rockchip to use binman
patman fix for checkpatch
binman optional entries, improved support for ELF symbols
trace improvements
minor fdt refactoring
2023-01-19 09:46:57 -05:00
Simon Glass
12c3e948ee rockchip: Drop the FIT generator script
This is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 14:55:40 -07:00
Simon Glass
e0c0efff2a rockchip: Support building the all output files in binman
Add the required binman images to replace the Makefile rules which are
currently used. This includes subsuming:

   - tpl/u-boot-tpl-rockchip.bin if TPL is enabled
   - idbloader.img if either or both of SPL and TPL are enabled
   - u-boot.itb if SPL_FIT is enabled
   - u-boot-rockchip.bin if SPL is used, either using u-boot.itb when
     SPL_FIT is enabled or u-boot.img when it isn't

Note that the intermediate files are dropped with binman, since it
producing everything in one pass. This means that
tpl/u-boot-tpl-rockchip.bin is not created, for example.

Note that for some 32-bit rk3288 boards, rockchip-optee.dtsi is included.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 14:55:39 -07:00
Simon Glass
4170dd9ec0 rockchip: Use multiple-images for rk3399
Enable multiple-images so we can generate more than one image. Also
add a comment for the end of the #if block.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:50:01 -07:00
Simon Glass
b2412dd5de rockchip: Enable bootstage on rockpro64
This board is useful for benchmarking overall U-Boot performance. Enable
the bootstage feature so we get a report.

Since this returns to the boot rom before finishing executing
board_init_r() in SPL, add a few bootstage calls so that we can collect
timing from TPL.

For the stash region, use a portion of SRAM, 64KB below the stack top.
This allows the TPL image to be up to nearly 120KB (it is typically about
64KB). SPL normally runs from SDRAM at 0, so can use the same stash
region.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:13 -07:00
Simon Glass
d81d17637a arm: Support trace on armv8
Use the notrace attribute so that timer functions can be used when
tracing. This is required to avoid infinite loops when recording a trace.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:13 -07:00
Simon Glass
33c60a38bb trace: Use notrace for short
The attribute syntax is quite verbose. Use the macro provided for this
purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:12 -07:00
Tom Rini
448e2b6327 event: Correct dependencies on the EVENT framework
The event framework is just that, a framework. Enabling it by itself
does nothing, so we shouldn't ask the user about it. Reword (and correct
typos) around this the option and help text. This also applies to
DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be
visible to the user to select, when EVENT is selected.

With this, it's time to address the larger problems. When functionality
uses events, typically via EVENT_SPY, the appropriate framework then
must be select'd and NOT imply'd. As the functionality will cease to
work (and so, platforms will fail to boot) this is non-optional and
where select is appropriate. Audit the current users of EVENT_SPY to
have a more fine-grained approach to select'ing the framework where
used. Also ensure the current users of event_register and also select
EVENT_DYNAMIC.

Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com>
Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Fixes: 42fdcebf85 ("event: Convert misc_init_f() to use events")
Fixes: c5ef202557 ("dm: fix DM_EVENT dependencies")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-18 12:46:13 -05:00
Tom Rini
5b958dea5c Merge branch '2022-01-16-bootstd-updates'
To quote the author:
So far standard boot lacks a boot menu, although it is possible to create
a rudimentary one using the existing 'bootmenu' command.

Even then, this text-based menu offer only basic functionality and does
not take full advantage of the displays which are common on many devices.

This series provides a 'bootflow menu' command which allows the user to
select from the available bootflows. An attempt is made to show the name
of the available operating systems, by reading more information into the
bootflow. A logo can be read also, where supported, so that this can be
presented to the user when an option is highlighted.

Full use is made of TrueType fonts, if enabled. For cases where only a
serial console is available, it falls back to a simple text-based menu.

All of this is implementing using a new 'expo' construct, a collection of
scenes (like menu screens) which can be navigated by the user to view
information and select options. This is fairly general and should be able
to cope with a wider array of use cases, with less hacking of the menu
code, such as is currently needed for CMD_BOOTEFI_BOOTMGR.

Of course it would be possible to enhance the existing menu rather than
creating a new setup. Instead it seems better to make the existing menu
use expo, if code space permits. It avoids the event-loop problem and
should be more extensible, given its loosely coupled components and use of
IDs instead of pointers. Further motivation is provided in the
documentation.

For now the CLI keypress-decoding code is split out to be used by the new
menu. The key codes defined by menu.h are reused also.

This is of course just a starting point. Some ideas for future work are
included in the documentation.
2023-01-17 08:55:40 -05:00
Tom Rini
6d03688e75 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- kirkwood: Convert to DM Serial for various Kirkwood boards (Tony)
- orion-timer: Fix problem in early_init_done() (Stefan)
2023-01-17 08:10:56 -05:00
Mattijs Korpershoek
b96640cbfb ARM: meson: g12a: switch dwc2 otg to DM
With CONFIG_DM_USB_GADGET=y, we no longer need any board_usb_*() logic
because:
* the dwc2 driver is DM compatible, and handles its own clock enabling
* the dwc3-meson-g12a glue drivers handles "force mode switching"

Remove all mach-meson/g12a usb code and enable CONFIG_DM_USB_GADGET.

Note: Only configs having both CONFIG_USB_DWC3_MESON_G12A=y *and*
      USB_GADGET_DWC2_OTG=y have been updated.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20221024-meson-dm-usb-v1-2-2ab077a503b9@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-17 09:27:17 +01:00
Tony Dinh
bee23537ba arm: kirkwood: Convert to DM Serial for various Kirkwood boards
For Kirkwood boards, it is necessary to have early malloc in DRAM area
when Driver Model for Serial is enabled. Please see Michael's patch here:
https://lore.kernel.org/u-boot/20220817193809.1059688-20-michael@walle.cc/

This patch enables the early malloc in DRAM for all Kirkwood boards.
Note that this will work for boards that have either non-DM serial
and DM_SERIAL. Also, add the CONFIG_KIRKWOOD_COMMON option to enable
DM_SERIAL as a common option for boards that have been tested.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2023-01-17 07:08:42 +01:00
Simon Glass
30f3333d88 image: Move common image code to image_board and command
We should use the cmd/ directory for commands rather than for common code
used elsewhere in U-Boot. Move the common 'source' code into
image-board.c to achieve this.

The image_source_script() function needs to call run_command_list()  so
seems to belong better in the command library. Move and rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-16 18:26:50 -05:00
Ashok Reddy Soma
724379d9af xilinx: versal-net: Add support for timer and start it
Add support for starting timer by setting up time stamp generator
registers. This is done only for EL3 i.e. mini U-Boot case.
For other cases, it will be done TF-A.

Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they
can be tuned as required.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com
2023-01-16 15:34:37 +01:00
Quentin Schulz
c925be73a0 rockchip: add support for PX30 Ringneck SoM on Haikou Devkit
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip
PX30 in a micro Qseven-compatible form-factor.

PX30-µQ7 features:
        * CPU: quad-core Cortex-A35
        * DRAM: 2GB dual-channel
        * eMMC: onboard eMMC
        * SD/MMC
        * TI DP83825I 10/100Mbps PHY
        * USB:
                * USB2.0 dual role port
                * 3x USB2.0 host via onboard USB2.0 hub
        * Display: MIPI-DSI
        * Camera: MIPI-CSI
        * onboard 2.4GHz WiFi + Bluetooth module
        * Companion Controller: on-board additional microcontroller
	  (STM32 Cortex-M0 or ATtiny):
                * RTC
                * fan controller
                * CAN (only STM32)

The non-U-Boot DTS files are imported from Linux v6.2-rc2.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
2c9f077064 arm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1
Sync the px30 dtsi from Linux kernel v6.1.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
600e0177e7 rockchip: px30: insert u-boot, spl-boot-device into U-Boot device tree
It is possible to boot U-Boot proper from a different storage medium
than the one used by the BOOTROM to load the SPL. This information is
stored in the u-boot,spl-boot-device Device Tree property and is
accessible from U-Boot proper so that it has knowledge at runtime where
it was loaded from.

Let's add support for this feature for px30.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
3898237384 rockchip: px30: list possible SPL boot devices
BOOTROM sets a bit in a CPU register so that the software can know from
where the first stage bootloader was booted. One use case for this is to
specify the default loading medium for U-Boot proper to match the one
used by the BOOTROM to load the SPL (same-as-spl in
u-boot,spl-boot-order).

Let's create the mapping between BOOTROM value and Device Tree node
names for MMC devices.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
e53856aaf4 rockchip: px30: fix possibly unused grf and cru variables
The grf and cru are only used when no UART base is provided by the user
(defaults to UART2) or for UART1, UART3 and UART5 to be used for the
debug UART. Therefore, let's surround those variable definitions with
the proper checks.

This wasn't an issue before support for UART0 was added, because all
cases were using cru and grf. UART0 only uses pmucru so there's a need
to not define those variables anymore.

Fixes: d0af506625 ("rockchip: px30: support debug uart on UART0")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Peter Robinson
5a42fd0258 rockchip: Add initial support for the PINE64 Pinephone Pro
The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.

Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-16 18:01:11 +08:00
Peter Robinson
30a6d14a97 arm64: dts: rk3399: Add upstream Pinephone Pro dts
Initial support for the PinePhone Pro has now landed upstream in
Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
b8f1ca9540 board: rockchip: Add Edgeble Neu2 IO Board
Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
43e89241f3 ARM: dts: rockchip: Add rv1126-u-boot.dtsi
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.

Both eMMC and SD boot are tested in Edgeble Neu2 SoM.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
0736dad4ed ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO
Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
d12471c7be ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.

General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT

Industrial grade (-40 °C to +85 °C) version of the same class of module
called Neu2k powered with Rockchip RV1126K.

Neu2 needs to mount on top of Edgeble IO boards for creating complete
platform solutions.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
c6154677c8 arm: rockchip: rv1126: Set dram area unsecure for SPL
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
ffb191e458 arm: rockchip: Add RV1126 arch core support
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04
2023-01-16 18:01:11 +08:00
Jagan Teki
2204a8c90a ARM: dts: rockchip: Add Rockchip RV1126 SoC
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.

It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.

This patch add basic core dtsi support.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
3fc0dee585 ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
Add pinctrl definitions for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
43cecf7234 arm: rockchip: Add grf header for rv1126
Add GRF header for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
f4ca986e29 arch: rockchip: Add cru header for rv1126
Add clock and reset unit header include for rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
e869b3485c ram: rockchip: Add rv1126 ddr driver support
Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jagan Teki
5ab30c3176 ram: rockchip: Update ddr pctl regs for px30
Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Jagan Teki
29c3148974 ram: rockchip: Compute ddr capacity based on grf split
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Quentin Schulz
ccaa55fb6e rockchip: puma-rk3399: sync DTS with Linux kernel next-20221114
This synchronizes the Device Trees related to Puma RK3399 SoM with Linux
kernel next-20221114 to include two important changes pertaining to
eMMC and SD card instability.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Quentin Schulz
4b56446002 rockchip: px30: make watchdog and tsadc trigger a first global reset
By default, the PX30 is configured for watchdog and tsadc to trigger a
second global reset which is a more permissive reset than first global
reset.

From TRM part 1 "2.3 System Reset Solution":
glb_srstn_1 will reset the all logic, and
glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs.

This enforces that the watchdog and tsadc trigger glb_srstn_1 as
similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?),
TF-A and Coreboot.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Hai Pham
0fe4366c9a ARM: renesas: condor: switch eMMC bus to 1V8
The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND
array and the VCCQ supplies the bus. On Condor, the VCC is connected to
3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux
to match the bus, which is always operating in 1.8V mode.

Based on Linux commit 69efe4bbeda50745 ("arm64: dts: renesas: condor:
Switch eMMC bus to 1V8") from Wolfram Sang

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-01-14 14:10:12 +01:00
Marek Vasut
3405cfa29d ARM: dts: renesas: condor: Enable SPI NOR fast-read
This board requires SPI NOR fast-read, otherwise the SPI NOR
access returns corrupted data. Enable the fast-read explicitly
in DT as it has been disabled in the MTD subsystem by commit
d008190920 ("mtd: spi-nor: Mask out fast read if not requested in DT")

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-14 14:10:12 +01:00
Tom Rini
fe4c21de4f Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
 Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
 stm32mp157a-dk1-scmi-u-boot.dtsi update
 Add support of OP-TEE and STM32MP13x in bsec driver
 ECDSA various fixes for stm32mp
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Merge tag 'u-boot-stm32-20230113' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
stm32mp157a-dk1-scmi-u-boot.dtsi update
Add support of OP-TEE and STM32MP13x in bsec driver
ECDSA various fixes for stm32mp
2023-01-13 09:56:19 -05:00
Marek Vasut
0e86f813f4 ARM: stm32: Make ECDSA authentication available to U-Boot
With U-Boot having access to ROM API call table, it is possible to use
the ROM API call it authenticate e.g. signed kernel fitImages using the
BootROM ECDSA support. Make this available by pulling the ECDSA BootROM
call support from SPL-only guard.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
6eea541514 ARM: stm32: Pass ROM API table pointer to U-Boot proper
The ROM API table pointer is no longer accessible from U-Boot, fix
this by passing the ROM API pointer through. This makes it possible
for U-Boot to call ROM API functions to authenticate payload like
signed fitImages.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
dbeaca79b7 ARM: stm32: Factor out save_boot_params
The STM32MP15xx platform currently comes with two incompatible
implementations of save_boot_params() weak function override.
Factor the save_boot_params() implementation into common cpu.c
code and provide accessors to read out both ROM API table address
and DT address from any place in the code instead.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
bbafbc044d ARM: stm32: Fix ECDSA authentication with Dcache enabled
In case Dcache is enabled while the ECDSA authentication function is
called via BootROM ROM API, the MMU tables are set up and the BootROM
region is not marked as executable, so an attempt to run code from it
results in a hang. Mark the BootROM region as executable as suggested
by Patrick to prevent the hang.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Heinrich Schuchardt
7e808fcc97 efi_loader: add .rela sections to .text on arm64
_relocate() needs the information in .rela* for self relocation
of the EFI binary.

Fixes: d7ddeb66a6 ("efi_loader: fix building aarch64 EFI binaries")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-13 09:09:07 +01:00
Sean Anderson
0998a20cfc misc: fs_loader: Add function to get the chosen loader
The fs_loader device is used to pull in settings via the chosen node.
However, there was no library function for this, so arria10 was doing it
explicitly. This function subsumes that, and uses ofnode_get_chosen_node
instead of navigating the device tree directly. Because fs_loader pulls
its config from the environment by default, it's fine to create a device
with nothing backing it at all. Doing this allows enabling
CONFIG_FS_LOADER without needing to modify the device tree.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-12 14:06:15 -05:00
Kshitiz Varshney
81ceb1695a Added dcp_rng driver initialization code
This commit initializes dcp_rng device driver inside
arch_misc_init() function.

Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2023-01-12 11:25:46 -05:00
Patrick Delaunay
a33885ff49 stm32mp: Add support of STM32MP13x in bsec driver
Add support for "st,stm32mp13-bsec" for STM32MP13x in the
bsec driver based on OP-TEE pseudo TA STM32MP BSEC.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
33a909a42a stm32mp: Add OP-TEE support in bsec driver
When OP-TEE is used, the SMC for BSEC management are not available and
the STM32MP BSEC pseudo TA must be used (it is mandatory for STM32MP13
and it is a new feature for STM32MP15x).

The BSEC driver try to open a session to this PTA BSEC at probe
and use it for OTP read or write access to fuse or to shadow.

This patch also adapts the commands stm32key and stboard to handle
the BSEC_LOCK_PERM lock value instead of 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
27bad4e7fc stm32mp: cosmetic: Update of bsec driver
Remove unnecessary return in stm32mp_bsec_write_lock and replace tab
by space for plat_auto opts.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
6e391c7d5f ARM: dts: stm32: Add timer interrupts on stm32mp15
The timer units in the stm32mp15x CPUs have interrupts, depending on the
timer flavour either one "global" or four dedicated ones. Add the irqs
to the timer units on stm32mp15x.

Sync the DT Files with linux kernel v6.1 and with commit a9b70102253ce
("ARM: dts: stm32: Add timer interrupts on stm32mp15")

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Patrick Delaunay
126aa470d6 ARM: dts: stm32mp15: fix typo in stm32mp15xx-dkx.dtsi
Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Patrick Delaunay
d1d56638c4 ARM: dts: stm32mp15: remove clksrc include in SCMI dtsi file
The include file stm32mp1-clksrc.h is not necessary for the SCMI STM32MP15
dtsi files as the clock tree is not defined in the U-Boot SCMI device tree;
these SCMI device tree only support TFABOOT with stm32mp15_defconfig,
SPL with the basic boot defconfig is not supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Fabrice Gasnier
214d6e7e68 ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1
Add support for USB2514B onboard hub on stm32mp157c EV1 board. The HUB
is supplied by a 3v3 PMIC regulator.

[backport from linux ad9591b01d24]
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-12 16:19:53 +01:00
Fabrice Gasnier
79da4074dd ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1
phy-stm32-usbphyc bindings uses a connector node with vbus-supply
property.

[backport from linux 43e55d778a6b]
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:08:43 +01:00
Ville Skyttä
fe482b886d Use grep -E or plain grep instead of egrep
`egrep` has been deprecated in GNU grep since 2007,
and since 3.8 it emits obsolescence warnings:
https://git.savannah.gnu.org/cgit/grep.git/commit/?id=a9515624709865d480e3142fd959bccd1c9372d1
Acked-by: Dhruva Gole <d-gole@ti.com>
2023-01-11 15:02:24 -05:00
Luca Ceresoli
66b39c1a8c arm64: zynqmp: remove Avnet UltraZed-EV Starter Kit
Nobody seems interested and able to keep this board supported, and
xilinx_zynqmp_virt_defconfig is supposed to be enough for any zynqmp board.

See the discussion at: https://lore.kernel.org/u-boot/CAPnjgZ3hHbyiFf=_Lp-Wz_XOWBkV-3vK4Q3xp=7bcERw-spNpA@mail.gmail.com/T/#m76d726f1ab3f7074c8105c9a2af2110ac7d18708

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Link: https://lore.kernel.org/r/20230111082554.1930782-1-luca.ceresoli@bootlin.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-11 10:43:39 +01:00
Andrew Davis
367c9e0614 ARM: omap3: evm: Name this directory omap3evm
Before this was named just evm, which doesn't match the naming
of the other TI board file directory and makes it look like a
common directory for evms. Name this omap3evm.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Derald Woods <woods.technical@gmail.com>
2023-01-10 15:39:08 -05:00
Dzmitry Sankouski
971ccee2fb SoC: sdm845: find and save KASLR to env variables
KASLR address is needed to boot fully functional Android.
KASLR is set by primary bootloader, and since u-boot is used
as a secondary bootloader(replacing kernel) on sdm845 platform,
KASLR may be found by comparing memory chunks at relocaddr over
supposed KASLR range.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
b672e85810 arm: mach-k3: copy bootindex to OCRAM for main domain SPL
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.

One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.

The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Martyn Welch
7c34b71a42 arm64:mach-k3 am625_init: Correct boot mode detection
The boot mode detection assumes that BOOT_DEVICE_MMC2 should always
result in MMCSD_MODE_FS, but MMCSD_MODE_RAW is also a valid option for
this port.

The current logic also avoids looking at the bootmode pin strapping,
which should be the primary means of determining whether a device is
being booted in MMCSD_MODE_EMMCBOOT mode.

Switch around the logic to check the boot mode to determine whether the
eMMC boot mode is expected or MMC/SD boot mode. From there we can look
at the boot mode config if in MMC/SD boot mode to determine whether to
attempt RAW or FS based booting.

This change allows U-Boot to also be successfully booted from RAW
offsets in addition to from a filesystem.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2023-01-10 15:39:06 -05:00
Sjoerd Simons
39248d3260 arm: dts: k3-am625-sk: Enable first ethernet port
The K3 am625 sk EVM has two ethernet ports; Enable the first one for
usage in u-boot.

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
2023-01-10 15:39:06 -05:00
Jim Liu
7ee1c4d1d1 pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-01-10 15:39:06 -05:00
Alexey Romanov
311106a1c6 arm/mach-meson: move smc commands in cmd/meson
It is incorrect to keep commands in the arch/ folder.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230110105650.54580-3-avromanov@sberdevices.ru
[narmstrong: moved after cmd/sound in index.rst]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-10 15:27:17 +01:00
Alexey Romanov
12d7827349 asm/arch-meson: add missing meson_sm_write_efuse signature
This function can be used by other modules. Also add comments.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20230110105650.54580-2-avromanov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-10 15:25:48 +01:00
Michal Simek
67ac851488 arm64: zynqmp: Remove unused snps,refclk_fladj property
The commit c55ac51a55 ("usb: dwc3: Program GFLADJ") hopefully fixed
issues around fladj logic. This DT property was used in Xilinx stack only
that's why remove because it is not needed anymore.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9bdbd1156b19e28cdebeca29149268b0579a8b6a.1670855257.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Harini Katakam
fd5f2718d3 arm64: zynqmp: Enable TI phy reset via GPIO
Add DT property to support reset of TI PHY connected to GEM.
This is present in RevA DT but needs to be extended RevB/1.0/1.1
versions which are built on top.

Fixes: 2b1db7b18c ("arm64: zynqmp: Wire GEM reset gpio")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b093616ddea269043cbbb1e3806644d5a4b23be.1670854455.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Harini Katakam
4664a63cc7 arm64: zynqmp: Describe TI phy as ethernet phy ID on ZCU102 RevB & up
TI phy requires a reset before PHY address detection to make sure
correct strapping via MIO is detected. Facilitate the same using
ethernet-phy-id compatible string. GPIO reset entry will be added in
a separate commit.
This support is present in RevA but needs to be extended to RevB/1.0/1.1
versions which are built on top.

Fixes: 13622c7a9d ("arm64: zynqmp: Describe TI phy as ethernet-phy-id")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6d500a83a787316353d4b26c75d1b51d29e3730e.1670854455.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
ef440787da arm64: zynqmp: Remove unused USB DT properties
xlnx,usb-polarity, xlnx,usb-reset-mode and snps,mask_phy_reset are not
documented in dt binding and also there is no code associated with them
that's why remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/369139fafa1745252ef687e31aebf6bcc2080a32.1670853972.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
a30a3ec888 arm64: zynqmp: Remove id from usb node name
There is no reason to have number in usb node name. This is also sync up
patch with upstream kernel.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b13db34031af88a5738d2ec2e05d2498ea8c869.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
b1d3e7fd9a arm64: zynqmp: Align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).
It is based on kernel commit (228e8a88b1915a2b467c83d8d0976605f1272fae).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae23999097553acb21dfca9288a913bb8b24587a.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
8dfdb6958b arm64: zynqmp: Fix AMS device tree node
Aligned node description with the Linux kernel. Node has been added by
kernel commit (271c1fa01c2307cf74f4656390d6299991119c3e).

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/74188b64cf615100345d058e026cb0d2de0e089b.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
e6a01d5102 arm64: zynqmp: Added GEM reset definitions
The Cadence GEM/MACB driver now utilizes the platform-level reset on the
ZynqMP platform. Add reset definitions to the ZynqMP platform device
tree to allow this to be used.
Linux upstream commit (e461bd6f43f4e568f7436a8b6bc21c4ce6914c36).

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/14e3637735dbc626659e96d142f04a63398362f8.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Michal Simek
2a5f7fd30c arm64: zynqmp: Sync #dma-cells property location
Sync property location with Linux kernel done by Linux commit
(1ff2d58e60c8093e9be935b1f191341c0cda957a).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e09ad90ea610a81528ef5ecbc931bc9791b1c653.1670590595.git.michal.simek@amd.com
2023-01-10 08:15:54 +01:00
Tom Rini
cebdfc22da Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-09 11:30:08 -05:00
Heinrich Schuchardt
4bba71ff83 efi_loader: make .data section of *_efi.so files RW
When building with binutils 2.39 warnings

    *_efi.so has a LOAD segment with RWX permissions

occur.

Use SHF_WRITE | SHF_ALLOC as section flags for the .data section.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-06 22:27:30 +01:00
Tom Rini
b82f12b642 First set of u-boot-at91 features for the 2023.04 cycle
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Merge tag 'u-boot-at91-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2023.04 cycle:

This feature set includes the new DM-based NAND flash driver (old non-DM
driver is still kept for backwards compatibility), and the move to DM
NAND flash driver for sam9x60ek board. Feature set also includes
devicetree alignment for sama7g5 with Linux, devicetree alignment on USB
with Linux for all boards (sama5, sam9x60), chip id for sama7g5, minor
configs and tweaks.
2023-01-06 11:53:26 -05:00
Tom Rini
9ddcdcc03c - stm32mp: Fix board_get_usable_ram_top(): workaround to avoid issue after the
commit 777aaaa706 ("common/memsize.c: Fix get_effective_memsize() to check
   for overflow") because the effective DDR effective size is reduce by 4KiB
   and sometime the board hang on boot
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Merge tag 'u-boot-stm32-20230106' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- stm32mp: Fix board_get_usable_ram_top(): workaround to avoid issue after the
  commit 777aaaa706 ("common/memsize.c: Fix get_effective_memsize() to check
  for overflow") because the effective DDR effective size is reduce by 4KiB
  and sometime the board hang on boot
2023-01-06 08:16:15 -05:00
Adam Ford
edd9c891d2 arm: dts: rz-g2-beacon-u-boot: Fix QSPI Regression
The QSPI is accessed via the RPC-IF, but the compatible flags
previously used a different name.  This compatibel name was changed
which broke the ability to access the QSPI.  Fix this by removing
the custom naming reference.

Fixes: 68083b897b ("renesas: Fix RPC-IF compatible values")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-06 08:14:19 -05:00
Fabio Estevam
f8548ce0e0 imx7d-pico: Fix the name of the u-boot.dtsi file
Since commit 2f96d4dd95 ("imx7s/d: synchronise device trees with linux")
the imx7d-pico board no longer boots.

The reason is that prior to the above commit there was an explicit
inclusion of arch/arm/dts/imx7d-pico-u-boot.dtsi inside imx7d-pico.dtsi.

After the syncing with the Linux upstream dtsi, this u-boot.dtsi inclusion
is gone and the board fails to boot.

U-Boot uses the imx7d-pico-pi.dtb file, so rename the u-boot.dtsi to
imx7d-pico-pi-u-boot.dtsi which gets included automatically by U-Boot
standard make logic and makes the board boot again.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-01-06 08:14:19 -05:00
Marek Vasut
a2e0b041d6 arm: stm32mp: Fix board_get_usable_ram_top() again
Do not access gd->ram_size and assume this is actual valid RAM size. Since commit
777aaaa706 ("common/memsize.c: Fix get_effective_memsize() to check for overflow")
the RAM size may be less than gd->ram_size , call get_effective_memsize() to get
the limited value instead.

The aforementioned commit makes STM32MP15xx boards with 1 GiB of DRAM
at 0xc0000000 hang on boot, which is a grave defect.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-06 11:02:17 +01:00
Cristian Birsan
11c037ab92 ARM: at91: add sama7 SFR definitions
Special Function Registers(SFR) definitions for SAMA7 product family.

Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:06:09 +02:00
Sergiu Moga
e4ad98d67b ARM: dts: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes
Add the pinctrl nodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
20bc95f8c8 ARM: dts: sama5d2_icp: Add pinctrl nodes for USB related DT nodes
Add the pinctrl subnodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
3cd06bfa96 ARM: dts: sama7g5ek: Add pinctrl, gpio and phy properties for USB
Add the required pinctrl, gpio and phy properties required by the
USB DT nodes of the sama7g5ek boards. Since these have not yet been
defined in upstream Linux, place them in the U-Boot specific DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
851960e591 ARM: dts: sama7g5: Add USB and UTMI DT nodes
Define the USB and UTMI DT nodes for the sama7g5 SoC's. Since these have
not yet been defined in upstream Linux, place them in the U-Boot specific
DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-05 10:04:57 +02:00
Sergiu Moga
205ecbdccd ARM: dts: sam9x60ek: Add pinctrl and gpio properties for USB
Add the required pinctrl and gpio properties required by the USB DT
nodes of the sam9x60ek boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
445ff8bb5a ARM: dts: sam9x60_curiosity: Add pinctrl and gpio properties for USB
Add the required pinctrl and gpio properties needed by the USB DT nodes
of the sam9x60_curiosity boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
3631be3ed6 ARM: dts: sam9x60: Add OHCI and EHCI DT nodes
Add the OHCI and EHCI DT nodes for the sam9x60 SoC's.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-05 10:04:57 +02:00
Heinrich Schuchardt
d7ddeb66a6 efi_loader: fix building aarch64 EFI binaries
While our EFI binaries execute without problems on EDK II they crash on
a Lenovo X13s. Let our binaries look more like what EDK II produces:

* move all writable data to a .data section
* align sections to 4 KiB boundaries (matching EFI page size)
* remove IMAGE_SCN_LNK_NRELOC_OVFL from .reloc section flags

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-04 13:17:42 +01:00
Mihai Sain
ee43b1e744 ARM: dts: at91: sam9x60: add sdhci1 node and pinctrl
Add node for sdhci1 controller and its pinctrl.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2023-01-03 10:58:15 +02:00
Stefan Bosch
28663622cf arm: s5p4418: dm_serial: remove old code / add DEBUG_UART
Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART
to s5p4418_nanopi2_defconfig.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
5745de2c9d arm: s5p4418: dm_serial: switch to DM_SERIAL
Switch the S5P4418-SOC and therefore the s5p4418_nanopi2 board to
DM_SERIAL.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
c8ba27f760 arm: s5p4418: dm_serial: add uarts to dts
Add S5P4418 UARTs and appropriate pinctrl to dts. Add UART to
s5p4418-nanopi2.dts.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Dai Okamura
872413bb0a arm: uniphier: use DM_TIMER of arm a9 global timer
All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer
in a simple implementation. Now DM_TIMER of it is available
on 35751c7f3f ("timer: sti: convert sti-timer to arm a9 global timer"),
so let's switch to it.

The old driver reads the lower 32bits of counter field
and sets the prescaler as 50 with PERIPHCLK(=50MHz),
so the global timer works as a 32-bit 1MHz timer.

The DM_TIMER uses the whole 64bits with no prescaler,
so the global timer works as a 64-bit PERIPHCLK timer.

CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency,
if there is no 'clocks' property in devicetree.

Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 16:01:39 -05:00
Rob Herring
bd8851c5b4 dts: synquacer: Drop unused and undocumented GPIO 'base' property
The 'base' GPIO controller property is unused in u-boot and Linux. It is
also not documented in the binding. So drop it.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-01-02 14:10:23 -05:00
Rob Herring
36ee37632c dts: synquacer: Drop unused and undocumented SPI properties
'active_clk_edges' and 'chipselect_num' SPI controller properties are
unused in u-boot and Linux. They are also not documented in the binding.
So drop them.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-01-02 14:10:23 -05:00
Rob Herring
00723684e4 dts: synquacer: Fix idle-states 'entry-method' value
The correct value for 'entry-method' in the idle-states binding is 'psci',
not 'arm,psci'. It hasn't mattered because it isn't used by the OS.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
563f238b67 dts: synquacer: Fix "arm, armv7-timer-mem" node address sizes
The "arm,armv7-timer-mem" schema defines the address sizes for child
nodes to be 32-bit as there's no need for 64-bit offsets and sizes of
the child 'frame' nodes.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
cc891c41f2 dts: synquacer: Use generic node names
DT node names should follow generic names defined in the DT spec. These
are also now checked by dtschema tools.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
6136c85ed0 dts: synquacer: Drop CPU 'arm,armv8' compatibles
'arm,armv8' compatible is for software models only. so drop it from cpu
nodes.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:43 -05:00
Christian Gmeiner
e93efaf9cc arm: dts: ti: k3-am64-mcu: Add pinctrl
Add the definition of the pinctrl for the MCU domain.

Same as kernel commit 500e6dfbb465531150ac6e2ff0856dd357ddc8a4

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-01-02 14:05:43 -05:00
Sean Anderson
bcc85b96b5 cmd: source: Support specifying config name
As discussed previously [1,2], the source command is not safe to use with
verified boot unless there is a key with required = "images" (which has its
own problems). This is because if such a key is absent, signatures are
verified but not required. It is assumed that configuration nodes will
provide the signature. Because the source command does not use
configurations to determine the image to source, effectively no
verification takes place.

To address this, allow specifying configuration nodes. We use the same
syntax as the bootm command (helpfully provided for us by fit_parse_conf).
By default, we first try the default config and then the default image. To
force using a config, # must be present in the command (e.g. `source
$loadaddr#my-conf`). For convenience, the config may be omitted, just like
the address may be (e.g. `source \#`). This also works for images
(`source :` behaves exactly like `source` currently does).

[1] https://lore.kernel.org/u-boot/7d711133-d513-5bcb-52f2-a9dbaa9eeded@prevas.dk/
[2] https://lore.kernel.org/u-boot/042dcb34-f85f-351e-1b0e-513f89005fdd@gmail.com/

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-31 13:35:19 -05:00
Sean Anderson
30fb045f2d treewide: Use NULL for script image name
Two callers of image_source_script specify an image name. However, both
use the deprecated @ syntax, indicating that they have not been updated
in a while. If CONFIG_FIT_SIGNATURE is enabled, we will reject such
names outright. Back in commit 152576a598 ("stm32mp: stm32prog: handle
U-Boot script in flashlayout alternate"), we even renamed one of the
nodes. Instead of hard-coding a script image name, just use the default
image.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-31 13:35:19 -05:00
Heinrich Schuchardt
3ec07c99d8 efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE
For the 64bit EFI binaries that we create set the
IMAGE_FILE_LARGE_ADDRESS_AWARE characteristic in the PE-COFF header
to indicate that they can handle addresses above 2 GiB.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Tom Rini
e95bcfb56c bcmcygnus: Convert CONFIG_IPROC to Kconfig
Select this symbol as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
f5dd0c5e19 configs: Remove unused or redundant CONFIG symbols
A number of CONFIG symbols have crept in that are never referenced in
code, so drop them here. Further, we have two symbols being enabled
in headers while already enabled correctly in Kconfig, so these lines
can also be removed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
e660e972c4 global: Migrate CONFIG_TEGRA_BOARD_STRING to CFG
Perform a simple rename of CONFIG_TEGRA_BOARD_STRING to CFG_TEGRA_BOARD_STRING

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
3e204427c8 global: Migrate CONFIG_SMP_PEN_ADDR to CFG
Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
3cdd6302a5 global: Migrate CONFIG_SC_TIMER_CLK to CFG
Perform a simple rename of CONFIG_SC_TIMER_CLK to CFG_SC_TIMER_CLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
9dbe356ef4 global: Migrate CONFIG_SAR_REG to CFG
Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
f9932d38a3 global: Migrate CONFIG_SAR2_REG to CFG
Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
f410d0ac8a global: Migrate CONFIG_PL011_CLOCK to CFG
Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
830fd095a3 global: Migrate CONFIG_PHY_IRAM_BASE to CFG
Perform a simple rename of CONFIG_PHY_IRAM_BASE to CFG_PHY_IRAM_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
8a897c4f97 global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG
Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
1d457dbb91 global: Migrate CONFIG_MAX_MEM_MAPPED to CFG
Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
8000ac874c global: Migrate CONFIG_LOWPOWER_FLAG to CFG
Perform a simple rename of CONFIG_LOWPOWER_FLAG to CFG_LOWPOWER_FLAG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
77db07ce1c global: Migrate CONFIG_LOWPOWER_ADDR to CFG
Perform a simple rename of CONFIG_LOWPOWER_ADDR to CFG_LOWPOWER_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
d4e4bc898b global: Migrate CONFIG_KSNET_NETCP_BASE to CFG
Perform a simple rename of CONFIG_KSNET_NETCP_BASE to CFG_KSNET_NETCP_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
f060d1885c global: Migrate CONFIG_KSNET_MAC_ID_BASE to CFG
Perform a simple rename of CONFIG_KSNET_MAC_ID_BASE to CFG_KSNET_MAC_ID_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
21bd204239 global: Migrate CONFIG_KSNET_CPSW_NUM_PORTS to CFG
Perform a simple rename of CONFIG_KSNET_CPSW_NUM_PORTS to CFG_KSNET_CPSW_NUM_PORTS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:49 -05:00
Tom Rini
7201b76978 global: Migrate CONFIG_IRAM_TOP to CFG
Perform a simple rename of CONFIG_IRAM_TOP to CFG_IRAM_TOP

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
7b5f75cffa global: Migrate CONFIG_IRAM_BASE to CFG
Perform a simple rename of CONFIG_IRAM_BASE to CFG_IRAM_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
35661f86eb global: Migrate CONFIG_I2C_MVTWSI_BASE1 to CFG
Perform a simple rename of CONFIG_I2C_MVTWSI_BASE1 to CFG_I2C_MVTWSI_BASE1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
45ede979e8 global: Migrate CONFIG_I2C_MVTWSI_BASE0 to CFG
Perform a simple rename of CONFIG_I2C_MVTWSI_BASE0 to CFG_I2C_MVTWSI_BASE0

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
04501ecca2 global: Migrate CONFIG_ARM_GIC_BASE_ADDRESS to CFG
Perform a simple rename of CONFIG_ARM_GIC_BASE_ADDRESS to CFG_ARM_GIC_BASE_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
957848882c rk32xx: Use standard TPL linker script
As of 2f41ade79e ("linker: Modify linker scripts to be more generic")
we can use the same linker script for SPL and TPL and not have to make
use of #undef tricks. Remove these last remnants.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23 10:07:03 -05:00
Tom Rini
b9d1f88b3a exynos: Rework legacy PWM usage
The way that the timer support is currently done for exynos/nexell
platforms relies on the legacy PWM infrastructure, and that needs to be
updated. However, we really cannot safely undef CONFIG_DM_PWM to build
the timer.c file without warnings. For now, rename the relevant legacy
functions to be prefixed with s5p_ and add prototypes to the arch pwm.h
files.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23 10:07:03 -05:00
Tom Rini
4fd9373bbb net: Remove more legacy functions
Remove some of the board and arch specific non-DM_ETH helper code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:49 -05:00
Tom Rini
d14f3f2725 Convert CONFIG_TEGRA_ENABLE_UARTA et al to Kconfig
This converts the following to Kconfig:
   CONFIG_TEGRA_ENABLE_UARTA
   CONFIG_TEGRA_ENABLE_UARTB
   CONFIG_TEGRA_ENABLE_UARTC
   CONFIG_TEGRA_ENABLE_UARTD
   CONFIG_TEGRA_SPI
   CONFIG_TEGRA_UARTA_GPU
   CONFIG_TEGRA_UARTA_SDIO1
   CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
   CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
32b7e39db4 Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig
This converts the following to Kconfig:
   CONFIG_STANDALONE_LOAD_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
f55281665a arm: ti814x: Remove remaining support code
When the ti814x_evm config was removed most, but not all, of the
relevant support code was remove.  Get rid of what was missed.

Fixes: 50b5326868 ("ti814x: Remove platform")
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
2b210540b1 Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig
This converts the following to Kconfig:
   CONFIG_PEN_ADDR_BIG_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
308520b8f2 global: Remove unused CONFIG symbols
This removes the following unreferenced CONFIG symbols:
   CONFIG_FDTADDR
   CONFIG_FDTFILE
   CONFIG_FLASH_SECTOR_SIZE
   CONFIG_FSL_CPLD
   CONFIG_HDMI_ENCODER_I2C_ADDR
   CONFIG_I2C_MVTWSI
   CONFIG_I2C_RTC_ADDR
   CONFIG_IRAM_END
   CONFIG_IRAM_SIZE
   CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
   CONFIG_L1_INIT_RAM
   CONFIG_MACB_SEARCH_PHY
   CONFIG_MIU_2BIT_21_7_INTERLEAVED
   CONFIG_MTD_NAND_VERIFY_WRITE
   CONFIG_MVGBE_PORTS
   CONFIG_NETDEV
   CONFIG_NUM_DSP_CPUS
   CONFIG_PHY_BASE_ADR
   CONFIG_PHY_INTERFACE_MODE
   CONFIG_PSRAM_SCFG
   CONFIG_RAMBOOT_SPIFLASH
   CONFIG_RAMBOOT_TEXT_BASE
   CONFIG_RD_LVL
   CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
   CONFIG_SETUP_INITRD_TAG
   CONFIG_SH_QSPI_BASE
   CONFIG_SMDK5420
   CONFIG_SOCRATES
   CONFIG_SPI_ADDR
   CONFIG_SPI_FLASH_QUAD
   CONFIG_SPI_FLASH_SIZE
   CONFIG_SPI_HALF_DUPLEX
   CONFIG_SPI_N25Q256A_RESET
   CONFIG_TEGRA_SLINK_CTRLS
   CONFIG_TPM_TIS_BASE_ADDRESS
   CONFIG_UBOOT_SECTOR_COUNT
   CONFIG_UBOOT_SECTOR_START
   CONFIG_VAR_SIZE_SPL
   CONFIG_VERY_BIG_RAM

And also:
   BL1_SIZE
   PHY_NO
   RESERVE_BLOCK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
3a581af21a Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig
This converts the following to Kconfig:

   CONFIG_FLASH_SPANSION_S29WS_N
   CONFIG_FLASH_VERIFY
   CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
   CONFIG_FSL_ISBC_KEY_EXT
   CONFIG_FSL_TRUST_ARCH_v1
   CONFIG_FSL_SDHC_V2_3
   CONFIG_MAX_DSP_CPUS
   CONFIG_MIU_2BIT_INTERLEAVED
   CONFIG_SERIAL_BOOT
   CONFIG_SPI_BOOTING
   CONFIG_X86EMU_RAW_IO

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
9b0240f8c6 Convert CONFIG_DM9000_BYTE_SWAPPED et al to Kconfig
This converts the following to Kconfig:
   CONFIG_DM9000_BYTE_SWAPPED
   CONFIG_DM9000_NO_SROM
   CONFIG_DM9000_USE_16BIT
   CONFIG_DM9000_DEBUG
   CONFIG_MXC_GPT_HCLK
   CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
4475d017c5 arm: exynos5: Migrate USB_BOOTING to Kconfig
This symbol is enabled for all exynos5 platforms, move to Kconfig and
select it.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-21 19:04:33 -05:00
Tom Rini
14f43797d0 Prepare v2023.01-rc4
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Merge tag 'v2023.01-rc4' into next

Prepare v2023.01-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-21 13:09:01 -05:00
Eugen Hristev
8374617637 ARM: dts: at91: sama5d2: fix wrong interrupt-cells property
The PMC node is not an interrupt provider, so it must not have
interrupt-cells.

This fixes the warning (on newer DTC):
arch/arm/dts/sama5d2.dtsi:82.22-602.6: Warning (interrupt_provider): /ahb/apb/pmc@f0014000: '#interrupt-cells' found, but node is not an interrupt provider

Fixes: 2c4b2dd289 ("ARM: at91/dt: Add device tree for SAMA5D2 Xplained")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-12-20 11:59:07 +02:00
Mihai Sain
a60c5a986e ARM: mach-at91: add support for sama7g5 chip id and extended id definition
Add SAMA7G5 series chip id definitions to align with linux SoC driver.
Add support for SAMA7G5 System-In-Package (SIP):
SAMA7G54D1G, SAMA7G54D2G, SAMA7G54D4G.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-12-20 11:59:07 +02:00
Eugen Hristev
4df35b38d1 ARM: dts: at91: sama7g5/sama7g5ek: align DT with kernel 6.1
Align the DT with current Linux 6.1 tree, wherever possible.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-12-20 11:59:07 +02:00
Tom Rini
daa531cc5c Merge tag 'u-boot-rockchip-20221219' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Only call binman when TPL available;
- rk3128 DTS fix;
- Fix GPT table corruption for rk3399 puma ;
- Fix i2c for rk3399 Pinebookpro;
- Enable UEFI capsule update for RockPi4;
2022-12-19 08:33:24 -05:00
Sughosh Ganu
e86c789ca3 rockpi4: board: Add firmware image information for capsule updates
Add information that will be needed for enabling the UEFI capsule
update feature on the RockPi4 boards. With the feature enabled, it
would be possible to update the idbloader and u-boot.itb images on the
RockPi4B and RockPi4C variants.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Sughosh Ganu
bea9267d7e rockchip: capsule: Add functions for supporting capsule updates
Add functions needed to support the UEFI capsule update feature on
rockchip boards. Currently, the feature is being enabled on the
RockPi4 boards with firmware images residing on GPT partitioned
storage media.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Michal Suchanek
216928c772 rockchip: Pinebook Pro: Do not initialize i2c before relocation
The i2c locks up when initialized before relocation, and it stays broken
in Linux as well breaking the ability to boot Linux.

The i2c bus and pmic was not actually used in pre-reloc before
commit ad607512f5 ("power: pmic: rk8xx: Support sysreset shutdown method")

The cause is not known.

This is board-specific, other boards that do not add the option to
include the i2c bus in pre-reloc DT are not affected.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Quentin Schulz
c74f6e748b rockchip: puma: fix GPT table corruption when saving U-Boot environment
The GPT table is taking the first 34 sectors, which amounts to 0x4400
bytes. Saving the environment below this address in storage will corrupt
the GPT table.

While technically the table ends at 0x4400, some tools (e.g. bmaptool)
are rounding everything to the logical block size (0x1000), so it is
safer to make it point to 0x5000 so that the environment could still
persist when flashing a sparse image with bmaptool or similar tools.

Obviously, the default 0x4000 environment size does not work anymore, so
let's set it to 0x3000 so it does fill the gap between the GPT table
(rounded to 0x1000) and the start of the idbloader.img.

Fixes: 56f580d3eb ("rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
58eb6675da arm: dts: rockchip: rk3128: fix clocks, compatible and phys
Fix rk3128 clocks, compatible and phys, so that they match the bindings.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
565d77b4c0 arm: dts: rockchip: rk3128: fix DT node names
The rk3128 DT node names should be generic.
Rename them to the pattern defined in the DT bindings.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
b919d43af5 arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files
Move all rk3128 u-boot specific properties in separate dtsi files.
Sort emmc node.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
c643468849 arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts
Bulk convert rk3128 DT gpios to their constant counterparts.

sed -i -f script.sed rk3128.dtsi
sed -i -f script.sed rk3128-evb.dts

================================

/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
4d89330b8a rockchip: rk3128-cru: sync the clock dt-binding header from Linux
In order to update the DT for rk3128
sync the clock dt-binding header.
This is the state as of v6.0 in Linux.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Kever Yang
f5315dd629 rockchip: Only call binman when TPL available
Rockchip platform use TPL to do the DRAM initialize for all the SoCs,
if TPL is not available, means no available DRAM init program, and the
u-boot-rockchip.bin is not functionable.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I2299f1eddce5aa7d5fb1a3fb4d8aeaa995b397fa
2022-12-19 10:55:58 +08:00
Andre Przywara
64531496f9 sunxi: board: annotate #endif lines
The legacy Allwinner code is cluttered with #ifdef's, some of them even
nested, which makes the code hard to read and error prone.
Eventually we will get rid of most of them, but for now let's at least
annotate the #endif lines with the corresponding symbol the bracket
started with.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-14 22:31:33 +00:00
Jim Liu
8debdf1417 ARM: dts: npcm7xx: add npcm750 gpio node compatible name
Add npcm750 gpio node compatible name

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-12-12 14:03:12 -05:00
Jim Liu
74bf4899b5 ARM: dts: npcm8xx: add npcm845 function node
1. add usb phy
2. add ehci ohci sdhci
3. add pinctrl node
4. add fiu node

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-12-12 14:03:12 -05:00
Andreas Kemnade
3419416a3a omap4: make musb probeable by simple bus
Like other peripherals important for booting,
do not rely on ti-sysc compatibility alone

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
2022-12-12 14:03:12 -05:00
Andrew Davis
1eaffe3958 arm: mach-omap2: Move common image process functions out of board files
The functions board_fit_image_post_process() and board_tee_image_process()
are not actually board specific (despite their names). Any board using the
OMAP2 family can use these functions. Move them to boot-common.c.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-12-12 14:03:11 -05:00
Dhruva Gole
8994ac365a arm: dts: Add OSPI support for AM62-SK
Add OSPI Support such that this device can boot up using OSPI Flash.
Also can use the flash for other purposes if required from uboot.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
2022-12-09 14:12:53 -05:00
Dhruva Gole
8bd8a5d022 arm: dts: k3-am62x: sync dt with linux kernel
Sync the DT Files with linux kernel (tag v6.0.3)

Signed-off-by: Dhruva Gole <d-gole@ti.com>
2022-12-09 14:12:53 -05:00
Bryan Brattlof
b6cbcd6155 arm: mach-k3: am62a: introduce auto-generated SoC data
Introduce the auto-generated clock tree and power domain data needed to
attach the am62a into the power-domain and clock frameworks of uboot

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
b511b371ad arm: mach-k3: introduce basic files to support the am62a
Introduce the mach-k3 files needed to properly boot TI's am62a SoC
family of devices

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
6bdfa69155 arm: dts: introduce am62a7 u-boot dtbs
Introduce the base dts files needed for u-boot or to augment the
linux dtbs for use in the u-boot-spl and u-boot binaries

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
253802912a arm: dts: introduce am62a7 dtbs from linux kernel
Introduce the basic am62a7 SoC dtbs from the v6.1-rc3 tag of the linux
kernel along with the new am62a specific pinmux definition that we will
use to generate the dtbs for the u-boot-spl and u-boot binaries

Co-developed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Tom Rini
8f17040877 - Drop MMCI interrupt-names in STM32H743, STM32MP15 and STM322MP13 DT
DHSOM:
   - Enable assorted ST specific commands
   - Add version variable
   - Add boot counter
 STM32MP13:
   - Add sdmmc cd-gpios for STM32MP135F-DK
   - Add clock & reset support
 STM32 ADC:
   - Split channel init into several routines
   - Add support of generic channels binding
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Merge tag 'u-boot-stm32-20221207' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Drop MMCI interrupt-names in STM32H743, STM32MP15 and STM322MP13 DT

DHSOM:
  - Enable assorted ST specific commands
  - Add version variable
  - Add boot counter
STM32MP13:
  - Add sdmmc cd-gpios for STM32MP135F-DK
  - Add clock & reset support
STM32 ADC:
  - Split channel init into several routines
  - Add support of generic channels binding
2022-12-08 11:25:08 -05:00
Balamanikandan Gunasundar
70cbf2f097 ARM: dts: at91: sam9x60ek: Enable NAND support
Enable the EBI and NAND flash controller. Define the pinctrl and
partition table

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
2d35bf2420 ARM: dts: at91: sam9x60: Add nodes for EBI and NAND
Add new bindings for EBI and NAND controller

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Tom Rini
9060919822 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Kautuk's semihosting patch:
  move semihosting library from arm directory to common place and add
  RISC-V support
- Zong's Kconfig patch:
  use "imply" instead of "select" to allow user to decide if
  SPL_SEPARATE_BSS should be selected
2022-12-08 08:28:14 -05:00
Tom Rini
341ba8d94b Second set of u-boot-at91 fixes for the 2023.01 cycle
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Merge tag 'u-boot-at91-fixes-2023.01-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 fixes for the 2023.01 cycle:

This is a single tiny fix that allows the correct name for one pin on
sama7g5 device. People with DT coming from Linux will have build errors
without this if they add NAND device.
2022-12-08 08:27:50 -05:00
Kautuk Consul
1c03ab9f4b lib: Add common semihosting library
We factor out the arch-independent parts of the ARM semihosting
implementation as a common library so that it can be shared
with RISC-V.

Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-08 15:15:22 +08:00
Tom Rini
2f420f135f net: tsec: Remove non-DM_ETH support code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.  Doing this removes some board support code
which was also unused. Finally, this removes some CONFIG symbols that
otherwise needed to be migrated to Kconfig, but were unused in code now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
8457d023b8 global: Remove extraneous DM_ETH imply/select
We only need to enable DM_ETH if we have a networking driver. All
networking drivers depend on DM_ETH being enabled, and their selection
ensures DM_ETH will be enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Marek Vasut
666b1a712d ARM: dts: stm32: Drop MMCI interrupt-names
The pl18x MMCI driver does not use the interrupt-names property,
the binding document has been updated to recommend this property
be unused, remove it.
Backport of Marek's Linux patch:
https://lore.kernel.org/linux-arm-kernel/20221013221242.218808-3-marex@denx.de/

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 17:04:08 +01:00
Yann Gautier
3068bb60c6 ARM: dts: stm32: add sdmmc cd-gpios for STM32MP135F-DK
On STM32MP135F-DK, the SD card detect GPIO is GPIOH4.
Backport of the Linux patch:
https://lore.kernel.org/linux-arm-kernel/20220921160334.3227138-1-yann.gautier@foss.st.com/

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-07 17:03:35 +01:00
Gabriel Fernandez
2c8d548f4e arm: dts: stm32mp13: add support of RCC driver
Adds support of Clock and Reset drivers for STM32MP13 platform.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 16:49:35 +01:00
Tom Rini
fc2240046c arm: Use the WEAK assembly entry point consistently
It is a bad idea, and more modern toolchains will fail, if you declare
an assembly function to be global and then weak, instead of declaring it
weak to start with. Update assorted assembly files to use the WEAK macro
directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-12-06 15:30:30 -05:00
Tom Rini
b43295a277 Convert CONFIG_TEGRA_CLOCK_SCALING et al to Kconfig
This converts the following to Kconfig:
   CONFIG_TEGRA_CLOCK_SCALING
   CONFIG_TEGRA_LP0
   CONFIG_TEGRA_PMU

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
1c34f7885d Convert CONFIG_SH_GPIO_PFC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SH_GPIO_PFC
   CONFIG_TMU_TIMER

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
9200011e95 Convert CONFIG_NAND_KMETER1 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_ECC_BCH
   CONFIG_NAND_KIRKWOOD
   CONFIG_NAND_KMETER1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
2568bd6db7 arm: Remove unused mx27 code
We no longer have any i.MX27 platforms, remove the remaining support
code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
4982e123b2 arm: samsung: Move CONFIG_MISC_COMMON to Kconfig
This option controls using board/samsung/common/misc.c, so add a Kconfig
file there as well and select it from the boards which use this
functionality.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-12-05 16:07:13 -05:00
Tom Rini
00faea644a arm: ls102xa: Migrate LS102XA_STREAM_ID
This symbol appears to be globally used in the architecture, select it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
d5596cbc6e arm: lpc32xx: Remove unused hsuart driver
This driver is not enabled in any config currently, remove it.

Cc: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
c136a86105 Convert CONFIG_IOMUX_SHARE_CONF_REG et al to Kconfig
This converts the following to Kconfig:
   CONFIG_IOMUX_LPSR
   CONFIG_IOMUX_SHARE_CONF_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
d5c77533b4 Convert CONFIG_IODELAY_RECALIBRATION to Kconfig
This converts the following to Kconfig:
   CONFIG_IODELAY_RECALIBRATION

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
98cb4c6b8e arm920t: Remove unused imx code
This code is currently unused, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
345c09de5e Convert CONFIG_FSL_DEVICE_DISABLE to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_DEVICE_DISABLE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Tom Rini
3b8dfc42a2 Convert CONFIG_SYS_TIMER_COUNTS_DOWN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_TIMER_COUNTS_DOWN

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
aa6e94deab global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
2db82bf2bd Convert CONFIG_SYS_PMAN et al to Kconfig
This converts the following to Kconfig:
   CONFIG_NOBQFMAN
   CONFIG_SYS_DPAA_DCE
   CONFIG_SYS_DPAA_FMAN
   CONFIG_SYS_DPAA_PME
   CONFIG_SYS_DPAA_RMAN
   CONFIG_SYS_PMAN

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
ecc8d425fd global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
789bb9537a Convert CONFIG_SYS_OMAP_ABE_SYSCK to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_OMAP_ABE_SYSCK

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
3408d96e6c Remove unused symbols
This commit removes the following unused symbols:
   CONFIG_SYS_NVRAM_BASE_ADDR
   CONFIG_SYS_NVRAM_SIZE
   CONFIG_SYS_PAXE_BASE
   CONFIG_SYS_PCCNT
   CONFIG_SYS_PCDAT
   CONFIG_SYS_PCDDR
   CONFIG_SYS_PCI1_ADDR
   CONFIG_SYS_PCI2_ADDR
   CONFIG_SYS_PCI1_IO_BUS
   CONFIG_SYS_PCI1_IO_SIZE
   CONFIG_SYS_PCI1_MEM_BUS
   CONFIG_SYS_PCI1_MEM_SIZE
   CONFIG_SYS_PCIE3_ADDR
   CONFIG_SYS_PCIE4_ADDR
   CONFIG_SYS_PCIE3_IO_PHYS
   CONFIG_SYS_PCIE3_IO_VIRT
   CONFIG_SYS_PCIE4_IO_PHYS
   CONFIG_SYS_PCIE4_IO_VIRT
   CONFIG_SYS_PLL_SETTLING_TIME
   CONFIG_SYS_QMAN_CENA_BASE
   CONFIG_SYS_QMAN_SP_CENA_SIZE
   CONFIG_SYS_RCAR_I2C0_BASE
   CONFIG_SYS_RCAR_I2C1_BASE
   CONFIG_SYS_RCAR_I2C2_BASE
   CONFIG_SYS_RCAR_I2C3_BASE
   CONFIG_SYS_SATA
   CONFIG_SYS_SDRAM_BASE2
   CONFIG_SYS_SGMII_REFCLK_MHZ
   CONFIG_SYS_SGMII_LINERATE_MHZ
   CONFIG_SYS_SGMII_RATESCALE
   CONFIG_SYS_SH_SDHI0_BASE
   CONFIG_SYS_SH_SDHI0_BASE
   CONFIG_SYS_SH_SDHI1_BASE
   CONFIG_SYS_SH_SDHI2_BASE
   CONFIG_SYS_SH_SDHI3_BASE
   CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
   CONFIG_SYS_SPI_U_BOOT_SIZE
   CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
   CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
   CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
   CONFIG_SYS_VCXK_BASE
   CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
   CONFIG_SYS_VCXK_DOUBLEBUFFERED
   CONFIG_SYS_VCXK_ENABLE_DDR
   CONFIG_SYS_VCXK_ENABLE_PIN
   CONFIG_SYS_VCXK_ENABLE_PORT
   CONFIG_SYS_VCXK_INVERT_DDR
   CONFIG_SYS_VCXK_INVERT_PIN
   CONFIG_SYS_VCXK_INVERT_PORT
   CONFIG_SYS_VCXK_REQUEST_DDR
   CONFIG_SYS_VCXK_REQUEST_PIN
   CONFIG_SYS_VCXK_REQUEST_PORT
   CONFIG_SYS_VSC7385_BR_PRELIM
   CONFIG_SYS_VSC7385_OR_PRELIM

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
cdc5ed8f1f global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
91092132ba global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
9591b63531 Convert CONFIG_SYS_NS16550_MEM32 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_NS16550_MIN_FUNCTIONS
   CONFIG_SYS_NS16550_MEM32
   CONFIG_SYS_NS16550_PORT_MAPPED
   CONFIG_SYS_NS16550_REG_SIZE
   CONFIG_SYS_NS16550_SERIAL

To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that
platforms can enable the legacy driver here for SPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:07 -05:00
Tom Rini
4e5909450e global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Michal Simek
6a664a7bd4 ARM: zynq: Add missing twd timer for mini configurations
The commit b7e0750d88 ("zynq: Convert arm twd timer to DM driver")
switched timer to DM but missing to add nodes to all mini configurations.
Based on it missing timer end up in non functional system where any delay
doesn't work.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2020fc7e3d4760e890265485b3c7e18eb1caf8be.1669724598.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Michal Simek
92e6900536 arm64: zynqmp: Do not enable IPI by default
ZynqMP mini configurations are not using IPI driver and enabling this is
adding additional ~1200 Bytes (depends on configuration).
This ends up in situation that there is no enough space in OCM for
relocation that's why disable this driver for all mini configurations.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c71bab3927cb71ae517d9c21f59f3d5cf0caf712.1669734580.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Michal Simek
74673ca705 arm64: zynqmp: Do not include psu_init to U-Boot by default
The commit ed35de6170 ("Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to
Kconfig") converted CONFIG_ZYNQMP_PSU_INIT_ENABLED symbol and enabled it by
default which is not correct configuration.
Intention of this config was to have it enabled by default for SPL and
provide an option to users to also do low level initialization directly
from U-Boot.
That's why it is necessary to define second symbol with SPL marking in it
and properly use symbols depends on usage in Makefile.
Also disable ZYNQMP_PSU_INIT_ENABLED from boards which enables it by
default. CONFIG_SPL_ZYNQMP_PSU_INIT_ENABLED is enabled by default when SPL
is enabled.

Reported-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d5fcbd66b05bf0d7ef594e66464ee23b48c5e4cc.1669969083.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Lukas Funke
d9efdc7d42 arm64: zynqmp: dynamically mark r5 cores as used
When Linux boot takes over control of the pmu
(by signaling PM_INIT_FINALIZE via ipi), pmu will switch off 'unused'
rpu cores. The Xilinx zynqmp fsbl prevents switching off those cores by
marking rpu cores as 'used' when loading code partitions to those cores.
The current u-boot SPL is missing this behaviour, which results in
halting rpu cores during Linux boot.

This commit mimics the xilinx zynqmp fsbl behavior by marking r5 cores as
used when they are released during boot.

Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Lukas Funke <lukas.funke-oss@weidmueller.com>
Link: https://lore.kernel.org/r/20221028121547.26464-2-lukas.funke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
Paul Barker
b9829e9846 am335x-sancloud-bbe: Add -u-boot.dtsi files
The SanCloud BBE requires the same dtb nodes to be present in the SPL as
the AM335x EVM.

The SanCloud BBE Lite also requires the SPI flash node and all
dependencies to be present in the SPL to support SPI boot.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
8328022d05 am335x-sancloud-bbe-lite: SPI flash is JEDEC compatible
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
78b9afd2c3 am335x-evm: Enable required dtb nodes in SPL
For successful boot when CONFIG_SPL_OF_CONTROL=y, we need to ensure that
the board EEPROM on i2c0, the uart0 serial port and the relevant boot
device (mmc1 or mmc2) can be accessed in the SPL. We also need to
preserve the parent nodes for each required dtb node.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Mihai Sain
94256dc610 ARM: dts: at91: sama7g5: fix signal name of pin PD8
The signal name of pin PD8 with function D is A22_NANDCLE
as it is defined in the datasheet.

Fixes: 558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-12-02 09:48:49 +02:00
Bryan Brattlof
4c710fa828 arm: mach-k3: fix spelling mistake "entended" -> "extended"
the macro for the boot data location from rom is misspelled. fix it

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-11-24 16:26:03 -05:00
Dylan Hung
8c7b55724c ram: ast2600: Align the RL and WL setting
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24 16:26:01 -05:00
Tom Rini
d5d9f32579 - Implement setbrg op to meson serial device
- Re-add the old PHY reset binding for nanopi-k2
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Merge tag 'u-boot-amlogic-20221122' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- Implement setbrg op to meson serial device
- Re-add the old PHY reset binding for nanopi-k2
2022-11-23 10:05:26 -05:00
Christian Hewitt
e0638f1d09 arm64: dts: meson: nanopi-k2: readd PHY reset properties
The sync of device-tree/bindings in 11a48a5a18c6 ("Linux 5.6-rc2") causes
Ethernet to break on some GXBB boards; the PHY seems to need proper reset
timing to function in u-boot and Linux. Re-add the old PHY reset binding
for dwmac until we support new bindings in the PHY node. This borrows the
same fix applied to the Odroid C2 board [0].

[0] https://lists.denx.de/pipermail/u-boot/2021-April/446658.html

Fixes: dd5f2351e9 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://lore.kernel.org/r/20221025143205.14470-1-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-11-22 18:53:21 +01:00
Ashok Reddy Soma
3655dd22a4 arm64: versal: Add octal spi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a
smaller footprint from on chip memory(OCM). This configuration has
required CONFIG's enabled to support octal spi flash and uses DCC terminal
for console output. Add required dts for octal spi flash mini u-boot
configuration.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221116141155.14788-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Ashok Reddy Soma
3c53ebdd5c arm64: versal: Add qspi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a
smaller footprint from on chip memory(OCM). This configuration has
required CONFIG's enabled to support qspi flash and uses DCC terminal
for console output. Add required dts files for qspi mini configuration.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221116141155.14788-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Michal Simek
64fc7fc887 soc: xilinx: versal-net: Add soc_xilinx_versal_net driver
Add soc_xilinx_versal_net driver to identify the family & revision of
versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to
enable/disable this driver. To enable this driver by default, add this
config to xilinx_versal_net_virt_defconfig file. This driver will be
probed using platdata U_BOOT_DEVICE structure which is specified in
mach-versal-net/cpu.c.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
38920451c7 arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106
zcu106 also connects ethernet phy reset via tca6416 chip as is done on
other evaluation boards. That's why describe this connection to make sure
that ethernet phy is reset before it's use.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21ccd672b799b5858021f6059098a1247c311fae.1668596358.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
6b067f4bfa xilinx: versal-net: Fix incorrect platform name in Kconfig
Fix incorrect name used in entry description.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Christian Kohn
96dcde487e ARM: zynq: DT: Enable all FCLKs by default
The fclk-enable property is set to 0 which disables all FCLKs.
Enable all FCLKs so they can be used as clock sources in the
programmable logic.

Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b1308dc1f14f8eb24662019f7376c959e5e763b8.1665567031.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Venkatesh Yadav Abbarapu
ba74bcf3e0 xilinx: common: Remove zynq_board_read_rom_ethaddr()
Removing the zynq_board_read_rom_ethaddr() function as
xlnx,eeprom is not used anymore. As all board dts to use
nvmem alias instead of xlnx,eeprom.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Stefano Babic
8fc220d0a6 Revert "imx: imx8: apalis: switch to binman"
This reverts commit b8072ae848.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-21 09:23:00 -05:00
Pali Rohár
04bb5e95be arm32: Fix relocation of env_addr if POSITION_INDEPENDENT=y
Apply commit 534f0fbd65 ("arm64: Fix relocation of env_addr if
POSITION_INDEPENDENT=y") also for 32-bit ARM.

This change fixes crashing of U-Boot on ARMv7 (Omap3 / Cortex-A8) Nokia N900
phone (real HW). Note that qemu emulator of this board with same u-boot.bin
binary has not triggered this crash.

Crash happened after U-Boot printed following debug lines to serial console:

    initcall: 0001ea8c (relocated to 8fe0aa8c)
    Loading Environment from <NULL>... Using default environment
    Destroy Hash Table: 8fe25a98 table = 00000000
    Create Hash Table: N=387

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-11-21 09:23:00 -05:00
Tom Rini
c4ee4fe92e For 2022.01
-----------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083
 
 - Fix UART
 - moved to binman (MX8 boards)
 - Toradex: sync DTS with Linux
 - Gateworks: fixes
 - New boards : MSC SM2S iMX8MP
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Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2022.01
-----------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083

- Fix UART
- moved to binman (MX8 boards)
- Toradex: sync DTS with Linux
- Gateworks: fixes
- New boards : MSC SM2S iMX8MP
2022-11-14 09:33:36 -05:00
Fabio Estevam
c9713c1551 imx8-u-boot: Fix SPL guard option
We should guard the SPL nodes against CONFIG_SPL_BUILD to fix
the following build error when the blobs are absent:

binman: Fail open first container file mx8qm-ahab-container.img

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-12 14:13:49 +01:00
Tom Rini
cc1159bbfa global: Migrate CONFIG_HPS* symbols to the CFG namespace
Migrate all of CONFIG_HPS* to the CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
6cc04547cb global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
15713fc855 mediatek: Include <linux/sizes.h> where needed
These files reference SZ_ macros without including <linux/sizes.h>,
correct this.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Stefano Babic
cca660c2bd Convert mx8 u-boot.dtsi to CONFIG_TEXT_BASE
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-09 17:12:32 +01:00
Oliver Graute
b8072ae848 imx: imx8: apalis: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
bdadc140a1 imx: imx8x: colibri: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
bc1d145eaf imx: imx8qxp: deneb switch to binman
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
dcbc4ae9d6 imx: imx8qxp: giedi switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
4aa738823c imx: imx8qm: imx8qm_mek switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
61c57b614e imx: imx8qxp: imx8qxp_mek switch to binman
Switch to use binman pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
5a878c9472 imx: imx8qm: cgtqmx8: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
55be8433d5 imx: imx8qm-rom7720: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Fabio Estevam
f827f84d3f wandboard: Pass mmc aliases
Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi.

After the sync with Linux in commit d0399a46e7 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.

This causes a regression in which the SD card cannot be found anymore:

Since commit  the aliases node has been removed
U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300)

CPU:   Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM:  2 GiB
Core:  62 devices, 17 uclasses, devicetree: separate
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment

Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the SD card (esdhc3) was
mapped to mmc0.

Fixes: d0399a46e7 ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-09 17:12:31 +01:00
Marcel Ziswiler
dbd5ca2e46 imx8mm: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
f067b59743 imx8mn: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
0b42fdca2d imx8mp: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
cb9b70fd2f imx8mq: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
ed7bda5710 imx8ulp: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
62f96866d3 imxrt1050: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
59a4e7fd88 imxrt1020: migrate to build system included -u-boot.dtsi
Migrate to using automatic build system included -u-boot.dtsi device
tree include files.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
05e22e2804 vf610: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Baruch Siach
cf8ffbe36f mx6cuboxi: migrate to DM_SERIAL
Add the needed DT overrides to enable UART in SPL.

Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-08 17:35:00 +01:00
Martyn Welch
c8f3402ad2 arm: imx8mp: Initial MSC SM2S iMX8MP support
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-08 17:34:47 +01:00
Martyn Welch
c92c3a4453 ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP
The i.MX8MP SoC contains 2 more i2c buses. Add support for the
configuration of these buses.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07 22:45:05 +01:00
Martyn Welch
03a7a82970 imx8m: USDHC3 base address definition for i.MX8MP
The i.MX8MP also has USDHC3, allow access to the relvant base address
definition.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07 22:45:05 +01:00
Adam Ford
3a7943a90c imx: imx8mm-beacon: Enable USB booting via SDP
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL.  Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode.  Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07 22:45:05 +01:00
Matthias Schiffer
975f4117d5 ARM: mx7: psci: fix suspend/resume e10133 workaround
The e10133 workaround was broken in two places:

- The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0.
  While the old register values were saved, the actual masking was
  missing.
- imx_udelay() expects the system counter to run at its base frequency,
  but the system counter is switched to a lower frequency earlier in
  psci_system_suspend(), leading to a much longer delay than intended.
  Replace the call with an equivalent loop (linux-imx 5.15 does the same)

This fixes the SoC hanging forever when there was already a wakeup IRQ
pending while suspending.

Fixes: 57b620255e ("imx: mx7: add system suspend/resume support")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2022-11-07 22:45:04 +01:00
Loic Poulain
a887f2ac3e configs: imx8m: Enable CONFIG_ARMV8_CRYPTO support
This enables armv8 crypto extension usage for SHA1/SHA256.

Which speed up sha1/sha256 operations, about 10x faster with
a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07 22:45:04 +01:00
Chris Packham
6cc8b5db40 arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
  * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
  * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
  * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
  * SR1: 88E2540*4
  * SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
  port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
  connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
  Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
  solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-11-07 07:46:28 +01:00
Chris Packham
7d7bb99e22 arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-11-07 07:46:28 +01:00
Chris Packham
3988e6d6b1 arm: mvebu: Don't use CONFIG_TIMER on ARM64
The 64-bit mvebu SoCs don't have a suitable timer driver so add a !ARM64
condition to the select.

Fixes: 7b530bb19e ("arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:46:12 +01:00
Hamish Martin
497db3ad89 arm: armada: dts: Add clock to armada-ap80x uart1
The uart1 node was missing the 'clock-frequency' property. This meant
the driver for this device would fail at probe.
The clock for uart1 is fed from the same source as uart0 and is a fixed
200MHz clock. This is confirmed via documentation for the CN9130 SoC
and from the equivalent code in Linux at:
<linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
where uart0 and uart1 share a common 'clocks' definition.

Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:17:55 +01:00
Christian Gmeiner
dcbc95c23c arm: dts: ti: k3-am64-main: Add RTI watchdog nodes
Add the needed bus mappings for the two main RTI memory ranges and
the required device tree nodes in the main domain.

Same as kernel commit 6dd8457dc20693e2ba9054c171499b22664fd4e7

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-11-02 13:58:17 -04:00
Andre Przywara
44b7abf8dc highbank: switch to use the Arm SP804 DM_TIMER driver
So far the Calxeda machines were using the CONFIG_SYS_TIMER_* macros to
simply hardcode the address of the counter register of the SP804 timer.
This method is deprecated and scheduled for removal.

Use the newly introduced SP804 DM_TIMER driver to provide timer
functionality on Highbank and Midway machines. The base address and base
frequency are taken from the devicetree.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:58:17 -04:00
Andre Przywara
2e32930087 arm: smh: Allow semihosting trap calls to be inlined
Currently our semihosting trap function is somewhat fragile: we rely
on the current compiler behaviour to assign the second inline assembly
argument to the next free register (r1/x1), which happens to be the
"addr" argument to the smh_trap() function (per the calling convention).
I guess this is also the reason for the noinline attribute.

Make it explicit what we want: the "addr" argument needs to go into r1,
so we add another register variable. This allows to drop the "noinline"
attribute, so now the compiler beautifully inlines just the trap
instruction directly into the calling function.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:31:40 -04:00
Andre Przywara
d660a82934 arm: smh: Make semihosting trap calls more robust
Commit f4b540e25c5c("arm: smh: Fix uninitialized parameters with newer
GCCs") added a memory clobber to the semihosting inline assembly trap
calls, to avoid too eager GCC optimisation: when passing a pointer, newer
compilers couldn't be bothered to actually fill in the structure that it
pointed to, as this data would seemingly never be used (at least from the
compiler's point of view).
But instead of the memory clobber we need to tell the compiler that we are
passing an *array* instead of some generic pointer, this forces the
compiler to actually populate the data structure.
This involves some rather hideous cast, which is best hidden in a macro.

But regardless of that, we actually need the memory clobber, but for two
different reasons: explain them in comments.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:31:40 -04:00
Andre Przywara
30b315b48d arm: smh: specify Thumb trap instruction
The ARM semihosting interface uses different trap instructions for
different architectures and instruction sets. So far we were using
AArch64 and ARMv7-M, and had an untested v7-A entry. The latter does
not work when building for Thumb, as can be verified by using
qemu_arm_defconfig, then enabling SEMIHOSTING and SYS_THUMB_BUILD:
==========
{standard input}:35: Error: invalid swi expression
{standard input}:35: Error: value of 1193046 too large for field of 2 bytes at 0
==========

Fix this by providing the recommended instruction[1] for Thumb, and
using the ARM instruction only when not building for Thumb. This also
removes some comment, as QEMU for ARM allows to now test this case.
Also use the opportunity to clean up the inline assembly, and just define
the actual trap instruction inside #ifdef's, to improve readability.

[1] https://developer.arm.com/documentation/dui0471/g/Semihosting/The-semihosting-interface?lang=en

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:31:40 -04:00
Sughosh Ganu
95b5a7de30 FWU: STM32MP1: Add support to read boot index from backup register
The FWU Multi Bank Update feature allows the platform to boot the
firmware images from one of the partitions(banks). The first stage
bootloader(fsbl) passes the value of the boot index, i.e. the bank
from which the firmware images were booted from to U-Boot. On the
STM32MP157C-DK2 board, this value is passed through one of the SoC's
backup register. Add a function to read the boot index value from the
backup register.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
a402adc664 stm32mp1: Add a node for the FWU metadata device
The FWU metadata structure is accessed through the driver model
interface. On the stm32mp157c dk2 and ev1 boards, the FWU metadata is
stored on the uSD card. Add the fwu-mdata node on the u-boot specifc
dtsi file for accessing the metadata structure.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:32 -04:00
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-31 11:01:31 -04:00
William Zhang
21545a8cbf timer: bcmbca: use arm global timer for bcm63138 SoC
As STI timer is renamed to ARM A9 global timer, change BCM63138 to use
the new global timer config symbol name.

This patch applies on top of the my previous patch [1].

[1]: https://lists.denx.de/pipermail/u-boot/2022-August/491060.html

Signed-off-by: William Zhang <william.zhang@broadcom.com>
2022-10-31 08:56:00 -04:00
William Zhang
779a7b665f arm: bcmbca: remove bcm6753 support under CONFIG_ARCH_BCM6753
BCM6753 is essentially same as the main chip BCM6855 but with different
SKU number. Now that BCM6855 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM6855, remove the original ARCH_BCM6753 support and migrate its
configuration and dts settings. This includes:
- Remove the bcm96753ref board folder. It is replaced by the
generic bcmbca board folder.
- Merge the 6753.dtsi setting to the new 6855.dtsi file. Update
96753ref board dts with the new compatible string.
- Delete broadcom_bcm96763ref.h and merge its setting to the new
bcm96855.h file.
- Delete bcm96753ref_ram_defconfig and use a basic config version of
bcm96855_defconfig

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:59 -04:00
William Zhang
62c0ae40bb arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCA
BCM6855 is a Broadcom ARM A7 based PON Gateway SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family. Like other
broadband SoC, this patch adds it under CONFIG_BCM6855 chip config and
CONFIG_ARCH_BCMBCA platform config.

This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and ARM PL101 uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:59 -04:00
William Zhang
872308c6b1 arm: bcmbca: remove bcm6858 support under CONFIG_ARCH_BCM6858
Now that BCM6858 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM6858, remove the original ARCH_BCM6858 support and migrate its
configuration and dts settings. This includes:
- Remove the bcm968580xref board folder. It is replaced by the generic
bcmbca board folder.
- Update bcm968580xref board dts with the new compatible string.
- Delete broadcom_bcm968580xref.h and merge its setting to the new
bcm96858.h file.
- Remove bcm968580xref_ram_defconfig as a basic config version of
bcm96858_defconfig is now added.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:58 -04:00
William Zhang
b0e2b6abac arm: bcmbca: add bcm6858 SoC support under CONFIG_ARCH_BCMBCA
BCM6858 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family. Like other broadband
SoC, this patch adds it under CONFIG_BCM6858 chip config and
CONFIG_ARCH_BCMBCA platform config.

This initial support includes a bare-bone implementation and the
original dts is updated with the one from linux next git repository.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:51 -04:00
William Zhang
fdf8f29dc7 arm: bcmbca: remove bcm68360 support under CONFIG_ARCH_BCM68360
BCM68360 is a variant within the BCM6856 chip family. Now that BCM6856
is supported under CONFIG_ARCH_BCMBCA and CONFIG_BCM6856, remove the
original ARCH_BCM68360 support and migrate its configuration and dts
settings. This includes:
  - Remove the bcm968360bg board folder. It is replaced by the generic
    bcmbca board folder.
  - Merge the 68360.dtsi setting to the new 6856.dtsi file. Update board
    dts with the new compatible string.
  - Merge broadcom_bcm968360bg.h setting to the new bcm96856.h file.
  - Remove bcm968360bg_ram_defconfig as a basic config version of
    bcm96856_defconfig is now added.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:50 -04:00
William Zhang
dc244ca33a arm: bcmbca: add bcm6856 SoC support under CONFIG_ARCH_BCMBCA
BCM6856 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family. Like other Broadband
SoC, this patch adds it under CONFIG_BCM6856 chip config and
CONFIG_ARCH_BCMBCA platform config.

This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and Broadcom uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from
linux.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:41 -04:00
William Zhang
07f97bde54 arm: bcmbca: remove bcm63158 support under CONFIG_ARCH_BCM63158
Now that BCM63158 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM63158, remove the original ARCH_BCM63158 support and migrate
configuration settings.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:55:40 -04:00
William Zhang
61546e7cda arm: bcmbca: add bcm63158 SoC support under CONFIG_ARCH_BCMBCA
BCM63158 is a Broadcom B53 based DSL Gateway SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family. Like other
Broadband SoC, this patch adds it under CONFIG_BCM63158 chip
config and CONFIG_ARCH_BCMBCA platform config.

This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and ARM PL011 uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from
linux.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:54:44 -04:00
William Zhang
e5703df262 arm: bcmbca: add bcm4908 SoC support
BCM4908 is a Broadcom B53 based WLAN AP router SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family so it's added
under ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and Broadcom uart.

This SoC is supported in the linux git repository so the dts and dtsi
files are stripped down version of linux copies with mininum blocks
needed by u-boot.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
2022-10-31 08:54:44 -04:00
William Zhang
1b81843bac arm: bcmbca: add bcm6813 SoC support
BCM6813 is a Broadcom B53 based PON and WLAN AP router SoC. It is part
of the BCA (Broadband Carrier Access origin) chipset family so it's
added under ARCH_BCMBCA platform. This initial support includes a
bare-bone implementation and dts with CPU subsystem, memory and ARM
PL011 uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
2022-10-31 08:54:43 -04:00
William Zhang
dc6117dcb3 arm: bcmbca: add bcm4912 SoC support
BCM4912 is a Broadcom B53 based WLAN AP router SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and ARM PL011 uart.

This SoC is supported in the linux-next git repository so the dts
and dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
2022-10-31 08:54:43 -04:00
William Zhang
c6e0073c05 arm: bcmbca: add bcm63146 SoC support
BCM63146 is a Broadcom B53 based DSL Broadband SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and ARM PL011 uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
2022-10-31 08:54:43 -04:00
William Zhang
21385adf2c arm: bcmbca: add bcm63138 SoC support
BCM63138 is an ARM A9 based DSL Broadband SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory, ARM A9 global timer
and Broadcom uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are stripped down version of linux copies with mininum blocks
needed by u-boot.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

This patch applies on top of the my previous patch [1].

[1] https://lists.denx.de/pipermail/u-boot/2022-August/490570.html

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31 08:54:43 -04:00
William Zhang
7e3d69592b arm: bcmbca: add bcm63148 SoC support
BCM63148 is an Broadcom B15 based DSL Broadband SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and Broadcom uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
2022-10-31 08:54:43 -04:00
William Zhang
4054fd7182 arm: bcmbca: add bcm6756 SoC support
BCM6756 is an ARM A7 based WLAN Gateway and Access Point Broadband SoC.
It is part of the BCA(Broadband Carrier Access origin) chipset family so
it's added under ARCH_BCMBCA platform. This initial support includes a
bare-bone implementation and dts with CPU subsystem, memory and ARM
PL011 uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
2022-10-31 08:54:43 -04:00
William Zhang
4cab03842c arm: bcmbca: add bcm6878 SoC support
BCM6878 is an ARM A7 based PON Broadband SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and ARM PL011
uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux with minor fix-up that needs to be
upstreamed to linux as well.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
2022-10-31 08:54:43 -04:00
William Zhang
adb34dd542 arm: bcmbca: add bcm6846 SoC support
BCM6846 is an ARM A7 based PON Broadband SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and Broadcom uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux with minor fix-up that needs to be
upstreamed to linux as well.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
2022-10-31 08:54:43 -04:00
William Zhang
41c65ce44c arm: bcmbca: add bcm63178 SoC support
BCM63178 is an ARM A7 based DSL Broadband SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and ARM PL011 uart.

This SoC is supported in the linux-next git repository so the dts and
dtsi files are copied from linux with minor fix-up that needs to be
upstreamed to linux as well.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
2022-10-31 08:54:42 -04:00
Simon Glass
b86986c7b3 video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEO
Now that all the old code is gone, rename this option. Driver model
migration is now complete.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30 20:07:17 +01:00
Simon Glass
5ce85e069f nexell: Drop old LCD code
This relies on the old LCD implementation which is to be removed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30 20:07:17 +01:00
Simon Glass
365e52dd25 video: samsung: Drop old LCD code
This relies on the old LCD implementation which is to be removed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30 20:07:17 +01:00
Simon Glass
6b9a829d27 video: Drop atmel LCD code
This has not been migrated to DM_VIDEO since 2019. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30 20:07:17 +01:00
Simon Glass
82f7b869f5 video: Drop CONFIG_AM335X_LCD
This relies on the old LCD implementation which is to be removed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30 20:07:16 +01:00
Simon Glass
820b5894c1 video: Move and rename DM_HX8238D option
This is actually a panel, not a video device. Rename the option, move it
into the right place and make it depend on PANEL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30 20:01:40 +01:00
Tom Rini
3eebbd866b Merge tag 'fsl-qoriq-2022-10-18' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Layerscape update
 - support sysreset,
 - de-select FSL_IFC when booting from SD
 - disable unused parts of ICID tables
 - reduce ns_dev size for csu
 - enable dma snooping for ls104x
 - nand driver fixups for ls1043ardb rev 7.0 boards.
2022-10-24 21:28:47 -04:00
Tom Rini
7d8ab3cd63 u-boot-imx-20221024
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916
 
 - for 2022.01
 - rework Kontron boards (mx6 and mx8)
 - fixes for Toradex
 - fixes (SPI, CAAM, )
 - sync DT with Linux
 - fixes for Gateworks GW7903 and GW7904 PMIC
 - Engicam i.Core MX8M Plus EDIMM2.2
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCY1aVgA8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76YlhwCfXTQJzJXruk6UKg1zbsimD3bsChUAoJFzB3yp
 zft+THzNdQTnfUGN9u+U
 =JHxW
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20221024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916

- for 2022.01
- rework Kontron boards (mx6 and mx8)
- fixes for Toradex
- fixes (SPI, CAAM, )
- sync DT with Linux
- fixes for Gateworks GW7903 and GW7904 PMIC
- Engicam i.Core MX8M Plus EDIMM2.2
2022-10-24 10:04:30 -04:00
Marcel Ziswiler
063195d41a imx28: avoid num_cs and spi_max_frequency build errors
Avoid the following build errors after the device tree sync:

drivers/spi/mxs_spi.c: In function ‘mxs_spi_probe’:
drivers/spi/mxs_spi.c:327:25: error: ‘struct dtd_fsl_imx23_spi’ has no
 member named ‘spi_max_frequency’
  327 |  priv->max_freq = dtplat->spi_max_frequency;
      |                         ^~
drivers/spi/mxs_spi.c:328:23: error: ‘struct dtd_fsl_imx23_spi’ has no
 member named ‘num_cs’
  328 |  plat->num_cs = dtplat->num_cs;
      |                       ^~

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
1550ab9d88 imx23: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
7d08ddd09b imx28: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
a557ccd0b6 imx51: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
10f4f3f569 imx53: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
fa4ce85194 imx6qdl: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
175a8741a7 imx6qp: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
2419acf7e2 imx6sl: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
97e530dd56 imx6sll: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
4ad2ff5166 imx6sx: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
7b370703c5 imx6ulz: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
1c385db358 imx6ull: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
bf947d2a4b imx6ul: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Marcel Ziswiler
dfd0adc2f6 imx7ulp: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-10-24 13:43:21 +02:00
Adam Ford
af007620d2 arm: dts: imx8mn-venice: Consolidate with imx8mn-u-boot
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-10-24 13:43:21 +02:00
Adam Ford
42eb9ef7bb arm: dts: imx8mn-var-som-symphony: Consolidate with imx8mn-u-boot
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-10-24 13:43:20 +02:00
Adam Ford
5a97f33938 arm: dts: imx8mn-evk: Consolidate with imx8mn-u-boot
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-10-24 13:43:20 +02:00
Adam Ford
2341256954 arm: dts: imx8mn-ddr4-evk: Consolidate with imx8mn-u-boot
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-10-24 13:43:20 +02:00
Adam Ford
d096b8a0e5 arm: dts: imx8mn-bsh-smm-s2: Consolidate with imx8mn-u-boot
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-10-24 13:43:20 +02:00
Adam Ford
cc1028b7e0 arm: dts: imx8mn-beacon-kit: Consolidate with imx8mn-u-boot
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-10-24 13:43:20 +02:00
Adam Ford
93c4c0e4dd arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi
Multiple boards create duplicate entries in their respective
-u-boot.dtsi files which all basically do the same thing.
To consolidate these and make it easier to make improvements
going forward, consolidate them all into one place.

This file creates a flash.bin image using binman, and supports
LPDDR4, DDR4 and DDR3.  Since individual boards use different
peripherals and different UART ports, those entries were kept
in their respective board files, but the spba1 node was addded
which contains all UART1-3 to help facilitate SPL_DM_SERIAL.
Individual users will still need to include their respective
UART and pinctrl nodes for those UARTS.

This consolidated file also supports generating a flash.bin file
which can boot from flexSPI if CONFIG_FSPI_CONF_HEADER is
enabled.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-24 13:43:20 +02:00
Andrejs Cainikovs
9836eb0a2f arm: dts: verdin-imx8mp: enable caam in SPL
CAAM is initialized in SPL, so relevant device tree nodes needs to be
updated.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2022-10-24 11:34:33 +02:00
Tim Harvey
61e7f97325 board: gateworks: venice: add imx8mm-gw7904 support
The GW7904 is based on the i.MX 8M Mini SoC featuring:
 - LPDDR4 DRAM
 - eMMC FLASH
 - microSD connector with UHS support
 - LIS2DE12 3-axis accelerometer
 - Gateworks System Controller
 - IMX8M FEC
 - 2x RS232 off-board connectors
 - PMIC
 - 10x bi-color LED's
 - 1x miniPCIe socket with PCIe and USB2.0
 - 802.3at Class 4 PoE
 - 10-30VDC input via barrel-jack

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-10-24 11:34:33 +02:00
Manoj Sai
864ac2cf38 board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.

i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
2022-10-24 11:34:33 +02:00
Manoj Sai
3fb342a53c arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Plus PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.

i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.

Add support for it.

Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP
devicetree file from linux-next tree.
commit <aec8ad34f7f24> (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit)

Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-24 11:34:33 +02:00
Manoj Sai
068782b498 arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam.

General features:
- NXP i.MX8M Plus
- Up to 4GB LDDR4
- 8 eMMC
- Gigabit Ethernet
- USB 3.0, 2.0 Host/OTG
- PCIe 3.0 interface
- I2S
- LVDS
- rest of i.MX8M Plus features

i.Core MX8M Plus needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Add support for it.

Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam devicetree file from linux-next tree.
commit <eefe06b295087> (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM)

Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-24 11:34:33 +02:00
Tom Rini
f35e37cffd First set of u-boot-at91 fixes for the 2023.01 cycle
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Merge tag 'u-boot-at91-fixes-2023.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91

First set of u-boot-at91 fixes for the 2023.01 cycle:

This small fixes set includes an indentation fix for sam9x60 DT and one
name for one pin for sama7g5.
2022-10-21 08:33:48 -04:00
Fabio Estevam
0db6a8110c imx8mn-venice-u-boot: Fix broken boot
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree.  This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot.  Fix this by adding the spba node to the spl
device tree to restore normal booting.

Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.

Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-21 11:54:13 +02:00
Fabio Estevam
8b4f9595ae imx8mn-ddr4-evk-u-boot: Fix broken boot
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree.  This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot.  Fix this by adding the spba node to the spl
device tree to restore normal booting.

Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.

Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-21 11:54:13 +02:00
Fabio Estevam
750d7ddf2c imx8mm_evk: Add Serial Download Protocol support
Add Serial Download Protocol support as it is a useful method to
load flash.bin to RAM and run it via 'uuu'.

With this patch, it is possible to start both U-Boot SPL and U-Boot
proper using the following 'uuu'command:

$ uuu -brun spl flash.bin

Based on a patch from Marek Vasut for the imx8mm-mx8menlo board.

Also, to fit the SPL binary into the internal RAM, select CONFIG_LTO
to reduce its size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-10-21 11:54:13 +02:00
Marek Vasut
60929b0506 ARM: dts: imx8m: imx8mm-mx8menlo: Enable SPL SDP support
Enable DM USB, DM PHY and USB gadget support in imx8mm-mx8menlo SPL
to let the board continue SDP loading of second stage after the first
stage was loaded by BootROM SDP implementation. It is not possible to
jump back into BootROM v1 and let the BootROM implementation continue
the SDP loading, all this has to be performed by the U-Boot CI HDRC
controller driver and SDP protocol implementation, both of which fit
into the SPL just barely.

With this patch, it is possible to start both U-Boot SPL and U-Boot
using e.g. uuu on this board as follows:

$ uuu -brun spl flash.bin

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-10-21 11:54:13 +02:00
Mihai Sain
17e21d7cbf ARM: dts: at91: sama7g5: fix signal name of pin PB2
The signal name of pin PB2 with function F is FLEXCOM11_IO1
as it is defined in the datasheet.

Fixes: 558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-10-21 08:59:27 +03:00
Dario Binacchi
275943dba4 ARM: dts: at91: sam9x60ek: fix indentation for pinctrl sub-nodes
The indentation went far on the right due to an extra tab for
each pinctrl sub-nodes.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-10-21 08:59:16 +03:00
Tom Rini
145a996592 Merge tag 'u-boot-rockchip-20221020' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- dts update and sync for rk356x, rk3288, rk3399 from Linux;
- Add rk3399 EAIDK-610 board support;
- Update for puma-rk3399 board;
- some fix and typo fix in different drivers;
2022-10-20 22:32:38 -04:00
Marek Vasut
5302576e93 ARM: dts: imx8mm: Swap i.MX8M Mini Menlo board UARTs back
The first production revision of the MX8M Mini Menlo board implements
a hardware change which swaps console UART and another UART connector.
Implement the swap, which maps the console UART back to the way Verdin
console is mapped.

Signed-off-by: Marek Vasut <marex@denx.de>
2022-10-20 17:35:52 +02:00
Tim Harvey
6fe5df86fb arm: dts: imx8mm-venice-gw7903: add dig1_ctl and dig2_ctl gpios
The GW7903 revision B adds two additional GPIO's to control the
direction of the 2 isolated digital I/O circuits.

Define them as:
 - dig1_ctl
 - dig2_ctl

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-10-20 17:35:52 +02:00
Tim Harvey
22adeef0f2 arm: dts: imx8mp-venice-gw74xx: update M2 gpio hogs
Update the M2 socket gpio hogs such that they are not active on boot by
flagging them as GPIO_ACTIVE_HIGH so that 'output-high' drives high.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-10-20 17:35:52 +02:00
Tim Harvey
35a9b62400 arm: dts: imx8mp-venice-gw74xx: fix uart configuration gpio hogs
Update the UART config gpio hogs such that it is configured for RS232
by default on boot. Additionally rename them to match the names used
on the reset of the venice boards.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-10-20 17:35:52 +02:00
Frieder Schrempf
5bc21d3869 imx: kontron-sl-mx8mm: Prepare for I2C display detection in environment script
Enable the I2C bus and set a env variable for the reset GPIO of the touch
controller. This allows us to probe the panel in a script.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
ba30cc2227 imx: kontron-sl-mx8mm: Add support for Kontron Electronics SoM SL i.MX8MM OSM-S
This adds support for the Kontron Electronics SoM SL i.MX8MM OSM-S
and the matching baseboard BL i.MX8MM OSM-S.

The SoM hardware complies to the Open Standard Module (OSM) 1.0
specification, size S (https://sget.org/standards/osm).

The existing board configuration for the non-OSM SoM is reused and
allows to detect the SoM variant at runtime.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
b314c0980a imx: kontron-sl-mx8mm: Use voltage rail names from schematic for PMIC regulator-names
Improve the naming of the regulators to contain the voltage rail
names from the schematic.

Suggested-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
8fd4c05cec imx: kontron-sl-mx8mm: Use the VSELECT signal to switch SD card IO voltage
It turns out that it is not necessary to declare the VSELECT signal as
GPIO and let the PMIC driver set it to a fixed high level. This switches
the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5
accordingly.

Instead we can do it like other boards already do and simply mux the
VSELECT signal of the USDHC interface to the pin. This makes sure that
the correct voltage is selected by setting the PMIC's SD_VSEL input
to high or low accordingly.

Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
dfbdc69c5d imx: kontron-sl-mx8mm: Adjust devicetree names, compatibles and model strings
This adjusts the names of the boards and SoMs to the official naming
used by Kontron marketing. These changes also affect devicetree
names and compatibles. The same changes have been submitted to the
Linux kernel.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
8dd0924ea0 imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint
The new stable configuration is missing the 100mt setpoint, remove
it before updating the config to make sure the changes are separated
cleanly.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
2a6f023061 imx: kontron-sl-mx8mm: Add redundant environment and SPI NOR partitions
Enable the redundant environment feature to allow falling back in case of
storage corruption. The partition layout for the SPI NOR device is added
to the devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
a06c6b2130 imx: kontron-sl-mx8mm: Remove LVDS board type and devicetrees
The display isn't and won't be used in U-Boot. Also the display setup
is not yet supported in mainline Linux, so even for cases where the
U-Boot devicetree is passed to the kernel there is currently no use
for this configuration.

Selecting the proper configuration in the kernel FIT image automatically
depending on the detected hardware can be handled by a script in the
environment.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-20 17:35:51 +02:00
Frieder Schrempf
9ab5204628 imx: imx6ul: kontron-sl-mx6ul: Sync devicetrees
Sync the devicetrees with Linux and adjust the board names.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-10-20 17:35:51 +02:00
Tim Harvey
b872c93beb arm: dts: imx8mm-venice-gw7902: add LTE modem gpios
Add missing LTE_PWR# and LTE_RST gpio pinmux.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2022-10-20 17:35:51 +02:00
Tom Rini
73ceadcd72 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Beside some rather unexciting sync of the DTs from the kernel tree, and
some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner
family, to support boards with the F1C200s (64MB DRAM) better. We will
get actual board support as soon as the DTs have passed the Linux review
process.
There is also support for the X96 Mate TV Box, featuring the H616 SoC and
a full 4GB of DRAM.
Also we found the secret to enable SPI booting on the H616 (pin PC5 must
be pulled to GND), so the SPI boot support patch is now good to go.

Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano,
X96 Mate and OrangePi Zero.
2022-10-20 08:58:05 -04:00
Andre Przywara
843ed983a0 suniv: add UART1 support
Some boards with the Allwinner F1C100s family SoCs use UART1 for its
debug UART, so define the pins for the SPL and the pinmux name and mux
value for U-Boot proper.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19 14:15:02 +01:00
Andre Przywara
b87fb19668 suniv: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig
So far we stated the lack of a lowlevel() init function for the
Allwinner F1C100s board by defining the respective SKIP_* symbol in the
board's defconfig. However we don't expect any *board* to employ such
low level code, so expect this to be never used for the ARMv5 Allwinner
SoCs.

Select the appropriate symbols in the Kconfig, so that we can remove
them from the defconfig, and avoid putting them in future defconfigs for
other boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19 14:15:02 +01:00
Andre Przywara
1bf98bd4e2 sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MB
Traditionally we assumed that every Allwinner board would come with at
least 256 MB of DRAM, and set our DRAM layout accordingly. This affected
both the default load addresses, but also U-Boot's own address
expectations (like being loaded at 160 MB).

Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So
far we special-cased those *chips*, as there was only one chip per DRAM
size. However new chips force us to take a more general approach.

Introduce a Kconfig symbol, which provides the minimum DRAM size of the
board. If nothing else is specified, we use 256 MB, and default to
smaller values for those co-packaged SoCs.
Then select the different DRAM maps according to this new symbol, so
that different SoCs with the same DRAM size can share those definitions.

Inspired by an idea from Icenowy.

This is just refactoring: compiled for all boards before and after this
patch: the binaries were identical.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19 14:15:02 +01:00
Icenowy Zheng
9a916b07fe sunxi: fix SUNIV build when enabling D-Cache
The enable_caches function in architecture-specific board code is only
necessary for V7A CPUs, code for both V8A and ARM926 have already
declared this function.

Only provide our implementation of enable_caches() for V7A CPUs.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-10-19 14:15:02 +01:00
FUKAUMI Naoki
85a8ef1264 arm: dts: rockchip: rk356x: sync with Linux 6.0
prepare for rk3566 based board

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:49 +08:00
Quentin Schulz
bd9b4ac9c5 rockchip: puma-rk3399: migrate to u-boot-rockchip-spi.bin
Now that a single binary containing TPL/SPL correctly formatted for SPI
flashes and U-Boot proper, can be generated by binman, let's do it.

Also update the documentation to tell the user to use this newly
generated file instead of manually generating and flashing the binaries.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:49 +08:00
Quentin Schulz
35f571b56c rockchip: puma-rk3399: migrate to u-boot-rockchip.bin
The offset of the SPL payload on Puma is different than for other
Rockchip devices in that it is stored at offset 256K instead of much
further away in the MMC.

Flashing one binary instead of two at different offsets is much more
user friendly so let's migrate to it by modifying the offset in the Puma
specific Device Tree.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:49 +08:00
Quentin Schulz
2169e29c5a rockchip: puma-rk3399: migrate to TPL
Depending on the toolchain used to compile the SPL for Puma RK3399-Q7
module, the board does not boot because the resulting binary is too big
to fit in SRAM.

Let's add a TPL so that there's no need to fiddle with or hack the
defconfig to have a working bootloader.

This follows what's been done for the majority of other RK3399-based
boards.

See the original commit for the first migrations:
bdc0008011 "rockchip: rk3399: update defconfig for TPL"

Unfortunately, the offset in SPI-NOR for U-Boot proper needs to be
modified, since the move from SPL to TPL+SPL for idbloader.img (and the
"only the first 2KB per 4KB blocks are written" "hack" for rkspi format)
increased the size above 256KB. Let's move it to 512KB to, hopefully, be
safe.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:49 +08:00
Quentin Schulz
e936e0ec58 rockchip: puma-rk3399: allow non-SD-Card-loaded SPL to load U-Boot proper from SD-Card
Trying to load U-Boot proper from SPL when SPL was not loaded from
SD-Card is currently not working because the SDMMC pins aren't muxed
correctly. It is assumed the BootROM is doing this for us when booting
from SD-Card hence why it's not needed when booting TPL/SPL from
SD-Card.

The pinctrl properties are removed from the SPL DT property removal list
and the pinctrl configuration nodes made available in the SPL DT, in
addition to the pull-up configurations to allow loading U-Boot proper
from SD-Card as a fallback mechanism for SPI-NOR and eMMC.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:49 +08:00
Quentin Schulz
c9bc7f988f rockchip: puma-rk3399: use gpio-hog instead of fixed-regulator for enabling eMMC/SPI-NOR
On Haikou devkit, it is possible to disable eMMC and SPI-NOR to force
booting from SD card or USB via rkdeveloptool by toggling a switch. This
switch needs to be overridden in software to be able to access eMMC and
SPI-NOR once the device has booted from SD Card. Puma SoM can override
this pin via gpio3_d5.

Until now, fixed regulator device was abused to model this, but since
there's now support for GPIO hogs, let's use it.

Since we want to be able to boot the SPL from SD Card but give it the
ability to load U-Boot proper from a fallback medium such as eMMC and
SPI-NOR, SPL support for GPIO hogs needs to be enabled too. Support for
other kinds of regulators are not needed anymore, so let's disable them.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:49 +08:00
Andy Yan
25e9a63a53 rockchip: rk3399: Add EAIDK-610 support
Specification
- Rockchip RK3399
- LPDDR3 4GB
- TF sd scard slot
- eMMC
- AP6255 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1 work in otg mode
- 12V DC Power supply

The dts file is sync from linux-next[0].

[0]:https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Quentin Schulz
d0af506625 rockchip: px30: support debug uart on UART0
UART0 can obviously also be used for debug uart in U-Boot, so let's add
its support.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Quentin Schulz
d774b2651a rockchip: rk3399: fix incorrect ifdef check on SPL_GPIO
The check to perform is on CONFIG_SPL_GPIO and not SPL_GPIO.
Because this was never compiled in, it missed an include of cru.h that
was not detected before. Let's include it too.

Also switch to IS_ENABLED in-code check as it is the preferred
inclusion/exclusion mechanism.

Fixes: 07586ee432 ("rockchip: rk3399: Support common spl_board_init")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Quentin Schulz
3a61ee7fae rockchip: rk3399: fix incorrect ifdef check on SPL_DM_REGULATOR
The check to perform is on CONFIG_SPL_DM_REGULATOR and not
SPL_DM_REGULATOR. Also switch to in-code check instead of ifdefs.

Fixes: 07586ee432 ("rockchip: rk3399: Support common spl_board_init")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> # Rock960
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Johan Jonker
6554464951 arm: dts: rockchip: rk3288: partial sync from Linux
Partial sync of rk3288.dtsi from Linux version 5.18

Changed:
  only properties and functions that are not yet included
  swap some clocks positions
  fix some irq numbers
  style and sort nodes

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Johan Jonker
6880ebd965 arm: dts: rockchip: update cpu and gpu nodes
In order to better compare the Linux rk3288.dtsi version
with the u-boot version update the cpu and gpu nodes.

Changed:
  use operating-points-v2
  update thermal for all cpus
  add labels to all cpus
  change gpu compatible
  change gpu interrupt names

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Johan Jonker
4fd6c2808c arm: dts: rockchip: rk3288: move thermal sub nodes to dtsi
In order to better compare the Linux rk3288.dtsi version
with the u-boot version move thermal sub nodes to the dtsi
file and remove rk3288-thermal.dtsi

Changed:
  replace underscore in nodename
  remove comments about sensor and ID
  use gpu phandle
  add #cooling-cells to gpu node
  lower critical temparature
  remove linux,hwmon property

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Johan Jonker
f9c68a566c rockchip: phycore_rk3288: remove phycore_init() function
The phycore_rk3288 board has a SPL size problem,
so remove phycore_init() function to stay within the limits.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Andrew Davis
e1e8fdfa6d arm: mach-k3: Move hardware handling to common files
These hardware register definitions are common for all K3, remove
duplicate data them by moving them to hardware.h.

While here do some minor whitespace cleanup + grouping.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-10-18 13:40:40 -04:00
Andrew Davis
b0931d1bd1 arm: mach-k3: security: Use dma-mapping for cache ops
This matches how this would be done in Linux and these functions
do the alignment for us which makes the code look cleaner.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-10-18 13:40:40 -04:00
Andrew Davis
fc95f83ec9 arm: mach-k3: common: Set boot_fit on non-GP devices
This matches what we did for pre-K3 devices. This allows us to build
boot commands that can check for our device type at runtime.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-10-18 13:40:40 -04:00
Dave Gerlach
f020cff02b arm: dts: k3-am64-evm: EMIF tool update to v0.08.40 for 1600MT/s DDR4
Move to latest DDR4 1600MT/s for k3-am64-evm based on EMIF tool
v0.08.40.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
2022-10-18 09:48:22 -04:00
Dave Gerlach
8359b9982a arm: dts: k3-am64-sk: EMIF tool update to v0.08.40 and move to 1600MT/s LPDDR4
Move k3-am64-sk to use 1600MT/s LPDDR4 configuration and update to latest EMIF
tool v0.08.40.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
2022-10-18 09:48:22 -04:00
Tom Rini
700b4fe782 Update uclass iterators to work better when devices fail to probe
Support VBE OS requests / fixups
 Minor error-handling tweaks to bootm command
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Merge tag 'dm-pull-18oct22' of https://source.denx.de/u-boot/custodians/u-boot-dm

Update uclass iterators to work better when devices fail to probe
Support VBE OS requests / fixups
Minor error-handling tweaks to bootm command
2022-10-18 07:36:52 -04:00
Andre Przywara
e50ee3a8d7 sunxi: SPL SPI: Add SPI boot support for the Allwinner H616 SoC
The H616 SoC uses the same SPI IP as the H6, also shares the same clocks
and reset bits.
The only real difference is a slight change in the pin assignment: the
H6 uses PC5, the H616 PC4 instead. This makes for a small change in
our spi0_pinmux_setup() routine.

Apart from that, just extend the H6 #ifdef guards to also cover the H616,
using the shared CONFIG_SUN50I_GEN_H6 symbol.
Also use this symbol for the Kconfig dependency.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Ivan Shishkin <s45rus@gmail.com>
2022-10-18 08:15:59 +01:00
Andre Przywara
ceda40a8e6 sunxi: dts: arm: update devicetree files
Update the devicetree files from the Linux kernel, version v6.0-rc4.
This is covering the 32-bit SoCs, from arch/arm/boot/dts/.

This avoids the not backwards-compatible r_intc binding change, to allow
older kernels to boot, but the other nodes are updated.

Not much change here, the vast majority is actually cosmetic: node names
and using symbolic names for the the RTC clocks.
The R40 boards gain DVFS support.
Some A23/A33 tablet DTs are unified into a single file.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-18 08:18:22 +01:00
Andre Przywara
7f53f5093b sunxi: dts: arm64: update devicetree files
Update the devicetree files from the Linux kernel, version v6.0-rc4.
This is covering the 64-bit SoCs, from arch/arm64/boot/dts/allwinner.

This avoids the not backwards-compatible r_intc binding change, to allow
older kernels to boot, but the other nodes are updated.

Not much change here, the vast majority is actually cosmetic: node names
and using symbolic names for the the RTC clocks.
Some A64 boards gain some audio nodes.
The H616 DTs are now switched to the version finally merged into the
kernel, which brings some changes, but none affecting U-Boot.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-18 08:15:59 +01:00
Patrick Delaunay
c37a668481 stm32mp: fix compilation issue with DEBUG_UART
Fix the compilation issue when CONFIG_DEBUG_UART is activated

 drivers/serial/serial_stm32.o: in function `debug_uart_init':
 drivers/serial/serial_stm32.c:291: undefined reference to \
    `board_debug_uart_init'

The board_debug_uart_init is needed for SPL boot, called in
cpu.c::mach_cpu_init(); it is defined in board/st/stm32mp1/spl.c.

But with the removal #ifdefs patch, the function debug_uart_init() is
always compiled even if not present in the final U-Boot image.

This patch adds a file to provided this function when DEBUG_UART and SPL
are activated.

Fixes: c8b2eef52b ("stm32mp15: tidy up #ifdefs in cpu.c")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-18 08:40:59 +02:00
Patrick Delaunay
637a370251 ARM: dts: stm32: update SCMI dedicated file
The PWR regulators don't need be removed as they are already deactivated.
This patches is a alignment with the accepted patch in Linux device tree
in commit a34b42f8690c ("ARM: dts: stm32: fix pwr regulators references
to use scmi").

Fixes: 69ef98b209 ("ARM: dts: stm32mp15: alignment with v5.19")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-18 08:37:21 +02:00
Marek Vasut
1587e689b3 ARM: dts: stm32: Fix and expand PLL configuration comments
Fix the frequencies listed in PLL configuration comments to match
the actual frequencies programmed into hardware. Furthermore, add
a comment which explains how those frequencies are calculated, so
it won't be necessary to look it up all over the datasheet and
make more mistakes in the calculation in the future.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-10-18 08:36:10 +02:00
Marek Vasut
0de10e2fe1 ARM: dts: stm32: Add DHCOR based Testbench board
Add DT for DHCOR Testbench board, which is a testbench for testing of
DHCOR SoM during manufacturing. This is effectively a trimmed down
version of AV96 board with CSI-2 bridge, HDMI bridge, WiFi, Audio and
LEDs removed and used as GPIOs instead. Furthermore, the PMIC Buck3
is always configured from PMIC NVM to cater for both 1V8 and 3V3 SoM
variant.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-18 08:34:25 +02:00
Marek Vasut
f8edb1e79c ARM: dts: stm32: Drop extra newline from AV96 U-Boot extras DT
Remove duplicate newline, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-18 08:33:20 +02:00
Marek Vasut
34be2ada13 ARM: dts: stm32: Remove buck3 regulator-always-on on AV96
In case the regulator-always-on is present in regulator DT node,
the regulator is always reconfigured to the voltage set in DT on
probe, even if regulator_set_value() has been called before. Drop
the property from AV96 U-Boot DT and enable the regulator manually
in code, as the board already reconfigures the Buck3 regulator in
code per PMIC NVM content instead.

Fixes: 0adf10a87b ("ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-18 08:20:35 +02:00
Michal Suchanek
1d0617bd74 dm: treewide: Use uclass_next_device_err when accessing second device
There are a couple users of uclass_next_device return value that get the
first device by other means and use uclass_next_device assuming the
following device in the uclass is related to the first one.

Use uclass_next_device_err because the return value from
uclass_next_device will be removed in a later patch.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Michal Suchanek
c726fc01cf dm: treewide: Use uclass_first_device_err when accessing one device
There is a number of users that use uclass_first_device to access the
first and (assumed) only device in uclass.

Some check the return value of uclass_first_device and also that a
device was returned which is exactly what uclass_first_device_err does.

Some are not checking that a device was returned and can potentially
crash if no device exists in the uclass. Finally there is one that
returns NULL on error either way.

Convert all of these to use uclass_first_device_err instead, the return
value will be removed from uclass_first_device in a later patch.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00
Sean Anderson
3ed84e73fb arm: layerscape: Disable unused parts of ICID tables
Several parts of the ICID table are only necessary for U-Boot proper.
Disable them in SPL. This saves around 500 bytes.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-10-18 09:32:52 +08:00
Sean Anderson
3d970cb264 arm: layerscape: Don't select FSL_IFC when booting from SD card
FSL_IFC should only be selected when booting from NAND flash (or when
NAND_FSL_IFC is enabled). The existing logic does this correctly when
QSPI is also enabled, but not when just booting from SD.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-10-18 09:32:51 +08:00
Sean Anderson
8fd111351c arm64: layerscape: Support SYSRESET
CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable
our version when it is enabled.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-10-17 15:17:56 +08:00
Sean Anderson
0c3eec2aea arm64: ls104x: Enable eDMA snooping
This enables eDMA snooping on the LS1043A and LS1046A. This will allow
marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent.
Oddly, this bit is only documented for the LS1043A, and is marked as
"reserved" in the LS1046ARM. I have tested this patch on the LS1046A
and found that marking i2c0 as dma-coherent works without issue.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-10-17 15:17:56 +08:00
Tom Rini
300077cf8c Xilinx changes for v2023.01-rc1 (round 3)
fpga:
 - Create new uclass
 - Get rid of FPGA_DEBUG and use logging infrastructure
 
 zynq:
 - Enable early EEPROM decoding
 - Some DT updates
 
 zynqmp:
 - Use OCM_BANK_0 to check config loading permission
 - Change config object loading in SPL
 - Some DT updates
 
 net:
 - emaclite: Enable driver for RISC-V
 
 xilinx:
 - Fix static checker warnings
 - Fix GCC12 warning
 
 sdhci:
 - Read PD id from DT
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Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc1 (round 3)

fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure

zynq:
- Enable early EEPROM decoding
- Some DT updates

zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates

net:
- emaclite: Enable driver for RISC-V

xilinx:
- Fix static checker warnings
- Fix GCC12 warning

sdhci:
- Read PD id from DT
2022-10-11 09:57:08 -04:00
Michael Trimarchi
9f46b8637f imx: gpmi: Add register needed to control nand bus timing
It is used as delay for gpmi write strobe.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-09 10:42:26 +02:00
Venkatesh Yadav Abbarapu
c9e28930e3 arm64: zynqmp: Fix compiler warnings in mp.c
make W=1 generates the following warning in cpu_disable, cpu_status and
cpu_release functions.

arch/arm/mach-zynqmp/mp.c:166:16: warning: comparison of unsigned expression
in '>= 0' is always true [-Wtype-limits]
166 |         if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
    |                ^~

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221004053454.25470-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-07 11:29:48 +02:00
Jim Liu
9ca71c9c19 arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Add basic support for the Nuvoton NPCM845 EVB (Arbel).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-06 21:05:17 -04:00
Pali Rohár
ae17910117 armv8: cache_v8: Fix pgtables setup when MMU is already enabled
When MMU is already enabled then dcache_enable() does not call mmu_setup()
and so setup_all_pgtables() is also never called.

In this situation when some driver calls mmu_set_region_dcache_behaviour()
function then U-Boot crashes with error message:

    Emergency page table not setup.

Fix this issue by explicitly calling setup_all_pgtables() in dcache_enable()
function near condition for mmu_setup().

This change fixes chainloading U-Boot from U-Boot on Turris Mox board which
uses mvneta ethernet driver which calls mmu_set_region_dcache_behaviour().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-06 21:05:17 -04:00
Ovidiu Panait
85e68ae001 common/board_f: move CONFIG_MACH_TYPE logic to arch/arm/lib/bdinfo.c
asm/mach_type.h header and CONFIG_MACH_TYPE macro are arm-specific, so move
related bdinfo logic to arch_setup_bdinfo() in arch/arm/lib/bdinfo.c.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
2022-10-06 21:05:17 -04:00
Pali Rohár
8092d1dd41 arm: mvebu: Add support for specifying VHV_Enable GPIO
VHV_Enable GPIO is required to enable during eFuse programming on Armada
SoCs not from 3700 family. Add support for enabling and disabling VHV pin
via GPIO during eFuse programming, when specified.

All details are in Marvell AN-389: ARMADA VHV Power document
(Doc. No. MV-S302545-00 Rev. C, August 2, 2016).

Note that due to HW Errata 3.6 eFuse erroneous burning (Ref #: HWE-3718342)
VHV power must be disabled while core voltage is off to prevent erroneous
eFuse programming.

This is specified in Marvell ARMADA 380/385/388 Functional Errata,
Guidelines, and Restrictions document
(Doc. No. MV-S501377-00 Rev. D, December 1, 2016).

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-10-06 10:15:35 +02:00
Pali Rohár
3b44b3fdf2 arm: mvebu: Add support for programming LD0 and LD1 eFuse
This patch implements LD eFuse programming support. Armada 385 contains two
LD eFuse lines, each is 256 bit long with one additional lock bit. LD 0
line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. U-Boot
32-bit fuse words 0-8 are mapped to LD eFuse line bits 0-255. U-Boot fuse
word 9 is mapped to LD eFuse line lock bit.

So to program LD 1 General Purpose Data line, use U-Boot fuse command:

    => fuse prog -y 65 0 0x76543210
    => fuse prog -y 65 1 0xfedcba98
    => fuse prog -y 65 2 0x76543210
    => fuse prog -y 65 3 0xfedcba98
    => fuse prog -y 65 4 0x76543210
    => fuse prog -y 65 5 0xfedcba98
    => fuse prog -y 65 6 0x76543210
    => fuse prog -y 65 7 0xfedcba98
    => fuse prog -y 65 8 0x1

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-10-06 10:15:35 +02:00
Stefan Roese
2de00f342f arm: mvebu: Remove timer.c
Since the move to CONFIG_TIMER with support for CONFIG_TIMER_EARLY, this
platform specific init_timer() function is not needed any more. Let's
remove it completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michael Walle <michael@walle.cc>
Cc: Pali Rohár <pali@kernel.org>
2022-10-06 10:15:35 +02:00
Holger Brunck
88383fd864 board/km: remove kirkwood boards
These boards are out of maintenance and can be removed.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-06 10:13:38 +02:00
Ashok Reddy Soma
5ccf97aeb0 arm64: dts: Remove unused property device_id
Device tree property "xlnx,device_id" is not used anymore, remove it.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220930092548.18453-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05 11:36:54 +02:00
Michal Simek
52a504c5c0 ARM: zynq: Define rtc alias on zc702/zc706
Define rtc alias on zc702/zc706 boards.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/47df614929d49af9f562c103defb92900de9d3e1.1664279424.git.michal.simek@amd.com
2022-10-05 08:43:54 +02:00
Michal Simek
ce92321559 ARM: zynq: Point via nvmem0 alias to eeprom on zc702/zc706
EEPROM stores identification information about board like a board name,
revision, serial number and ethernet MAC address. U-Boot is capable to read
nvmemX aliases and read/display provided information when nvmem alias link
is described.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c63bba87d0400b6bd0f5651fac21d525f12288f5.1664265311.git.michal.simek@amd.com
2022-10-05 08:43:54 +02:00
Tom Rini
2d45913534 Merge branch 'next' 2022-10-03 15:39:46 -04:00
Fabio Estevam
0bd7811ca9 imx8mn-ddr4-evk-u-boot: Fix broken boot
When the imx8mn.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree.  This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot.  Fix this by adding the spba node to the spl
device tree to restore normal booting.

Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.

Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-03 13:38:42 -04:00
Fabio Estevam
a2bf0373b8 imx8mn-venice-u-boot: Fix broken boot
When the imx8mn.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree.  This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot.  Fix this by adding the spba node to the spl
device tree to restore normal booting.

Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.

Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-03 13:38:22 -04:00
Simon Glass
8909066199 dm: core: Drop ofnode_is_available()
This function is also available as ofnode_is_enabled(), so use that
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:11:31 -04:00
Simon Glass
f3543e6944 treewide: Drop image_header_t typedef
This is not needed and we should avoid typedefs. Use the struct instead
and rename it to indicate that it really is a legacy struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
d9d7c20b73 treewide: Drop bootm_headers_t typedef
This is not needed and we should avoid typedefs. Use the struct instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Tom Rini
01c88e3dcd - Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
 - Device tree alignement with kernelv6.0-rc4 for MCU's board
 - Device tree alignement with kernelv6.0-rc3 for MPU's board
 - Update DDR node for STM32MP15
 - Cleanup config file for STM32MP1
 - Update for cmd_stm32key command
 - Fix compatible string to add partitions for STM32MP1
 - Update for stm32programmer tool
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Merge tag 'u-boot-stm32-20220927' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
- Device tree alignement with kernelv6.0-rc4 for MCU's board
- Device tree alignement with kernelv6.0-rc3 for MPU's board
- Update DDR node for STM32MP15
- Cleanup config file for STM32MP1
- Update for cmd_stm32key command
- Fix compatible string to add partitions for STM32MP1
- Update for stm32programmer tool
2022-09-27 08:53:51 -04:00
Tom Rini
55ccdee315 Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
 - Add support for new Versal NET SOC
 
 zynqmp:
 - Use mdio bus for ethernet phy description
 - Wire ethernet phy reset via i2c-gpio
 
 versal:
 - Config cleanup
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Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.01-rc1 (round 2)

xilinx:
- Add support for new Versal NET SOC

zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio

versal:
- Config cleanup
2022-09-26 11:28:14 -04:00
Tom Rini
ffa2c88bcf Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next 2022-09-26 11:27:30 -04:00
Patrice Chotard
3cc471d30a configs: stm32f769-disco: Fix internal flash size
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769
MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for
STM32F746. The flash layout is quite similar between the 2 SoCs :

	STM32F746 			STM32F769
4 *  32KB sectors 			4 *  32KB sectors
1 * 128KB sector 			1 * 128KB sector
3 * 256KB sectors			7 * 256KB sectors

Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:21:02 +02:00
Patrice Chotard
9f603e2fff ARM: dts: stm32: DT sync with kernel v6.0-rc4 for MCU's boards
Device tree alignment with kernel v6.0-rc4.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-26 15:19:57 +02:00
Michal Simek
f2641f066b arm64: versal-net: Add support for mini configuration
Versal NET mini configuration is designed for running memory test. Current
output is on DCC but changing serial0 alias to pl011 will move console to
serial port.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:30 +02:00
Michal Simek
1e681448a3 spi: cadence_qspi: Add support for Versal NET platform
Trivial changes to support cadence ospi driver for Versal NET platform.
Also avoid ospi flash reset for now.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Michal Simek
f6aebdf676 arm64: versal-net: Add support for Versal NET platform
Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar to Versal but it will
likely diverge in longer run.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Pali Rohár
049704f808 board_f: Fix types for board_get_usable_ram_top()
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.

So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.

Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23 15:12:42 -04:00
Weijie Gao
663e6262c5 arm: dts: mt7622: add i2c support
Add both hardware and software i2c support for mt7622.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
bc15e30346 arm: dts: mt7622: force high-speed mode for uart
The input clock for uart is too slow (25MHz) which introduces frequent data
error on both receiving and transmitting even if the baudrate is 115200.

Using high-speed can significantly solve this issue.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
e053ccf6ef board: mediatek: add MT7981 reference boards
This patch adds general board files based on MT7981 SoCs.

MT7981 uses one mmc controller for booting from both SD and eMMC, and the
pins of mmc controller are also shared with spi controller.
So three configs are need for these boot types:

1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND
2. mt7981_emmc_rfb_defconfig - eMMC only
3. mt7981_sd_rfb_defconfig - SD only

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
389ba6986b board: mediatek: add MT7986 reference boards
Add general board files based on MT7986 SoCs.

MT7986 uses one mmc controller for booting from both SD and eMMC.
Both MT7986A and MT7986B use the same pins for spi controller.

Configs for various boot types:
1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B
2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only
3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
ed86e4fba1 arm: mediatek: add support for MediaTek MT7981 SoC
This patch adds basic support for MediaTek MT7981 SoC.
This include the file that will initialize the SoC after boot and its
device tree.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
10c6233696 arm: mediatek: add support for MediaTek MT7986 SoC
This patch adds basic support for MediaTek MT7986 SoC.
This include the file that will initialize the SoC after boot and its
device tree.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Patrick Delaunay
9f7c58dc0d ARM: dts: stm32mp15: update DDR node
Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.

With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c ("ram:
stm32mp1: compute DDR size from DDRCTL registers").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:35:45 +02:00
Patrick Delaunay
e83cef87a8 arm: stm32mp: adapt the command stm32key for STM32MP13x
Change the mask of OTP0 used to close the device on STM32MP
- STM32MP15x: bit 6 of OPT0
- STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device

And support the 2 keys for STM32MP13x
- PKHTH : Hash of the 8 ECC Public Keys Hashes Table
          (ECDSA is the authentication algorithm)
- EDMK : Encryption/Decryption Master Key

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:28:25 +02:00
Patrick Delaunay
fd1f4c9abd arm: stm32mp: support several key in command stm32key
Update the command stm32key to support several keys selected by
key name and managed by the new sub-command:

stm32key list
stm32key select [<key>]
stm32key read -a

This patch doesn't change the STM32MP15 behavior, only PKH is
supported, but it is a preliminary patch for STM32MP13 support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:28:25 +02:00
Patrick Delaunay
8921b3dccd arm: stm32mp: introduced read_close_status function in stm32key command
Split the read_hash_otp function and introduce the helper function
read_close_status to read the close status in OTP separately of the PKH.

This patch is a preliminary step for STM32MP13 support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:28:25 +02:00
Patrick Delaunay
c6327ba40f arm: stm32mp: add defines for BSEC_LOCK status in stm32key command
Add defines for value used in stm32key for BSEC permanent lock status
and error.

This patch is a preliminary step to support more lock status in BSEC
driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:28:25 +02:00
Patrick Delaunay
450036f4ef stm32mp: stm32prog: improve the partitioning trace
Improve the partitioning trace done in command stm32prog:
- remove the trace "partition: Done" when the GPT partitioning is not done
- indicate the mmc instance used for each 'gpt write' command

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:25:29 +02:00
Patrick Delaunay
152498d580 ARM: dts: stm32mp: alignment with v6.0-rc3
Device tree alignment with Linux kernel v6.0-rc3:
- ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp15xx-dkx
- ARM: dts: stm32: Add alternate pinmux for RCC pin
- ARM: dts: stm32: Add alternate pinmux for DCMI pins
- ARM: dts: stm32: Add alternate pinmux for SPI2 pins
- ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15
- ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk
- ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
- ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 14:05:04 +02:00
Patrick Delaunay
93b2d4d0bd stm32mp: stm32prog: correctly handle OTP when SMC is not supported
As the SMC is only supported in SP-MIN for STM32MP15x, the associated
partition should be absent when the TA NVMEM is not available in OPT-TEE
in STM32MP13x.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 13:58:20 +02:00
Patrick Delaunay
3df19b8bec stm32mp: stm32prog: solve warning for 64bits compilation
Solve many compilation warning when stm32prog is activated on the aarch64.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 13:58:20 +02:00
Patrick Delaunay
ada8fe0c42 stm32mp: stm32prog: change default flashlayout location to CONFIG_SYS_LOAD_ADDR
Change the defaut flashlayout location, hardcoded at STM32_DDR_BASE,
to CONFIG_SYS_LOAD_ADDR to avoid issue on board with reserved memory
at STM32_DDR_BASE.

This patch changes the command behavior for STM32MP13 and STM32MP15
platform, as CONFIG_SYS_LOAD_ADDR(0xc2000000) != STM32_DDR_BASE
but without impact for serial boot with STM32CubeProgrammer.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 13:58:20 +02:00
Patrick Delaunay
4d7df7f766 stm32mp: stm32prog: support empty flashlayout
When the STM32CubeProgrammer sent a empty flashlayout.tsv
file, the command stm32prog correctly parse the file
but data->dev_nb = 0 and the stm32prog_devices_init
operations should be skipped.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-23 13:58:20 +02:00
Michal Simek
2b1db7b18c arm64: zynqmp: Wire GEM reset gpio
With ethernet-phy-id driver ETH phy reset can be properly handle that's why
describe it in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5bfd92827033d19617113f4117f37dcf79699a0f.1662721547.git.michal.simek@amd.com
2022-09-21 09:55:19 +02:00
Michal Simek
13622c7a9d arm64: zynqmp: Describe TI phy as ethernet-phy-id
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset. Reset description will be added in separate commit.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com
2022-09-21 09:55:19 +02:00
Marek Vasut
fdf6bbb260 ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock
Pull this LPGPR unlock into common code, since it is used in multiple
systems already.

Signed-off-by: Marek Vasut <marex@denx.de>
2022-09-20 18:30:02 +02:00
Tim Harvey
9bf0cbf396 arm: dts: imx8mm-venice-gw7901: add dsa phy handles to u-boot dtsi
The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.

Fixes: 24a7a3c1c0 ("imx8mm: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-09-20 18:30:02 +02:00
Tim Harvey
1581f17378 arm: dts: imx8mp-venice-gw74xx: add dsa phy handles to u-boot dtsi
The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.

Fixes: e0caa84ca6 ("imx8mp: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-09-20 18:30:02 +02:00
Tom Rini
ebdd6afa54 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-marvell into next
- Enable CONFIG_TIMER for all Kirkwood / MVEBU boards (Stefan)
- u-boot-spl.kwb/SPL: Add / improve size limit setup / detection (Pali)
- mvebu: theadorable: Misc updates in defconfig und dts (Stefan)
2022-09-20 08:50:07 -04:00
Tom Rini
245746e8e0 First set of u-boot-at91 features for the 2023.01 cycle
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Merge tag 'u-boot-at91-2023.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2023.01 cycle:

This feature set includes the important update on PIO4 pinctrl driver
that solves a long time mismatch between Linux and U-boot, related on
the unification of pinctrl and gpio driver support, now respecting the
pinctrl bindings ABI; and also support for pinctrl subnodes. The feature
set also adds support for PDA screen detection for sam9x60_curiosity
board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks.
2022-09-20 08:49:36 -04:00
Stefan Roese
b81db4bfdd arm: mvebu: dts: mvebu-u-boot.dtsi: Add "u-boot, dm-pre-reloc" to timer DT node
Adding the "u-boot,dm-pre-reloc" DT property to the timer node is
necesssary to support the timer in the early boot phases (e.g.
SPL & pre-reloc).

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-20 06:39:43 +02:00
Stefan Roese
d06ba5cc71 arm: mvebu: dts: armada-375.dtsi: Add timer0 & timer1
Add the DT bindings / descriptions for timer0 & timer1, exactly as done
in mainline Linux.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-20 06:39:43 +02:00
Stefan Roese
0cc5d2321f arm: mvebu: dts: Makefile: Compile Armada 375 dtb in a separate step
This patch changes the compilation, so that the Armada 375 board(s) are
compiled in a separate step. This is necessary for the timer dts
conversion, as A375 has a different / timer description in the dts.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-20 06:39:43 +02:00
Stefan Roese
7b530bb19e arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms
Now that the new timer support is available for these platforms, let's
select this IF for all these platforms. This way it's not necessary
that each board changes it's config header.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-09-20 06:39:43 +02:00
Stefan Roese
50e4d8511d arm: mvebu: theadorable: Update eth & mdio DT nodes
With the recent changes in the Marvel mvneta network driver, the MDIO
bus is not connected any more. This patch updates the DT nodes to use
the nodes from the dtsi files instead of creating ad-hoc nodes.

Signed-off-by: Stefan Roese <sr@denx.de>
2022-09-20 06:39:43 +02:00
Tom Rini
e9a1ff9724 Merge branch 'master' into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-19 16:07:12 -04:00
Sergiu Moga
f02e52b7e6 ARM: dts: at91: sama7: Align with Linux Devicetree
This patch makes sure that the Devicetree for the sama7
boards are aligned with the Devicetree from Linux. This
implies removing the GPIO compatible and replacing it
with the PINCTRL one, as well as unifying the SDMMC
pinctrl related subnodes under one single subnode.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2022-09-19 09:51:04 +03:00
Sergiu Moga
2df729e96d ARM: dts: at91: sama5: Align with Linux Devicetree
This patch makes sure that the Devicetree for the sama5
boards are aligned with the Devicetree from Linux. This
implies removing the GPIO compatible and replacing it
with the PINCTRL one, as well as unifying the SDMMC
pinctrl related subnodes under one single subnode.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2022-09-19 09:51:04 +03:00
Durai Manickam KR
3534672200 ARM: dts: at91: sam9x60_curiosity: add onewire support
Add support for onewire memory.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
2022-09-19 09:50:17 +03:00
Michael Trimarchi
cc74cab86a bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2 boards
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.

Add support for imx6ulz BSH SMM M2 board:

- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-09-18 22:56:18 +02:00
Angus Ainslie
466a9ea2a1 board: purism: add the Purism Librem5 phone
Initial commit of Librem5 u-boot and SPL

Signed-off-by: Angus Ainslie <angus@akkea.ca>
Co-developed-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-09-18 22:56:10 +02:00
Marek Vasut
2debd004fe ARM: dts: imx: Fix I2C5 GPIO assignment on i.MX8M Plus DHCOM
Fix copy-paste error of the I2C5 bus recovery GPIO assignment,
the I2C5 GPIOs are on gpio3 instead of gpio5.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18 22:56:10 +02:00
Marek Vasut
dd5ca87464 ARM: dts: imx: Adjust ECSPI1 pinmux on i.MX8M Plus DHCOM
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18 22:56:10 +02:00
Marek Vasut
866a33e478 ARM: dts: imx: Rename imx8mp-dhcom{-pdk2,}-boot.dtsi
Rename imx8mp-dhcom-pdk2-u-boot.dtsi to imx8mp-dhcom-u-boot.dtsi, since
this file is shared by PDK2, PicoITX and DRC02. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18 22:56:10 +02:00
Marek Vasut
a5f29e72d3 ARM: dts: imx: Add SoM compatible to i.MX8M Plus DHCOM PDK2
Add SoM compatible string into i.MX8MP DHCOM PDK2 compatible strings.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18 22:56:10 +02:00
Marek Vasut
aa87db42ff ARM: dts: imx: Drop Atheros PHY header from i.MX8M Plus DHCOM PDK2
This PHY is not used on PDK2, the header was added due to copy-paste
error, drop it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18 22:56:09 +02:00
Marek Vasut
d1aebfab75 ARM: dts: imx: Add HW variant details to i.MX8M Plus DHCOM PDK2
Add information about which exact SoM variant is used on which PDK2 variant.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-09-18 22:56:09 +02:00
Adam Ford
a18f23f977 arm: dts: imx8mn-beacon-kit-u-boot: Fix broken booting
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree.  This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot.  Fix this by adding the spba node to the spl
device tree to restore normal booting.

Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Adam Ford <aford173@gmail.com>
2022-09-18 22:56:09 +02:00
Marcel Ziswiler
a8e518b80a imx: romapi: fix spurious ampersand in address print
Fix spurious ampersand in address print e.g.

	Find img info 0x&480331a0, size 855

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>"
2022-09-18 20:42:56 +02:00
Jesse Taube
505efde27a ARM: dts: imx: add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.

The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.

This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18 20:42:56 +02:00
Jesse Taube
a5b7a87673 ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
Add binding header for i.MXRT1170 pinctrl device tree.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18 20:42:56 +02:00
Jesse Taube
67e2df581c imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
This commit adds board support for i.MXRT1170-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT117x processor family.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-18 20:42:56 +02:00
Stefan Roese
29caf9305b cyclic: Use schedule() instead of WATCHDOG_RESET()
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-18 10:26:33 +02:00
Simon Glass
e33a5c6be5 blk: Switch over to using uclass IDs
We currently have an if_type (interface type) and a uclass id. These are
closely related and we don't need to have both.

Drop the if_type values and use the uclass ones instead.

Maintain the existing, subtle, one-way conversion between UCLASS_USB and
UCLASS_MASS_STORAGE for now, and add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-16 11:05:16 -04:00
Simon Glass
6b03b9d5b7 blk: Enable CONFIG_BLK for all media
Enable this option on all boards which support block devices. Drop the
related depencies on BLK since these are not needed anymore.

Disable BLOCK_CACHE on M5253DEMO as this causes a build error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-16 11:05:00 -04:00
Bernhard Messerklinger
febd82c45e brppt1: Cleanup device tree
* Remove unnecessary device tree nodes which are not needed in
  U-Boot directly.
* Move all U-Boot specific device tree properties to u-boot dtsi.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-09-15 14:22:08 -04:00
Bernhard Messerklinger
b0a18f1f9f brppt1: Fix SPL boot stage
Commit 6337d53fdf ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs
the am335x device tree with the latest linux kernel am335x device tree.
That causes problems with device tree in SPL stage.
To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the
synced bus addresses correctly.
A custom U-Boot device tree is also needed since the SPL build removes
bus properties from bus nodes which are not explicitly marked with the
u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of
the in the SPL needed devices must be marked with u-boot,dm-pre-reloc.
Also since there is no driver for "ti,sysc" compatible property in SPL
the buses marked with this compatible string must also be marked with
compatible = "simple-bus" to make the underlying devices visible in
SPL. Otherwise the matching device drivers aren't found and the uclass
drivers are dropped.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-09-15 14:22:08 -04:00
Bernhard Messerklinger
6dfc1f4c51 brppt1: Remove unused board variants
The SPI and NAND board variants never went into production.
Drop those board variants.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-09-15 14:22:08 -04:00
Nathan Barrett-Morrison
7a0d88076b Add in the ability to load and boot an uncompressed kernel image during the Falcon Mode boot sequence.
This is required for architectures which do not support compressed kernel images (i.e. ARM64).  This is only used while not booting via FIT image.

Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-09-14 15:23:03 -04:00
Chin-Ting Kuo
d37b4f37ea arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.

AST2500:
  - FMC:
      CS number: 3
      controller reg: 0x1e620000 - 0x1e62ffff
      decoded address: 0x20000000 - 0x2fffffff

  - SPI1:
      CS number: 2
      controller reg: 0x1e630000 - 0x1e630fff
      decoded address: 0x30000000 - 0x37ffffff

  - SPI2:
      CS number: 2
      controller reg: 0x1e631000 - 0x1e631fff
      decoded address: 0x38000000 - 0x3fffffff

AST2600:
  - FMC:
      CS number: 3
      controller reg: 0x1e620000 - 0x1e62ffff
      decoded address: 0x20000000 - 0x2fffffff

  - SPI1:
      CS number: 2
      controller reg: 0x1e630000 - 0x1e630fff
      decoded address: 0x30000000 - 0x3fffffff

  - SPI2:
      CS number: 3
      controller reg: 0x1e631000 - 0x1e631fff
      decoded address: 0x50000000 - 0x5fffffff

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-09-13 12:08:40 -04:00
Michal Simek
4e16826028 xilinx: Fix mdio bus description for vck190-sc
Current behavior is that eth_phy_get_mdio_bus

Net:   FEC: can't find phy-handle

ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii
eth0: ethernet@ff0b0000

Net:
ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii
eth0: ethernet@ff0b0000

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5b7da5808136b3f579c0cf7a3431b56c758655e9.1662460749.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
5c341965dd ARM: zynq: DT: List OCM memory
Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high
that's why it is placed on fixed location.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a951dbe885640197efe3e91bb9fa5caedb54b387.1662460712.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
41634fd24b ARM: zynq: Align qspi node name with Linux kernel
Nodes should follow generic rules where compatible and reg properties
should be listed on the top of node. That's why sync it up.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/922dca6227cb0aa4f79e6d3595c5f280ba020684.1662460540.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
9e89e30d4d arm64: versal: Define zynqmp_mmio_write() for versal
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
  378 |   zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Michal Simek
be3a73c0c4 ARM: zynq: Align bss and end of u-boot image to 64bits
The main reason is that DT memory reserved code is expecting DT to be 64bit
aligned. For more information take a look at commit 5bd5ee02b2 ("xilinx:
zynqmp: Check that DT is 64bit aligned").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Piyush Mehta
1bff67eda7 arm64: zynqmp: add ref_clk property for REFCLKPER calculation
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ
calculation. This property configure correct value for SOF/ITP counter
and period of ref_clk.
This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
fd9c9f2932 arm64: zynqmp: Add missing tca6416 to zynqmp SC
Add missing tca6416 i2c gpio controller to SC dts file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a19c191d0dffb213d9dc8809d22728d79cf73a22.1661259623.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Harini Katakam
ddcc161c4e arm: dts: Add xlnx prefix to GEM compatible string
cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx
prefix. Add this new compatible string and retain the existing string for
compatibility with uboot drivers.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a38b1b55132fc026cc09224dba61e42fd03b1a36.1661259558.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Amit Kumar Mahapatra
c8630167e0 arm64: zynqmp: Add mtd partition for secure OS storage area
Update MTD partitions of Kria device trees to allocate 128KB of QSPI
memory for secure OS. Increased "SHA256" partition size & changed
starting address of "User" partition to accommodate the new partition
"Secure OS Storage"

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Pali Rohár
5818198e6a arm: mvebu: Fix moving internal registers
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") moved code from file cpu.c to lowlevel.c,
which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE.

But the steps describing how to do it correctly were documented only in
older U-Boot versions and commit cefd764222 ("arm: mvebu: Fix internal
register config on A38x") probably unintentionally removed important
details about MMU from code comments around.

Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") implemented code movement according to
(now incomplete) comments which resulted in semi-broken code.

The result is that I-cache is currently disabled for all Armada 38x boards
and maybe there are some other (unreported / undetected) issues.

Reimplement it correctly. First flush all caches, then disable MMU and L2
cache and then move Marvell internal registers. There is no need to
explicitly disable I-cache.

After this change lzmadec command with lzma image of 0x7000000 bytes is
doing decompression just 5 seconds. Before this change it was 30 seconds.

To make lowlevel.S code more readable, extend asm/pl310.h header file to be
compatible with assembler and use macros from this file.

Fixes: 5bb2c550b1 ("arm: mvebu: Move internal registers in arch_very_early_init() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 09:04:22 +02:00
Pali Rohár
4f2333ba88 arm: mvebu: Enable L2 cache also on Armada 38x
For some unknown reason when L2 cache is disabled on Armada 385 then loadb,
loadx and loady commands do not work with higher baudrates than 115200
(they just abort transfer) and lzmadec command with lzma image of size
0x7000000 (maybe even smaller, we tested this one) is doing decompression
for more than 2 minutes. After enabling L2 cache decompression takes only
30s and loadb, loadx and loady are stable and working fine.

git bisect identified problematic commit 3308933d2f ("arm: mvebu: Avoid
reading MVEBU_REG_PCIE_DEVID register too many times"). Before this commit
above issues were not present.

But investigation showed that above issue was possible to reproduce also by
reverting that commit and forcing compiler to do inline optimization of
mvebu_soc_family() function. Which seems that the root of this issue is in
caches and position of instruction of segments. So currently it is unknown
what is or was broken, but code movement, code inlining or other compiler
optimization triggered it.

Commit 3e5ce7ceeb ("arm: mvebu: Enable L2 cache on Armada XP") mentioned
that enabling L2 cache on Armada XP improved performance and that Armada
38x has L2 disabled (which is default state) and if needed it has to be
enabled in separate patch. As enabling L2 cache also improve performance
on Armada 38x, enable it.

Note that Aurora cache in no outer mode is available only on Armada XP,
hence it is not touched for Armada 38x code.

Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Reported-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 09:04:22 +02:00
Pali Rohár
a7199f4493 arm: mvebu: lowlevel.S: Use CR_M from asm/system.h
Replace magic constant 1 when disabling MMU by macro CR_M from include
header file asm/system.h.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 09:04:22 +02:00
Pali Rohár
2a0d9ae414 arm: mvebu: Guard non-AXP code by checking for AXP
Commit c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada
XP at all") introduced branch for non-AXP code which was guarded by A38X
condition. Fix this issue by checking for AXP platform, not by A38X.

Fixes: c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada XP at all")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 09:04:22 +02:00
Pali Rohár
117ef65502 arm: mvebu: Fix function enable_caches
Commit 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID
register too many times") broke support for caches on all Armada SoCs.

Before that commit there was code:

    if (mvebu_soc_family() != MVEBU_SOC_A375) {
        dcache_enable();
    }

And after that commit there is code:

    if (IS_ENABLED(CONFIG_ARMADA_375)) {
        dcache_enable();
    }

Comment above this code says that d-cache should be disabled on Armada 375.
But new code inverted logic and broke Armada 375 and slowed down all other
Armada SoCs (including A38x).

Fix this issue by changing logic to:

    if (!IS_ENABLED(CONFIG_ARMADA_375)) {
        dcache_enable();
    }

Which matches behavior prior that commit.

Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 09:04:22 +02:00
Pali Rohár
b120519d76 arm: mvebu: Mark constant data with const keyword
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-13 06:38:08 +02:00
Stefan Herbrechtsmeier
b7e0750d88 zynq: Convert arm twd timer to DM driver
Move arm twd timer driver from zynq to generic location.

DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-12 12:03:17 +02:00
Tom Rini
e9de8c8c64 - simplify the STM32MP15x package parsing code
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
   and enable CONFIG_DM_REGULATOR for stm32f769-disco
 - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
   after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
 - Fix SYS_HZ_CLOCK value for stih410-b2260 board
 - Switch STMM32MP15x DHSOM to FMC2 EBI driver
 - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
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Merge tag 'u-boot-stm32-20220907' of https://source.denx.de/u-boot/custodians/u-boot-stm

- simplify the STM32MP15x package parsing code
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
  and enable CONFIG_DM_REGULATOR for stm32f769-disco
- handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
  after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
- Fix SYS_HZ_CLOCK value for stih410-b2260 board
- Switch STMM32MP15x DHSOM to FMC2 EBI driver
- Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
2022-09-08 08:33:41 -04:00
Sean Anderson
bdbdaede67 ARMv8/sec_firmware: Convert to use fit_get_data_conf_prop
This reduces sec_firmware_get_data to a single call to
fit_get_data_conf_prop. I think sec_firmware_check_copy_loadable could also
be converted, but it does not map as straightforwardly, so I have left it
for a future cleanup.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-07 13:40:45 +08:00
Sean Anderson
1b0e98221d ARMv8/sec_firmware: Remove SEC_FIRMWARE_FIT_CNF_NAME
The config to use for FIT images can be better specified by enabling
CONFIG_MULTI_DTB_FIT and implementing board_fit_config_name_match.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-07 13:40:43 +08:00
Etienne Carriere
d6ff3c9f04 ARM: dts: stm32mp15: remove hwlocks from pinctrl
Removes hwlocks properties from stm32mp151 pinctrl node. These locks
could be used for other purpose, depending on board and software
configuration hence do not enforce their use to protect pinctrl
devices.

This patch is an alignment with Linux device tree with v6.0 as the
hwsem support wasn’t yet added in pincontrol in kernel. It avoids
issues when the Linux kernel is started with the U-Boot device tree.

Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-06 15:40:14 +02:00
Marek Vasut
9cccc358c4 ARM: stm32: Switch DHSOM to FMC2 EBI driver
Perform long overdue conversion of ad-hoc FMC2 EBI bus initialization
to upstream FMC2 EBI driver. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-06 15:33:07 +02:00
Tom Rini
166d2693dd Merge tag 'fsl-qoriq-2022-9-6' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Reset fixes for p1_p2_rdb_pc
Fix use after free issue fix in fsl_enetc.c
Fix for fsl ddr: make bank_addr_bits reflect actual bits
sl28 board update
2022-09-06 08:59:51 -04:00
Patrice Chotard
5468dc82cb ARM: dts: stm32: Fix display-timings settings for stm32f746-disco
Since commit ef4ce6df32 "video: stm32: stm32_ltdc: fix data enable polarity"
The panel display output wasn't functional anymore.
Device tree display-timings de-active property value must be updated
to 1.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-06 14:09:05 +02:00
Patrick Delaunay
50b2184257 stm32mp: simplify the STM32MP15x package parsing code
Simplify the package parsing code for STM32MP15X as package can be
affected with get_cpu_package() result.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-09-06 13:54:50 +02:00
Michael Walle
6622c30f2e armv8: layerscape: spl: mark OCRAM as non-secure
By default the OCRAM is marked as secure. While the SPL runs in EL3 and
thus can access it, DMA devices cannot. Mark the whole OCRAM as
non-secure.
This will fix MMC and SD card boot on LS1028A when using SPL instead of
TF-A.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-06 09:10:41 +08:00
Tom Rini
05f135ab3e Merge tag 'u-boot-rockchip-20220905' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- migrate to use binman for U-Boot image generate on rockchip platform;
- Some fixes for rk3399 and rk3308;
2022-09-04 22:35:40 -04:00
Quentin Schulz
e1faa535b9 rockchip: add u-boot-rockchip-spi.bin image for booting from SPI-NOR flash
This new image is similar to u-boot-rockchip.bin except that it's
destined to be flashed on SPI-NOR flashes.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-04 20:00:39 +08:00
Quentin Schulz
a4bb36df49 rockchip: allow to build SPI images even without HAS_ROM option
This prepares for the creation of a u-boot-rockchip-spi.bin image
similar to u-boot-rockchip.bin to the exception it's destined for
SPI-NOR flashes instead of MMC storage medium.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:39 +08:00
Quentin Schulz
05713d5707 rockchip: generate u-boot-rockchip.bin with binman for ARM64 boards
This allows to build u-boot-rockchip.bin binary with binman for Rockchip
ARM64 boards instead of the legacy Makefile way.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-04 20:00:39 +08:00
Quentin Schulz
001f788cdb rockchip: generate idbloader.img content for u-boot-rockchip.bin with binman for ARM
idbloader.img content - currently created by way of Makefile - can be
created by binman directly.

So let's do that for Rockchip ARM platforms.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:39 +08:00
Quentin Schulz
7a81a44caf rockchip: rk3399: sync spl_boot_devices_tbl and boot_devices node paths
While technically not a bug, let's have some consistency in paths
returned by u-boot,spl-boot-order look-up and the one saved in
u-boot,spl-boot-device by syncing spl_boot_devices_tbl and boot_devices
node paths.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:39 +08:00
Quentin Schulz
72ebe8b8cb rockchip: rk3399: fix incorrect boot-device in u-boot, spl-boot-device
On RK3399, mmc0 is eMMC and mmc1 is SD card, c.f. console:
MMC:   mmc@fe320000: 1, mmc@fe330000: 0

In arch/arm/mach-rockchip/spl-boot-order.c:board_boot_order, the
boot_device (BOOT_DEVICE_*) value is gotten from spl_node_to_boot_device
function. Said function returns BOOT_DEVICE_MMC1 for mmc0 (eMMC) and
BOOT_DEVICE_MMC2 for mmc1 (SD card).

Since the SD card controller is at mmc@fe320000, it should be associated
with BOOT_DEVICE_MMC2 and not BOOT_DEVICE_MMC1. Same applies to eMMC.

Let's fix that by swapping the two BOOT_DEVICEs.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
2022-09-04 20:00:38 +08:00
John Keeping
74f7025ea6 rockchip: rk3308: fix same-as-spl boot order
Rockchip SoCs need the boot_devices array defined in order to map the
bootloader's value to a U-Boot device.  Implement this for rk3308.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:38 +08:00
Quentin Schulz
07b5d348a6 rockchip: rk3399: boot_devices: fix eMMC node name
When idbloader.img is flashed on the eMMC, the SPL still tries to load
from SPI-NOR first.

This is due to an incorrect look-up in the Device Tree. Since commit
822556a934 ("arm: dts: sync the Rockhip 3399 SoCs from Linux"), the
node name (but not label) changed from sdhci@fe330000 to mmc@fe330000
meaning U-Boot SPL is not looking for the correct node name anymore and
fails to find the "same-as-spl" node when eMMC is the medium from which
the SPL booted.

Fixes: 822556a934 ("arm: dts: sync the Rockhip 3399 SoCs from Linux")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Artem Lapkin  <email2tema@gmail.com>
Tested-by: Artem Lapkin  <email2tema@gmail.com>
Tested-by: Lapkin Artem <email2tema@gmail.com>
Tested-by: Lapkin Artem <email2tema@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:38 +08:00
Johan Jonker
69820e02d2 arm: dts: rockchip: rk3288: rename mmc nodenames
The boot_devices constants for rk3288 were changed to match the
binding, but the dtsi file was not synced.
Fix by renaming the rk3288 mmc node names.
Also correct the clock name for "ciu-drive".

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:38 +08:00
Simon Glass
a55014d09b Makefile: Allow LTO to be disabled for a build
LTO (Link-Time Optimisation) is an very useful feature which can
significantly reduce the size of U-Boot binaries. So far it has been
made available for selected ARM boards and sandbox.

However, incremental builds are much slower when LTO is used. For example,
an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7
seconds with LTO enabled.

Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be
disabled during development if needed, for faster builds.

Add some documentation about LTO while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-02 16:20:11 -04:00
Sergei Antonov
583f1b2f10 arm: ARMv4 assembly compatibility
There is currently a problem that U-Boot can not work on ARMv4
because assembly imlementations of memcpy() and some other functions
use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr"
should be used instead).

A working preprocessor-based solution to this problem is found in
arch/arm/lib/relocate.S. Move it to the "ret" macro in
arch/arm/include/asm/assembler.h and change all "bx lr" code
to "ret lr" in functions that may run on ARMv4. Linux source code
deals with this problem in the same manner.

v1 -> v2:
Comment update. Pointed out by Andre Przywara.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
CC: Samuel Holland <samuel@sholland.org>
CC: Ye Li <ye.li@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Marek Vasut <marex@denx.de>
CC: Sean Anderson <sean.anderson@seco.com>
CC: Tom Rini <trini@konsulko.com>
2022-09-02 13:40:42 -04:00
Geert Uytterhoeven
68083b897b renesas: Fix RPC-IF compatible values
The compatible values used for device nodes representing Renesas Reduced
Pin Count Interfaces were based on preliminary versions of the Device
Tree Bindings.

Correct them in both DTSi files and drivers, to match the final DT
Bindings.

Note that there are no DT bindings for RPC-IF on RZ/A1 yet, hence the
most logical SoC-specific value is used, without specifying a
family-specific value.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-02 13:25:01 +02:00
Geert Uytterhoeven
e17205d067 ARM: dts: rmobile: Fix RPC-IF device node names
According to the Generic Names Recommendation in the Devicetree
Specification Release v0.3, and the DT Bindings for the Renesas Reduced
Pin Count Interface, the node name for a Renesas RPC-IF device should be
"spi".  Especially on R-Car Gen3 and RZ/G2, the node name matters, as
the node is enabled by passing a DT fragment from TF-A to U-Boot, and
from U-Boot to subsequent software.

Fix this by renaming the device nodes from "rpc" to "spi".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-02 13:25:01 +02:00
Philip Oberfichtner
b6664eace8 ARM: cache: Allow SPL to build cache-pl310.c
Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the
SPL to build cache-pl310.c.

Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.

After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.

[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-09-01 17:18:42 -04:00
Philip Oberfichtner
111688839a Convert CONFIG_SYS_L2_PL310 to Kconfig
This converts CONFIG_SYS_L2_PL310 to Kconfig.

For omap2 and mvebu the 'select SYS_L2_PL310' locations were
determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.

For mx6 I manually chose ARCH_MX6 as 'select' location. The
correctness has been verified using

	$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF
	0 matches

That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this
was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert
the 'select' statement under ARCH_MX6.

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-09-01 17:18:42 -04:00
Sean Anderson
f4b540e25c arm: smh: Fix uninitialized parameters with newer GCCs
Newer versions of GCC won't initialize parts of structures which don't
appear to be used. This results in uninitialized semihosting parameters
passed via R1. Fix this by marking the inline assembly as clobbering
memory.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-08-31 12:21:47 -04:00
Sumit Garg
0ddabb6830 arm: dts: qcom: Sync pinctrl DT nodes with Linux bindings
Currently for all Qcom SoCs/boards there are separate compatibles for
GPIO and pinctrl. But this is inconsistent with official (upstream) Linux
bindings which requires only a single compatible "qcom,<SoC name>-pinctrl"
and there is no such compatible property as "qcom,tlmm-<SoC name>".

So fix this inconsistency for Qcom SoCs in order to comply with upstream
DT bindings. This is done via removing compatibles from "msm_gpio" driver
and via binding to "msm_gpio" driver from pinctrl driver in case
"gpio-controller" property is specified for pinctrl node.

Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:46 -04:00
Sumit Garg
a4b99582bb pinctrl: sdm845: Remove redundant CONFIG_SDM845 check
DT compatible is sufficient to make platform specific differentiation,
so remove redundant CONFIG_SDM845 check.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-08-26 10:55:46 -04:00
Sumit Garg
106822de5e board: qcs404-evb: Enable USB3 specific PMIC GPIO
For USB3 host controller to detect devices on the bus it is required to
enable a PMIC GPIO: usb_vbus_boost_pin. So enable that during board
specific initialization.

And since this PMIC GPIO parsing is quite u-boot specific, so add a
DT override to qcs404-evb-uboot.dtsi to represent usb_vbus_boost_pin.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:46 -04:00
Sumit Garg
9c96a0c62a dts: qcs404-evb: Add PMIC GPIO controller node
PMIC GPIOs are special GPIOs which are accessible through SPMI bus. So
add corresponding DT nodes.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:46 -04:00
Sumit Garg
0c1eab6f75 dts: qcs404-evb: Add USB controller and PHY nodes
QCS404 SoC provides support for two USB controllers: one USB3 and the
other one being USB2. The USB3 controller supports further 2 PHY: one high
speed PHY and the other super speed PHY. The USB2 controller supports a
single high speed PHY. So add corresponding DT nodes.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:45 -04:00
Sumit Garg
968597b85c clocks: qcs404: Add support for USB clocks
Add support for USB controller and PHY clocks for QCS404 SoC.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:45 -04:00
Sumit Garg
c9e384e9b6 clocks: qcom: Add clock enable callback support
Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks.
So add corresponding support for Qcom clock drivers.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:45 -04:00
Sumit Garg
21ed4563cb dts: qcs404-evb: Add reset controller node
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-26 10:55:45 -04:00
Davidson K
42f051ceb6 arm: total_compute: enable psci
psci is used for system reset

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
2022-08-26 10:55:45 -04:00
Michael Walle
5dbf2f0de7 board: lsxl: disable eth0
The board has only one network interface. The linux kernel will
gracefully skip a the ethernet interface if no connected PHY could be
probed. u-boot on the other hand will throw an error message. The kernel
device tree is about to be fixed. For now, just disable the ethernet
interface in our -u-boot.dtsi.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:40:27 +02:00
Michael Walle
7c9bd92eea board: lsxl: convert to DM_GPIO
Use the new mvebu GPIO driver and convert all the function calls to the
former kirkwood GPIO driver. This means that we are now using the LED
uclass and the regulator uclass. Unfortunately, the GPIO LED doesn't
offer a blinking method. Thus we are now stuck with solid on and off
states, which makes debugging a bit harder. Also, there is no GPIO fan
driver for now.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:40:06 +02:00
Michael Walle
aa088beac3 board: lsxl: make last resort recovery more reliable
If something is wrong with the environment, we cannot rely on a proper
u-boot operation anymore. In fact, it is possible, that we never reach
misc_init_r() with a broken environment.

Also don't enable the netconsole by environment settings. This way the
user don't have to reconfigure the environment. Instead the network
console is only enabled when the push button is pressed during boot.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:40:00 +02:00
Michael Walle
7717c2faf8 board: lsxl: automatically select CONFIG_MISC_INIT_R
The board code needs this to be set. Otherwise, the recovery mechanism
doesn't work. Therefore, select this option automatically with the
board.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:39:36 +02:00
Michael Walle
78c9b85df8 arm: kirkwood: make it CONFIG_TIMER aware
If we switch to CONFIG_TIMER, we don't need the legacy timer macros and
functions anymore. Add the proper guards to exclude them from compiling.

Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:38:54 +02:00
Pali Rohár
f395cf9cac arm: kirkwood: 88f6281: Detect CONFIG_SYS_TCLK from SAR register
Bit 21 in SAR register specifies if TCLK is running at 166 MHz or 200 MHz.
This information is undocumented in public Marvell Kirkwood Functional
Specifications [2], but is available in Linux v3.15 kirkwood code [1].

Commit 8ac303d49f ("arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK")
broke support for Marvell 88F6281 SoCs because it was expected that all
those SoCs have TCLK running at 200 MHz as specified in Marvell 88F6281
Hardware Specifications [3].

Fix broken support for 88F6281 by detecting CONFIG_SYS_TCLK from SAR
register, like it was doing Linux v3.15.

[1] - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/arm/mach-kirkwood/common.c?h=v3.15#n542
[2] - https://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
[3] - https://web.archive.org/web/20120620073511/http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf

Update by Stefan 2022-08-23:
- Fix compilation error for ds109

Fixes: 8ac303d49f ("arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:38:47 +02:00
Pali Rohár
5692e5b244 arm: mvebu: mbus: Fix mbus driver to work also after U-Boot relocation
mbus driver is initialized from arch_cpu_init() callback which is called
before relocation. This driver stores lot of functions and structure
pointers into global variables, so it is data position dependent.

Therefore after relocations all pointers are invalid and driver does not
work anymore as all pointers referes to the old memory, which overlaps with
CONFIG_SYS_LOAD_ADDR and ${loadaddr}.

For example U-Boot fuse command crashes if loadaddr memory is cleared or
rewritten by some image loaded by U-Boot load command.

  mw.w ${loadaddr} 0x0 10000
  fuse read 0 1 2

Fix this issue by removing of all mbus global variables in which are stored
pointers to structures or functions which changes during relocation. And
replace it by direct function calls (not via pointers). With this change
fuse command finally works.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 12:35:37 +02:00
Pali Rohár
397626ced6 arm: mvebu: Define env_sf_get_env_addr() for all Armada boards in SPL
SPI0 CS0 Flash is mapped to address range 0xD4000000 - 0xD7FFFFFF by BootROM.
Proper U-Boot removes this direct mapping. So it is available only in SPL.
This applies for all 32-bit Armada BootROMs. SPL mvebu code is used only on
32-bit Armada SoCs. So move env_sf_get_env_addr() function from Turris
Omnia board to common SPL mvebu code and add proper checks for SPI0 CS0.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-23 10:48:59 +02:00
Tom Rini
c50ff4a933 arm: Remove warp board
This board is missing migration to CONFIG_DM, which had a deadline of
v2020.01, which is now more than 2 years passed due.  Remove it.

Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-20 22:45:00 -04:00
Tom Rini
cd9b71c3f6 layerscape: Disable CONFIG_FMAN_ENET on *aqds* platforms
The *aqds* platforms have not been migrated to be able to enable
CONFIG_DM_ETH with CONFIG_FMAN_ENET. Disable CONFIG_FMAN_ENET on these
platforms.

Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Pramod Kumar <pramod.kumar_1@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-20 21:18:15 -04:00
Tom Rini
9d7add8ac9 net: lpc32xx_eth.c ethernet driver
This driver has not been converted to DM_ETH.  The migration
deadline passed 2 years ago.

Cc: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
2022-08-20 21:18:15 -04:00
Tom Rini
40463b9c4a arm: Remove kzm9g board
This board is behind on several mandatory DM migrations and is missing
OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Cc: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-20 21:18:15 -04:00
Tom Rini
0fb054b3f7 arm: Remove armadillo-800eva board
This board is behind on several mandatory DM migrations and is missing
OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-20 21:18:15 -04:00
Tom Rini
d8d5ab40d5 arm: Remove cm_t335 board
This board is behind on several mandatory DM migrations and is missing
OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-20 21:18:15 -04:00
Tom Rini
5663b137e6 arm: Remove edminiv2 board
This board is not converted to use CONFIG_DM, well passed the migration
deadline.  Remove it.

Cc: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-08-20 21:18:15 -04:00
Rasmus Villemoes
4b05301979 arm64: explicitly disable pointer authentication instructions
The Yocto project builds their aarch64 cross-compiler with the
configure knob --enable-standard-branch-protection, which means that
their gcc behaves as if -mbranch-protection=standard is passed; the
default (lacking that configure knob) is -mbranch-protection=none.

This means that when building U-Boot using the Yocto toolchain, most
functions end up containing paciasp/autiasp/bti instructions. However,
since U-Boot is not an ordinary userspace application, there's no OS
kernel which has set up the required authentication keys, so these
instructions do nothing at all (even on arm64 hardware that does have
the pointer authentication capability). They do however make the image
larger.

It is theoretically possible for U-Boot to make use of the pointer
authentication protection - cf. the linux kernel's
CONFIG_ARM64_PTR_AUTH_KERNEL - but it is far from trivial, and it's
hard to see just what threat model it would protect against in a
bootloader context. Regardless, we certainly have none of the required
infrastructure now, so explicitly pass -mbranch-protection=none to
ensure those useless instructions do not get emitted.

For a toolchain not configured with
--enable-standard-branch-protection, this changes nothing. For the
Yocto toolchain, this reduces the size of both SPL and U-Boot proper
by about 3% for my imx8mp target.

If you don't have a Yocto toolchain, the effect can easily be
reproduced by applying this patch and changing =none to =standard.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-08-20 18:12:37 -04:00
Matwey V. Kornilov
297c439b37 Restore pcm051_rev3_defconfig config
pcm051_rev3_defconfig config (Phytec Wega board) has been dropped in

    64efd11d ("arm: Remove pcm051 board")

due to expired migration deadlines. Here, pcm051_rev3_defconfig support is
reintroduced.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-08-20 16:40:14 -04:00
Pali Rohár
9ca6c91732 Nokia RX-51: Move board required options from defconfig to Kconfig
Some of config options are board specific and should be set in into their
default values automatically. So move them from defconfig file to Kconfig
definitions to ensure that possible user custom defconfig files would have
these required options also enabled.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-08-20 16:18:40 -04:00
Pali Rohár
c5be5f6f54 Nokia RX-51: Use U-Boot generic position independent code
Switch from custom board specific fixup/copy code to U-Boot generic
position independent code provided by config option POSITION_INDEPENDENT.

This also slightly decrease size of u-boot.bin binary (by 52 bytes). Note
that option POSITION_INDEPENDENT increase size but not more than custom
board fixup/copy code which is being deleted (as it is not needed anymore).

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-08-20 16:17:50 -04:00
Pali Rohár
012d4be439 arm: Set default MACH_TYPE in Kconfig
For boards which requires correct MACH_TYPE, set their correct default
values directly in Kconfig.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-08-20 16:17:50 -04:00
Gaurav Jain
47465877a5 ls1021atwr: caam: Enable Uboot validaion in SPL.
caam driver model enabled in spl for secure boot.
fsl_rsa_mod_exp driver enabled in spl for validating uboot image.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-08-16 17:07:30 +08:00
Tom Rini
08f80184a9 arm: Remove snapper9260 board
This board is behind on several mandatory DM migrations and is missing
OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-08-12 16:10:50 -04:00
Tom Rini
ff4e87c030 Convert CONFIG_SYS_FSL_QMAN_V3 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_NGPIXIS
   CONFIG_SYS_FSL_QMAN_V3
   CONFIG_SYS_FSL_RAID_ENGINE
   CONFIG_SYS_FSL_RMU
   CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
   CONFIG_SYS_FSL_SRIO_LIODN
   CONFIG_SYS_FSL_TBCLK_DIV
   CONFIG_SYS_FSL_USB1_PHY_ENABLE
   CONFIG_SYS_FSL_USB2_PHY_ENABLE
   CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
   CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
1de46d91dd Convert CONFIG_SYS_FSL_NUM_CC_PLLS to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_NUM_CC_PLLS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
c6eec0182a Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_MAX_NUM_OF_SEC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
8b549c0b23 Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al
This removes the following symbols:
   CONFIG_SYS_FSL_DSPI_BE
   CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
   CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
   CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
   CONFIG_SYS_FSL_DSP_DDR_ADDR
   CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
   CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
   CONFIG_SYS_FSL_ERRATUM_A008751
   CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
   CONFIG_SYS_FSL_ESDHC_NUM
   CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
   CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
   CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
   CONFIG_SYS_FSL_ISBC_VER
   CONFIG_SYS_FSL_QSPI_LE
   CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
   CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
   CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
   CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
   CONFIG_SYS_FSL_SRDS_NUM_PLLS
   CONFIG_SYS_FSL_WDOG_BE
   CONFIG_SYS_GP1DIR
   CONFIG_SYS_GP1ODR
   CONFIG_SYS_GP2DIR
   CONFIG_SYS_GP2ODR
   CONFIG_SYS_HALT_BEFOR_RAM_JUMP
   CONFIG_SYS_HMI_BASE
   FSL_QSPI_FLASH_NUM
   FSL_QSPI_FLASH_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Tom Rini
d0748898d8 Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
   CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS

And we remove the entries from the README for a number of already
converted items.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Simon Glass
4e4bf9449b common: Drop display_options.h from common header
Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-08-10 13:46:55 -04:00
Tom Rini
3dd4e91632 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu/turris_omina: Misc fixes and improvements (Pali & Marek)
- mvebu: spl: Always fallback to BootROM boot method (Pali)
- mvebu: Cleanup u-boot,dm-pre-reloc code (Pali)
- gpio: Remove mvgpio driver (Chris)
- SBx81LIFKW/SBx81LIFXCAT disable KIRKWOOD_GPIO (Chris)
- misc: atsha204a: Don't check for error when waking up the device (Pali)
2022-08-09 08:16:14 -04:00
Tom Rini
af7d151b8e - fixup error on efuse commands return
- add documentation on boot flow
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Merge tag 'u-boot-amlogic-20220809' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- fixup error on efuse commands return
- add documentation on boot flow
2022-08-09 08:14:09 -04:00
Chris Packham
d1471948f3 ARM: kirkwood: SBx81LIFKW: remove direct access of GPIO registers
Replace code that accessed the GPIO registers directly with code that
makes use of the LED_GPIO driver.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Pali Rohár
c8ef618ae1 arm: mvebu: armada-38x-controlcenterdc.dts: Move u-boot, dm-pre-reloc to -u-boot.dtsi
Move U-Boot specific device tree property u-boot,dm-pre-reloc into U-Boot
specific device tree include file armada-38x-controlcenterdc-u-boot.dtsi.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Pali Rohár
e49a55af8b arm: mvebu: armada-xp-theadorable.dts: Move u-boot, dm-pre-reloc to -u-boot.dtsi
Move U-Boot specific device tree property u-boot,dm-pre-reloc into U-Boot
specific device tree include file armada-xp-theadorable-u-boot.dtsi.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Pali Rohár
5d4d1212f7 arm: mvebu: Remove redundant u-boot, dm-pre-reloc from all 32-bit Armada SoCs
Replace it by including of mvebu-u-boot.dtsi file. When board does not use
-u-boot.dtsi then mvebu-u-boot.dtsi is included automatically by makefile
scripts/Makefile.lib.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:27 +02:00
Pali Rohár
8879258ec0 arm: mvebu: Introduce mvebu-u-boot.dtsi for 32-bit Armada SoCs
Set u-boot,dm-pre-reloc for /soc/, /soc/internal-regs/ and &uart0 nodes as
it is required on every 32-bit Armada SoCs. And set also u-boot,dm-pre-reloc
for &spi0 when going to boot from SPI because otherwise SPL SPI drivers do
not load.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:26 +02:00
Pali Rohár
0e8b74addc arm: mvebu: dts: Build only arch-compatible dts files
64-bit Armada DTS files are not build correctly during compilation of
32-bit Armada boards and vice versa. So fix makefile build system to
compile only those dts files which are compatible for the current build
(64-bit Armada DTS files only for 64-bit builds and 32-bit Armada DTS files
only for 32-bit builds).

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:58:26 +02:00
Pali Rohár
dfebc1b908 arm: mvebu: spl: Always fallback to BootROM boot method
BootROM boot method should always work so always add it as fallback method
to spl_boot_list. In case U-Boot SPI driver fails it is better to try using
BootROM than hanging as by default only one boot method is specified.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-08-09 08:57:23 +02:00
Kunihiko Hayashi
dd8c3136aa ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins
UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays
of RGMII interface using pull-ups on the RXDLY and TXDLY pins.

So should set the phy-mode to "rgmii-id" to show that RX/TX delays are
enabled.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Ramon  Fried <rfried.dev@gmail.com>
2022-08-08 11:37:57 -04:00
Jerome Brunet
3145e0d0ff ARM: meson: fixup error on efuse commands return
All `sm efuseread/efusewrite` commands exit with an error, even if the fuse
have actually been dealt with correctly.

This is because the smc call return the size it actually processed but this
result is checked against 0.

Return failure in do_efuse_read/write if the return value of
meson_sm_read/write_efuse() is not the requested size.

Fixes: 52195ba5f5 ("ARM: amlogic: add sm efuse write support and cmd for read/write efuse")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220804144138.33809-1-jbrunet@baylibre.com
2022-08-08 09:56:38 +02:00
Tom Rini
7da6a9e7df Convert CONFIG_SYS_FSL_CORES_PER_CLUSTER to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_CORES_PER_CLUSTER

As part of this, correct the dependencies on SYS_FSL_THREADS_PER_CORE.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Tom Rini
612f7a61d5 Convert CONFIG_FSL_MEMAC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_MEMAC
   CONFIG_SYS_MEMAC_LITTLE_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Tom Rini
923a855509 Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_CCSR_GUR_BE
   CONFIG_SYS_FSL_CCSR_SCFG_BE
   CONFIG_SYS_FSL_ESDHC_BE
   CONFIG_SYS_FSL_IFC_BE
   CONFIG_SYS_FSL_PEX_LUT_BE
   CONFIG_SYS_FSL_CCSR_GUR_LE
   CONFIG_SYS_FSL_CCSR_SCFG_LE
   CONFIG_SYS_FSL_ESDHC_LE
   CONFIG_SYS_FSL_IFC_LE
   CONFIG_SYS_FSL_PEX_LUT_LE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Tom Rini
2d752b0d4a Convert CONFIG_SYS_FMAN_V3 to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FMAN_V3

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:47 -04:00
Andrew Davis
b661c1bc92 arm: mach-k3: security: Remove certificate if detected on GP device
If the device is a GP and we detect a signing certificate then remove it.
It would fail to authenticate otherwise as the device is GP and has no
secure authentication services in SYSFW.

This shouldn't happen often as trying to boot signed images on GP devices
doesn't make much sense, but if we run into a signed image we should at
least try to ignore the certificate and boot the image anyway. This could
help with users of GP devices who only have HS images available.

If this does happen, print a nice big warning.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
a0379c6fe3 arm: mach-k3: security: Bypass image signing at runtime for GP devices
We can skip the image authentication check at runtime if the device is GP.
This reduces the delta between GP and HS U-Boot builds. End goal is
to re-unify the two build types into one build that can run on all
device types.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
e1ef04fb3e arm: mach-k3: security: Allow signing bypass if type is HS-FS
On HS-FS devices signing boot images is optional. To ease use
we check if we are HS-FS and if no certificate is attached
to the image we skip the authentication step with a warning
that this will fail when the device is set to security enforcing.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
d1c079557f arm: mach-k3: Add support for device type detection
K3 SoCs are available in a number of device types such as
GP, HS-FS, EMU, etc. Like OMAP SoCs we can detect this at runtime
and should print this out as part of the SoC information line.
We add this as part of the common.c file as it will be used
to also modify our security state early in the device boot.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-08-04 15:32:20 -04:00
Quentin Schulz
2c9cf3b644 mx7ulp_com: fix incorrect select for SPL options
SPL_GPIO_SUPPORT is named SPL_GPIO since commit 83061dbd1c ("Rename
GPIO_SUPPORT to GPIO"), SPL_MMC_SUPPORT is named SPL_MMC since commit
103c5f1806 ("mmc: Rename MMC_SUPPORT to MMC"), SPL_SERIAL_SUPPORT is
named SPL_SERIAL since commit 2a73606668 ("serial: Rename
SERIAL_SUPPORT to SERIAL") so let's select the correct Kconfig options.

Fixes: 8b71576f38 ("mx7ulp_com: add support for SPL")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2022-08-04 15:32:20 -04:00
Jim Liu
88513fe584 ARM: dts: npcm7xx: add npcm750 full function node
add npcm750 BMC full function node

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-08-04 15:32:20 -04:00
Marek Behún
b2d7619e46 arm: mvebu: turris_omnia: Fix mpp26 pin name and comment
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
which is routed to CN11 pin header, is documented as SPI CS1, but
MPP[26] pin does not support this function. Instead it controls chip
select 2 if in "spi0" mode.

Fix the name of the pin node in pinctrl node and fix the comment in SPI
node.

Signed-off-by: Marek Behún <kabel@kernel.org>
2022-07-29 13:55:52 +02:00
Pali Rohár
162311637d arm: mvebu: Synchronize armada-385-turris-omnia with Linux v5.20
* Add SPDX-License-Identifier
* Add SFP and LED nodes
* Fix PHY nad NOR nodes
* Remove duplicates from u-boot.dtsi file

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 13:55:52 +02:00
Pali Rohár
48223161b5 arm: mvebu: Synchronize armada-385.dtsi with Linux v5.20
* Define PCIe interrupts

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 13:55:52 +02:00
Pali Rohár
30bbb02a5c arm: mvebu: Synchronize armada-38x.dtsi with Linux v5.20
* Replace skeleton.dtsi by explicit #address-cells / #size-cells
* Add sdramc@1400 and phy@18300 nodes
* Remove (unused) timeout-ms i2c properties
* Fix compatible string for UARTs
* Add interrupts properties for watchdog

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 13:55:52 +02:00
Pali Rohár
204b8707cd arm: mvebu: Fix compatible string for nand controller
Linux kernel uses compatible string "marvell,armada370-nand-controller" for
nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of
"marvell,armada370-nand" and "marvell,mvebu-pxa3xx-nand".

So unify it and use just Linux kernel compatible string.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 13:55:35 +02:00
Pali Rohár
8327389748 arm: mvebu: turris_omnia: Add mcu node with gpio-controller
This allows U-Boot to register new Turris Omnia MCU driver.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-29 10:02:43 +02:00
Pali Rohár
319b62880c arm: mvebu: Add gpio-ranges into Armada 38x device tree file
This allows U-Boot mvebu-gpio.c driver to switch particular MPP pin into
GPIO mode and enable GPIO support.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-28 08:41:45 +02:00
Andre Przywara
81e712a917 ARM: relocate: Fix Thumb code by using proper label type
The generic ARM relocate_code function was using its own function entry
point as a relocation base, and it was obtaining that address by using
the "adr" instruction on that entry point label.
However that label is not just an ordinary label, instead we explicitly
mark it as a function start address. Normally that doesn't change much
(other than for debugging), but when assembled in Thumb mode, newer
versions of the GNU assembler prepare everything for this address being
used as the argument to a "bx" call, so make sure bit 0 is set in there
to mark this function as Thumb code. Of course this doesn't end up very
well when we use this address for the ensuing memcpy operation.

To avoid this problem, and to solve it in a robust way, add an extra
label, which is not marked as a function entry, and use that for the adr
instruction. This lets all assemblers generate the right immediate offset
in the "adr" instruction.

This fixes in particular ARMv7-M ports when using GNU binutils v2.37 or
newer (commit d3e52e120b68 seems to trigger the change in behaviour).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Jesse Taube <mr.bossman075@gmail.com>
2022-07-26 17:53:43 -04:00
Tom Rini
86feeab3dc u-boot-imx-20220726
-------------------
 
 i.MX for 2022.10
 
 - Added i.MX93 architecture
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12891
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Merge tag 'u-boot-imx-20220726' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220726
-------------------

i.MX for 2022.10

- Added i.MX93 architecture

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12891
2022-07-26 10:26:00 -04:00
Peng Fan
e29303993b imx: imx8mm-icore: migrate to use BINMAN
Use BINMAN instead of imx specific packing method.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-07-26 11:29:02 +02:00
Peng Fan
c065a6c6f6 arm: dts: imx8m: shrink ddr firmware size to actual file size
After we switch to use BINMAN_SYMBOLS, there is no need to pad
the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.

Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-07-26 11:29:02 +02:00
Peng Fan
25daa2cdda arm: dts: imx8m: update binman ddr firmware node name
We are migrating to use binman symbols, the current names are
inconsistent across different boards, so unify them.

Also add `type = "blob-ext";`, since the new names are not valid binman
types.

Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
[Alper: Edit commit message]
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-07-26 11:29:02 +02:00
Peng Fan
481f96068e board: freescale: imx93_evk: support ethernet
Add ethernet support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
feaf8e0cf0 imx: imx93_evk: Set ARM clock to 1.7Ghz
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
86a179703c imx: imx93_evk: Add basic board support
Add basic board codes and defconfig for i.MX93 11x11 EVK board.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
0da3d96e10 arm: dts: Add i.MX93 SoC DTSi file
Add the DTSi file and DT header files for i.MX93 SoC

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
99c7cc58e1 ddr: imx: Add i.MX9 DDR controller driver
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.

The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
e631185a20 imx: imx9: clock: Add DDR clock support
Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
87650716ea imx: imx9: Support multiple env storages at runtime
Select env storages according to boot device at runtime

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
c383379f25 imx: imx9: Support booting m33 from Acore
Add bootaux command to support on-demand booting M33 from u-boot.
It kicks M33 via ATF by "bootaux 0x201e0000 0"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
a8753afed7 imx: imx9: Add M33 release prepare function
To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.

The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
0256577a83 imx: imx9: Add MIX power init
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.

SPL should call the power init in its boot sequence before accessing
above three MIX and USB.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
12f2322736 imx: imx9: Add gpio registers structure
Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Alice Guo
31b3ca5527 misc: fuse: support to access fuse on i.MX93
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
1a55a633e0 misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
Use more generic name for S40x msg structure

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Peng Fan
989f73934d imx: imx9: Get the chip revision through S400 API
Update the get chip revision methond to use S400 API, also record
other information like lifecycle and UID to global data.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
fd94c2367b imx: imx9: Add AHAB boot support
Add AHAB driver for iMX9 to do authentication by calling sentinel API

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
5fda95fb94 imx: imx9: Add TRDC driver for TRDC init
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
   permission to the memory where SPL image runs. Sentinel will set
   the memory to RX only after ROM authentication for the OEM
   closed part.
2. Init phase will configure TRDC to allow non-secure master to
   access DDR. So the peripherals can work in u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
2727245638 misc: s400_api: introduce ahab_release_m33_trout
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
625473d6ce misc: S400_API: New API for FW status and chip info
Add new API to get sentinel FW status and SoC chip info

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
e5fcf91348 misc: S400_API: Update release RDC API
To support more RDC instances on i.MX93, update API to latest
definition.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
45fed324b5 misc: s4mu: Support iMX93 with Sentinel MU
Support iMX93 communicate with Sentinel

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
03fcf96651 misc: imx: S400_API: Move S400 MU and API to a common place
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
636c95f82b imx: imx9: support romapi
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.

Also include mmc env functions that use ROM API.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
2c5f5457bc imx: imx9: disable watchdog
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Jian Li
53cf550d23 imx: imx9: Add function to initialize timer
Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.

Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
f79c162668 imx: imx9: Add CCM and clock API support
Add clock API to support CCM root clock and LPCG setting
Set the CCM AUTHEN register to allow non-secure world to set
root clock and lpcg.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
07110c6f53 imx: pinctrl: add pinctrl and pinfunc file for i.MX93
Add the pinctrl driver and pinfunc header file to support iMX93

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
881df6ed84 imx: add basic i.MX9 support
Add i.MX9 Kconfig and basic files for the new SoC

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
787f04bb6a imx: add USB2_BOOT type
Add USB2_BOOT type for i.MX8ULP and i.MX9

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
b0a284a7c9 imx: move get_boot_device to common file
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device
implementation, so move to a common file. And when support i.MX9,
no need to include the other function copy.

Since sys_proto.h is included in imx_romapi.c, there will be build
warning for i.MX8M because wdog_regs not defined, so include imx-regs.h
in i.MX8M sys_proro.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
1859b8b60d imx: move get_boot_device to common header
Most i.MX implements get_boot_device, move it to common header to
simplify code

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
793b760fb0 imx: simplify dependency with SPL_BOOTROM_SUPPORT
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.

And drop the guard with structure definition, there is no need.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
bf43907f6e imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
Move the default mapping of spl_boot_device to weak function of
spl_board_boot_device. So that every board of iMX7/8/8M can overwrite
this function to implement specific mapping.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Ye Li
9270cc8f3b imx: Change USB boot device type
The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from
USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Peng Fan
2f5ee7f812 arm: makefile: cleanup mach-imx usage
All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so
the macro could be the gate to build arch/arm/mach-imx to simplify
the rules.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Jun Nie
651478777b imx: syscounter: support timer_get_boot_us
With supporting timer_get_boot_us, we can profile boot up time with below
configs and function bootstage_mark_name().

CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_BOOTSTAGE=y

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-07-26 11:28:43 +02:00
Oleksandr Suvorov
d7fcbfc19b fpga: xilinx: add bitstream flags to driver desc
Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-07-26 09:34:21 +02:00
Ashok Reddy Soma
cce3351501 mailbox: zynqmp: Move struct zynqmp_ipi_msg from sys_proto.h
Mailbox driver might be need for Versal and other future platforms.
To remove the dependency, move struct zynqmp_ipi_msg to
zynqmp_firmware.h so that mailbox driver compiles for other platforms
easily.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-5-ashok.reddy.soma@xilinx.com
2022-07-26 08:36:20 +02:00
Ashok Reddy Soma
65168910ad zynqmp: Run board_get_usable_ram_top() only on main U-Boot
With commit ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory
location"), the function board_get_usable_ram_top() is allocating
MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this
much memory in case of mini U-Boot.

Keep these functions which use lmb under CONFIG_LMB so that they are
compiled and used only when LMB is enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
2022-07-26 08:23:54 +02:00
Michal Simek
b09e462482 arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED
CONFIG_OF_LIBFDT is used twice for guarding the same code. It is enough to
do it once that's why remove additional ifdefs from arm and risc-v code.

Fixes: 0c303f9a66 ("image: Drop IMAGE_ENABLE_OF_LIBFDT")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/f8e3ff9124195cbd957874de9a65ef79760ef5e7.1657183634.git.michal.simek@amd.com
2022-07-26 08:23:54 +02:00
Michal Simek
156cb2af92 arm64: zynqmp: Used fixed-partitions for QSPI in k26
Using fixed partitions is recommended way how to describe QSPI. Also add
label for qspi flash memory to be able to reference it in future.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a84f7ce8d6472fce66539ba29d31fbaae511d94b.1655732762.git.michal.simek@amd.com
2022-07-26 08:23:54 +02:00
Ayan Kumar Halder
41d7f67448 xilinx: Remove the legacy property "#stream-id-cells"
"#stream-id-cells" was being used with "mmu-masters" for Xen specific
device trees.
With Xen commit 2278d2cbb0b7c1b48b298c6c4c6a7de2271ac928 (Link below)
Xen is able to support smmu bindings in both formats ie :
1. Using iommus (linux format)
2. Using mmu-masters (legacy format).

Thus, "#stream-id-cells" which was used for the legacy format, can be
removed as Xen can use smmu bindings in linux format.

Link: https://www.mail-archive.com/xen-devel@lists.xenproject.org/msg101649.html
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1e062acb233dee47cd7dd2429cb482132617cbc8.1655886415.git.michal.simek@amd.com
2022-07-26 08:23:54 +02:00
Tom Rini
032c9b045c arm: Remove unused references to CONFIG_SOC_DM*
There are no references to CONFIG_SOC_DM355 / CONFIG_SOC_DM365 /
CONFIG_SOC_DM644X / CONFIG_SOC_DM646X and the files these Makefile lines
reference have already been dropped.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-25 14:57:27 -04:00
Andrew Davis
a9ec2f6509 spl: Use SPL_TEXT_BASE instead of ISW_ENTRY_ADDR
The ISW_ENTRY_ADDR symbol was used for OMAP devices in place of
SPL_TEXT_BASE. Keystone2 HS devices were not using it right either.
Remove ISW_ENTRY_ADDR and use SPL_TEXT_BASE directly.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 14:57:27 -04:00
Andrew Davis
121596a98f arm: k3: config.mk: Read software revision information from file on HS
Read the swrv.txt file from the TI Security Development Tools when
TI_SECURE_DEVICE is enabled. This allows us to set our software
revision in one place and have it used by all the tools that create
TI x509 boot certificates.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-07-25 14:57:27 -04:00
Yogesh Siraswar
0019427251 k3_gen_x509_cert: Make SWRV configurable for anti-rollback protection
The x509 certificate SWRV is currently hard-coded to 0. This need to be
updated to 1 for j721e 1.1, j7200 and am64x. It is don't care for other
k3 devices.

Added new config K3_X509_SWRV to k3. Default is set to 1.

Signed-off-by: Yogesh Siraswar <yogeshs@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
2022-07-25 14:57:27 -04:00
Andrew Davis
080fe39b8c arm: mach-k3: Remove ROM firewalls on GP devices
This isn't strictly needed as these firewalls should all be disabled on
GP, but it also doesn't hurt, so do this unconditionally to remove this
use of CONFIG_TI_SECURE_DEVICE.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 14:57:27 -04:00
Andrew Davis
80b93bb71c arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654
The first AM6x device was the AM654x, but being the first we named it
just AM6, since more devices have come out with this same prefix we
should switch it to the normal convention of using the full name of the
first compatibility device the series. This makes what device we are
talking about more clear and matches all the K3 devices added since.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Andrew Davis
46da163b72 arm: mach-k3: Only build init files for SPL
The content of these files are only used in SPL builds. The contents are
already ifdef for the same, remove that and only include the whole file
in the build when building for SPL.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Stephan Gerhold
afc13335a5 arm: dts: db410c/db820c: Fix SPMI addresses
The Qualcomm device trees in U-Boot are currently not consistent with
the upstream DTs used in the Linux kernel. While some bindings are
similar to the official specification in the Linux kernel, several
nodes have subtle differences, e.g. the "compatible"s or the exact
specification of memory registers.

This means that some of the Qualcomm-related U-Boot drivers are not
compatible with the Linux DT (and vice versa).

The SPMI node is one such example: the "core" region starts at
0x0200f000 in the upstream Linux MSM8916 DT, but in U-Boot it starts at
0x0200f800. The end result is normally the same, since the Linux SPMI
driver simply adds the 0x800 internally.

However, commit f5a2d6b4b0 ("spmi: msm: add arbiter version 5
support") imported this behavior into the U-Boot driver, without
adjusting the DB410c/DB820c device trees. This means that the 0x800
offset is now added twice, breaking all SPMI read/write operations:

  Failed to find PMIC pon node. Check device tree
  Failed to find pm8916_gpios@c000 node.
  USB init failed: -6
  starting USB...
  Bus ehci@78d9000: Failed to find pm8916_gpios@c000 node.
  probe failed, error -6
  No working controllers found

While the mistake is strictly speaking in the spmi-msm driver, fix the
issue by making the SPMI nodes in the DB410c/DB820c consistent with the
upstream Linux DT instead.

Ideally we should even go a step further by fixing the remaining uses
of custom bindings in the U-Boot drivers and moving to using the Linux
DTs as-is. This would likely avoid such mistakes in the future and
would also make the porting process much easier.

Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Fixes: f5a2d6b4b0 ("spmi: msm: add arbiter version 5 support")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2022-07-25 13:02:04 -04:00
Matt Ranostay
cab8510821 armv8: mach-k3: correct define checking for AM625/AM642 memory maps
Using CONFIG_IS_ENABLED breaks accessing memory map structure when
doing a A53 SPL build for AM625 and AM642 platforms. This is due to
'abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y''
in which there is no CONFIG_SPL_SOC_K3_AM625/CONFIG_SPL_SOC_K3_AM642
defined in the configuration.

For the A53 SPL builds on these platform to access the memory mapping
which it will need for enabling the mmu/cache it must use #if defined(X)
checks and not CONFIG_IS_ENABLED.

Cc: Suman Anna <s-anna@ti.com>
Cc: Neha Francis <n-francis@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Weijie Gao
a3ba6adb70 arm: dts: mt7622: remove default pinctrl of uart0
Currently u-boot running on mt7622 will print an warning log at beginning:
> serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

It turns out that the pinctrl uclass can't work properly in board_f stage.

Since the uart0 is the default UART device used by bootrom, and will be
initialized in both bootrom and tf-a bl2. It's ok not to setup pinctrl for
uart0 in u-boot.

This patch removes the default pinctrl of uart0 to suppress the unwanted
warning.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-25 13:02:04 -04:00
Anand Gadiyar
997d7a2b4b arm: dts: k3-am64-ddr fix typo causing DDR4 register corruption
The entry for DDRSS_PI_321_DATA was accidentally repeated leading to the
last few PI registers being incorrectly programmed.

Fix this.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Sumit Garg
bf95d17809 board: qualcomm: Add support for QCS404 EVB
Add support for Qualcomm QCS404 SoC based evaluation board.

Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot

U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/qcs404.rst.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-07-25 13:02:04 -04:00
Sumit Garg
a4a9d9e874 clocks: qcom: Add clock driver for QCS404 SoC
Currently this clock driver initializes clocks for UART and eMMC. Along
with this import "qcom,gcc-qcs404.h" header from Linux mainline to
support DT bindings.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-07-25 13:02:04 -04:00
Sumit Garg
a8effc2ee4 pinctrl: qcom: Add pinctrl driver for QCS404 SoC
Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-07-25 13:02:04 -04:00
Sumit Garg
d35b211374 board: qualcomm: Add support for dragonboard845c
Add support for 96Boards Dragonboard 845C aka Robotics RB3 development
platform. This board complies with 96Boards Open Platform Specifications.

Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive

U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/sdm845.rst, board: dragonboard845c.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-07-25 13:02:04 -04:00
Sumit Garg
f5ed6c9ccf uart: sdm845: Fix debug UART pinmux
Configure debug UART pins as function: "qup9" rather than being regular
gpios. It fixes a hang seen during pinmux setting.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-07-25 13:02:04 -04:00
Sumit Garg
ffa7928719 clocks: sdm845: Import qcom,gcc-sdm845.h
Rather than using magic numbers as clock ids for peripherals import
qcom,gcc-sdm845.h from Linux to be used standard macros for clock ids.
So start using corresponding clk-id macro for debug UART.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-07-25 13:02:04 -04:00
Sumit Garg
866985b7e6 arm64: dts: sdm845: Remove redundant u-boot DT properties
According to u-boot DT recomendation, u-boot specific DT properties belong
to *-uboot.dtsi. Also for starqltechn board (which is the only current
consumer of sdm845.dtsi), the properties are already included in
starqltechn-uboot.dtsi, so remove corresponding redundant properties.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-07-25 13:02:03 -04:00
Sumit Garg
c551c8fe5f board: starqltechn: Align DT node overrides with sdm845.dtsi
Currently there is a mismatch among DT node overrides in starqltechn
board DTS file and the actual DT nodes in the sdm845.dtsi. So fix that
to align with DT nodes in sdm845.dtsi.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-07-25 13:02:03 -04:00
Marcel Ziswiler
24a7a3c1c0 imx8mm: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:01 +02:00
Marcel Ziswiler
181d1684ca imx8mq: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:01 +02:00
Marcel Ziswiler
e6ad8070a7 verdin-imx8mp: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device tree we are now using the
regular one for the Verdin Development (carrier) board (e.g.
imx8mp-verdin-wifi-dev.dtb rather than the previous imx8mp-verdin.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:01 +02:00
Marcel Ziswiler
84c5cd9b84 imx8mp-rsb3720-a1: fix pwms property warnings
Fix the following build-time pwms property warnings:

w+arch/arm/dts/imx8mp-rsb3720-a1.dtb: Warning (pwms_property):
 /lvds_backlight@0:pwms: property size (12) too small for cell size 3
w+arch/arm/dts/imx8mp-rsb3720-a1.dtb: Warning (pwms_property):
 /lvds_backlight@1:pwms: property size (12) too small for cell size 3

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:01 +02:00
Marcel Ziswiler
e0caa84ca6 imx8mp: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:01 +02:00
Marcel Ziswiler
4e5114daf9 imx8mn: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
a68bad0a37 imx8mm-mx8menlo/verdin-imx8mm: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device tree we are now using the
regular one for the Verdin Development (carrier) board (e.g.
imx8mm-verdin-wifi-dev.dtb rather than the previous imx8mm-verdin.dtb).

Please further note that the PMIC node name got changed from a pmic
label to pmic@25 which required adjustment in resp. board SPL file
board/toradex/verdin-imx8mm/spl.c.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
35c819ed4e imx8mm-kontron-n801x-s-lvds: fix pwms property warnings
Fix the following build-time pwms property warnings:

w+arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dtb: Warning (pwms_property):
 /backlight:pwms: property size (12) too small for cell size 3

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
b96a9683e5 imx8mm-venice-gw700x: prepare to synchronise device trees with linux
As a preparatory step remove the pinctrl_pmic reference which does not
exist in the Linux upistream device tree.

This avoids the following error once synchronised:

+Error: arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi:26.1-14 Label or
 path pinctrl_pmic not found

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
b4052d55ad colibri_vf: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device tree we are now using the
regular one for the Colibri Evaluation (carrier) board V3 (e.g.
vf610-colibri-eval-v3.dtb rather than the previous vf610-colibri.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
e8a9521e64 vf500/vf610: synchronise device trees with linux
Synchronise device trees with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
fed2e400ff ARM: DTS: bk4r1/pcm052: prepare to synchronise device trees with linux
As a preparatory step rename the included SoC dtsi from vf.dtsi to
vf610.dtsi as this is how it is named in Linux upstream.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
25ab97986c colibri-imx7d/-emmc: synchronise device tree with linux
Synchronise device tree with linux-next next-20220708.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device trees we are now using the
regular ones for the Colibri Evaluation (carrier) board V3 (e.g.
imx7d-colibri-eval-v3.dtb rather than the previous
imx7-colibri-rawnand.dtb and imx7d-colibri-emmc-eval-v3.dtb rather than
the previous imx7-colibri-emmc.dtb).

Please further note that the PMIC node name got changed from rn5t567@33
to pmic@33 which required adjustment in resp. board file
board/toradex/colibri_imx7/colibri_imx7.c.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
2f96d4dd95 imx7s/d: synchronise device trees with linux
Synchronise device tree with linux-next next-20220708.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
868b5cb74e imx: imx7d-sdb: prepare to synchronise device trees with linux
As a preparatory step remove the epdc reference which does not exist in
the Linux upstream device tree and rename the qspi1 reference to qspi as
this is how it is named in the Linux upstream device tree.

This avoids the following error once synchronised:

+Error: arch/arm/dts/.imx7d-sdb-qspi.dtb.pre.tmp:10.1-6 Label or path
 epdc not found
+Error: arch/arm/dts/.imx7d-sdb-qspi.dtb.pre.tmp:29.1-7 Label or path
 qspi1 not found
+Error: arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi:6.1-7 Label or path
 qspi1 not found

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
7b4a934d73 imx: imx7-cm: prepare to synchronise device trees with linux
As a preparatory step rename the qspi1 reference to qspi as this is how
it is named in the Linux upstream device tree.

This avoids the following error once synchronised:

+Error: arch/arm/dts/.imx7-cm.dtb.pre.tmp:96.1-7 Label or path qspi1 not
 found

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
c21b61bff1 colibri-imx6ull/-emmc: synchronise device tree with linux
Synchronise device tree with linux v5.19-rc5.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device trees we are now using the
regular ones for the Colibri Evaluation (carrier) board V3 (e.g.
imx6ull-colibri-eval-v3.dtb rather than the previous imx6ull-colibri.dtb
and imx6ull-colibri-emmc-eval-v3.dtb rather than the previous
imx6ull-colibri-emmc.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
5d7a95f499 imx6ul/imx6ull: synchronise device trees with linux
Synchronise device trees with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
091a03f8f3 imx: mx6ul_14x14_evk: prepare to synchronise device trees with linux
As a preparatory step remove the qspi node with its flash0 label as this
is already in the Linux upstream device tree.

This avoids the following error once synchronised:

+arch/arm/dts/imx6ul-14x14-evk.dtb: ERROR (duplicate_label):
 /soc/bus@2100000/spi@21e0000/n25q256a@0: Duplicate label 'flash0' on
 /soc/bus@2100000/spi@21e0000/n25q256a@0 and
 /soc/bus@2100000/spi@21e0000/flash@0

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
bd483b7a9f colibri_imx6: synchronise device tree with linux
Synchronise device tree with linux-next next-20220708.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device tree we are now using the
regular one for the Colibri Evaluation (carrier) board V3 (e.g.
imx6dl-colibri-eval-v3.dtb rather than the previous imx6-colibri.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
50ba171e2d apalis_imx6: synchronise device tree with linux
Synchronise device tree with linux-next 20220706.

Please note that this also means that instead of the previous "generic"
U-Boot specific carrier board agnostic device tree we are now using the
regular one for the Apalis Evaluation (carrier) board (e.g.
imx6q-apalis-eval.dtb rather than the previous imx6-apalis.dtb).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
d0399a46e7 imx6dl/imx6qdl: synchronise device trees with linux
Synchronise device trees with linux-next next-20220708.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
50b229523b tbs2910: prepare to synchronise device trees with linux
As a preparatory step make sure to refer to absolute node paths where
labels were removed in Linux upstream.

This avoids the following error once synchronised:

+Error: arch/arm/dts/imx6q-tbs2910-u-boot.dtsi:3.1-7 Label or path aips1
 not found
+Error: arch/arm/dts/imx6q-tbs2910-u-boot.dtsi:11.1-5 Label or path soc
 not found

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
6f7db3a968 imx6: aristainetos: fix pwms property warnings
Fix the following build-time pwms property warnings:

w+arch/arm/dts/imx6dl-aristainetos2c_7.dtb: Warning (pwms_property):
 /backlight:pwms: property size (12) too small for cell size 3
w+arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dtb: Warning (pwms_property):
 /backlight:pwms: property size (12) too small for cell size 3

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-07-25 16:12:00 +02:00
Marcel Ziswiler
398ae1dca1 board/BuR/brppt2: fix pwms property warning
Fix the following build-time pwms property warning:

w+arch/arm/dts/imx6dl-brppt2.dtb: Warning (pwms_property):
 /backlight:pwms: property size (12) too small for cell size 3

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-25 16:12:00 +02:00
Fabio Estevam
05996f350d imx8mm: Sync device tree with linux-next 20220711
Sync imx8mm.dtsi device tree with linux-next 20220711.

The main motivation for doing this sync is the sha256 regression
reported by Andrey Zhizhikin [1].

The linux-next kernel has the following commit, which disables
the job ring 0 and fixes the problem:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20220715&id=dc9c1ceb555ff661e6fc1081434600771f29657c

[1] https://lore.kernel.org/u-boot/AM6PR06MB46912207D9460CD9924F35DAA68B9@AM6PR06MB4691.eurprd06.prod.outlook.com/T/#t

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-07-25 16:12:00 +02:00
Julien Panis
169582025a arm64: mach-k3: am625_init: Probe ESM nodes
On AM62x devices, main ESM error event outputs can be routed to
MCU ESM as inputs. So, two ESM device nodes are expected in the
device tree : one for main ESM and another one for MCU ESM.
MCU ESM error output can trigger the reset logic to reset
the device when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is
set to '0'.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2022-07-25 09:38:47 -04:00
Julien Panis
3128c890f2 arm64: dts: k3-am625-r5: Add support for ESM devices
Add main ESM and MCU ESM nodes to AM625-R5 device tree.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2022-07-25 09:38:47 -04:00
Janne Grunau
e53237aa53 arm: apple: Add initial Apple M2 support
Apple's M2 SoC very similar to the M1 and can use the same memory map.
The keyboard/trackpad on the MacBook Pro (13-inch, M2, 2022) uses
"dockchannel" as transport instead of SPI and needs a new driver.
USB, NVMe, uart, framebuffer and watchdog are working with the existing
drivers.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2022-07-25 09:38:47 -04:00
Mamta Shukla
1c3a8e7753 configs: imx8mm: Define CONFIG_SYS_UBOOT_BASE for i.MX8m
The macro `CONFIG_SYS_UBOOT_BASE` is used by SPL loaders `"NOR"` and
`"XIP"` to determine the base address of u-boot.

For `"NOR"` on i.MX8MM it is the base address of QSPI0 plus the offset
of the flattened image tree blob.
Although `QSPI0_AMBA_BASE` is used to define CONFIG_SYS_UBOOT_BASE in
multiple board header files for i.MX8MM, it is not specified.

Specify offset of flattened image tree blob (needs to be set to same
value as specified in 'binman' node), base address of QSPI0 and size of
FlexSPI configuration block.

Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com>
Signed-off-by: Thomas Haemmerle <thomas.haemmerle@leica-geosystems.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrey Zhizhikin  <andrey.zhizhikin@leica-geosystems.com>
2022-07-25 15:35:35 +02:00
Mamta Shukla
de99721c35 dts: imx8mm-uboot: Add support to pack FlexSPI Header using binman
Add definition for FSPI configuration block and subsequently new offsets for
u-boot-spl and u-boot-itb for CONFIG_FSPI_HEADER option.

Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com>
Signed-off-by: Thomas Haemmerle <thomas.haemmerle@leica-geosystems.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
5809d764a9 imx8ulp: soc.c: use rom_api_query_boot_infor() wrapper
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
f963622f28 imx8m: soc.c: use rom_api_query_boot_infor() wrapper
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
f8001fdd2c imx8: use ROM API wrappers in spl_imx_romapi.c
Simplify the use of the ROM API by using the wrappers that take care
of saving/restoring gd and computing the xor value. This makes the
generated code smaller and the C code easier to read.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
748da8abb0 imx8: add rom api wrappers
The ROM API is thoroughly undocumented, but apparently passing the xor
of the real arguments as an extra argument is required [1]. Also, we
need to do the "save gd/restore gd" dance. These are both error-prone,
and lead to a lot of code duplication.

Since both imx8m[np] and imx8ulp SOCs have this, add a separate
translation unit which is included precisely when the new
CONFIG_IMX8_ROMAPI symbol is set, which provide convenience wrappers
that take care of computing the xor value as well as doing the gd
dance, and that thus have a more intuitive API. Subsequent patches
will make use of these to reduce boilerplate.

[1] One wonders, for example, if the check is only applied to the
lower 32 bits, or if we're implicitly relying on all 64-bit pointer
values we're passing effectively have 0 in the upper 32 bits.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
de20c5d405 imx8: sys_proto.h: change guard logic around ROM API
This exposes the struct rom_api, the g_rom_api variable declaration
and the associated #defines to slightly fewer boards: namely, those
IMX8M which are not IMX8MN or IMX8MP. But the latter two are the only
IMX8M* ones where the g_rom_api variable is defined (in imx8m/soc.c),
so that should be fine.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Rasmus Villemoes
8e290150e3 imx8: add hidden IMX8_ROMAPI Kconfig symbol
In order not to repeat the IMX8MN || IMX8MP || IMX8ULP logic in
multiple places where we need to know if the SOC exposes the ROM API,
add a "def_bool y" Kconfig symbol.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25 15:35:34 +02:00
Tim Harvey
408349acbf arm: dts: imx8mm-venice-gw700x: add support for GPY111 phy
The TI DP83867 phy has been replaced with the MaxLinear GPY111 phy
due to part availability. Add support for it:
 - increase post-reset time to 300ms per datasheet
 - leave tx-delay/rx-delay undefined in dt defaulting to 2.0ns

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-07-25 15:08:23 +02:00
Pali Rohár
ca85b5a146 arm: mvebu: turris_omnia: Set ETHPRIME to DT alias
CONFIG_ETHPRIME can be set to DT node name or alias which refers to DT
node. Define ethernet aliases and set ETHPRIME to eth2 which refers to WAN
ethernet port. This removes hardcoded DT node name from U-Boot
configuration file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Pali Rohár
3308933d2f arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times
Change detection of platform/cpu from runtime to compile time via config
define. This completely eliminates compiling code which is not going to run
on selected platform. Code which parses and prints device / revision id
still reads device id from MVEBU_REG_PCIE_DEVID register, but only once.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Marek Behún
61143f741e treewide: Fix Marek's name and change my e-mail address
Fix diacritics in some instances of my name and change my e-mail address
to kabel@kernel.org.

Add corresponding .mailmap entries.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Robert Marko
b4108f3fd3 arm: mvebu: add support for Methode eDPU
Methode eDPU is an Armada 3720 power board based on the Methode uDPU.

They feature the same CPU, RAM, and storage as well as the form factor.

However, eDPU only has one SFP slot plus a copper G.hn port which does not
work under U-boot.

In order to reduce duplication, split the uDPU DTS into a common one.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 10:14:04 +02:00
Robert Marko
58b39652bb arm: mvebu: dts: sync DTS
Update the uDPU DTS to the version that is pending upstream [1][2][3][4].

[1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220516124828.45144-4-robert.marko@sartura.hr/
[2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220516124828.45144-5-robert.marko@sartura.hr/
[3] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220516124828.45144-6-robert.marko@sartura.hr/
[4] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220516124828.45144-7-robert.marko@sartura.hr/

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 07:46:10 +02:00
Chris Packham
8fd3cf2940 arm64: mvebu: handle non-zero base address for RAM
board_get_usable_ram_top() conflated the RAM size with the top address
of RAM. On systems where RAM starts at address 0 these numbers are the
same so it went unnoticed. Update board_get_usable_ram_top() to take
CONFIG_SYS_SDRAM_BASE into account when determining the top address.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-21 07:46:10 +02:00
Samuel Holland
a35628ec33 sunxi: Move INITIAL_USB_SCAN_DELAY to driver Kconfig
This option is used only by the phy-sun4i-usb driver, which does not
inherently depend on the ARM architecture.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18 23:48:09 +01:00
Michal Suchanek
e038c7a201 sunxi: lcd: Move range from kconfig description to definition.
KConfig has range option, use it instead of notice in the option
descrition.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18 11:34:26 +01:00
Tom Rini
54f683dbfb Merge https://source.denx.de/u-boot/custodians/u-boot-usb 2022-07-14 11:10:49 -04:00
Tom Rini
357fa8bb4d - Alignment with Linux kernel device tree v5.19 for stm32mp15 and stm32mp13
- Add OP-TEE nodes for stm32mp13x, alligned with upstreamed OP-TEE
 - Introduce of_to_plat ops in stm32_sdmmc2 driver
 - Activate more features in stm32mp13 defconfig and support of STM32MP13x Rev.Y
 - Drop fastboot and stm32prog trigger gpios on STM32MP15x DHCOM board
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Merge tag 'u-boot-stm32-20220712' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Alignment with Linux kernel device tree v5.19 for stm32mp15 and stm32mp13
- Add OP-TEE nodes for stm32mp13x, alligned with upstreamed OP-TEE
- Introduce of_to_plat ops in stm32_sdmmc2 driver
- Activate more features in stm32mp13 defconfig and support of STM32MP13x Rev.Y
- Drop fastboot and stm32prog trigger gpios on STM32MP15x DHCOM board
2022-07-13 08:09:20 -04:00
Michal Simek
f36479e302 ti: keystone: Don't select GPIO_EXTRA_HEADER
keystone doesn't have custom gpio.h that's why don't select
GPIO_EXTRA_HEADER which points to it.

Logic in arch/arm/include/asm/gpio.h is very clear

 #ifdef CONFIG_GPIO_EXTRA_HEADER
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>

Where it is visible that there is no gpio.h in platform headers:
$ ls arch/arm/mach-keystone/include/mach/
clock_defs.h  clock-k2e.h  clock-k2hk.h  ddr3.h      hardware-k2e.h
hardware-k2hk.h  i2c_defs.h      mon.h   mux-k2g.h   xhci-keystone.h
clock.h       clock-k2g.h  clock-k2l.h   hardware.h  hardware-k2g.h
hardware-k2l.h   mmc_host_def.h  msmc.h  psc_defs.h

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-12 21:59:54 +02:00
Johann Neuhauser
48d9eaf682 arm: dts: stm32mp1: Drop fastboot and stm32prog trigger gpios on DHCOM
PA13 and PA14 are used for USB power control and can't be used
to enforce fastboot or stm32prog mode by pressing a button.

Defining CONFIG_FASTBOOT/CONFIG_CMD_STM32PROG without this patch applied
results in fastboot/stm32prog always starting, because PA13/PA14 are always
low during boot. So drop the wrong trigger gpios definitions.

Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-07-12 11:48:15 +02:00
Patrick Delaunay
6d647676ea ARM: dts: stm32mp13: activate led on STM32MP13F-DK
Activate the led managed in stm32mp1 board for U-Boot indication
in STM32MP13F-DK device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:48:15 +02:00
Patrick Delaunay
12d5a0626c ARM: dts: stm32mp13: alignment with v5.19
Device tree alignment with Linux kernel v5.19-rc1 with:
- ARM: dts: stm32: add UserPA13 button on stm32mp135f-dk
- ARM: dts: stm32: add blue led (Linux heartbeat) on stm32mp135f-dk
- ARM: dts: stm32: add EXTI interrupt-parent to pinctrl node on stm32mp131
- ARM: dts: stm32: enable RTC support on stm32mp135f-dk
- ARM: dts: stm32: add RTC node on stm32mp131
- ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:48:09 +02:00
Patrick Delaunay
50b371fd68 stm32mp: add support of STM32MP13x Rev.Y
Add support of STM32MP13x Rev.Y for the Silicon revision REV_ID = 0x1003.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:47:34 +02:00
Patrick Delaunay
6cccc8d396 ARM: dts: stm32: add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)
Add a "secure" version of STM32 boards based on SCMI when RCC_TZCR.TZEN=1.

Only boards provided by STMicroelectronics are concerned:
-STM32MP157A-DK1
-STM32MP157C-DK2
-STM32MP157C-ED1
-STM32MP157C-EV1

The resources secured by RCC_TZCR.TZEN=1 are managed by OP-TEE
and the associated SCMI services, reset and clock.

These device trees are only supported with stm32mp15_defconfig,
with OP-TEE, SCMI and without SPL support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:46:32 +02:00
Patrick Delaunay
69ef98b209 ARM: dts: stm32mp15: alignment with v5.19
Device tree alignment with Linux kernel v5.19-rc1

- ARM: dts: stm32: Add alternate pinmux for ethernet0 pins
- ARM: dts: stm32: Add alternate pinmux for mco2 pins
- ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)
- ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group
- dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
- dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
- dt-bindings: clock: stm32mp15: rename CK_SCMI define
- dt-bindings: reset: stm32mp15: rename RST_SCMI define
- dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains
  on stm32mp15
- dt-bindings: clk: cleanup comments
- ARM: dts: align SPI NOR node name with dtschema
- ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15
- ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)
- ARM: dts: stm32: move SCMI related nodes in a dedicated file for
  stm32mp15

+ patch from stm32-dt-for-v5.19-fixes-2

- ARM: dts: stm32: move SCMI related nodes in a dedicated file for
  stm32mp15
- ARM: dts: stm32: fix pwr regulators references to use scmi
- ARM: dts: stm32: use the correct clock source for CEC on stm32mp151
- ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board
- ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI
- ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:46:31 +02:00
Patrick Delaunay
44db098ae1 ARM: dts: stm32mp13: add SCMI nodes
Add the node for SCMI firmware with the associated reserved memory nodes

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:46:30 +02:00
Patrick Delaunay
0b69ce6a81 ARM: dts: stm32mp13: add OP-TEE nodes
Add the node for OP-TEE firmware with the associated reserved memory nodes

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-07-12 11:46:18 +02:00
Tom Rini
36b661dc91 Merge branch 'next' 2022-07-11 14:58:57 -04:00
Tom Rini
cb42c1f9b1 i2c: Remove non-DM_I2C support from davinci_i2c.c
As the migration deadline has passed, and all platforms have been
migrated, remove the non-DM code here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-08 17:57:34 -04:00
Tom Rini
edcbd6e388 omap3: emif4: More clearly hard-code cs0 size
We have a single platform that is both in the OMAP3 family of parts, but
has an EMIF4 memory controller.  Currently we hard-code the size of
chip select 0.  Make this more clear by putting the value in the
function rather than a CONFIG option.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-08 17:57:34 -04:00
Tom Rini
95cc3efcc1 arm: Remove strongarm support
There are no platforms using this architecture anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-08 17:57:33 -04:00
Tom Rini
9ff4ce8abc nman external-symbol improvements
Driver model memory-usage reporting
 patman test-reporting improvements
 Add bloblist design goals
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Merge tag 'dm-pull-28jun22' of https://source.denx.de/u-boot/custodians/u-boot-dm into next

nman external-symbol improvements
Driver model memory-usage reporting
patman test-reporting improvements
Add bloblist design goals
2022-07-08 14:39:07 -04:00
Tom Rini
bb20a105e9 Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_BOOT_RAMDISK_HIGH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 14:01:09 -04:00
Tom Rini
a457ebd786 arm: Remove PXA architecture support
With the last platform for this architecture removed, remove the rest of
the architecture support as well.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-07 09:29:08 -04:00
Tom Rini
d9d4978143 thunerx_88xx: Clean up config slightly.
We don't use CONFIG_SYS_64BIT anywhere and can use
CONFIG_TARGET_THUNDERX_88XX to build the device trees.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
2bb9d7c65a Convert CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
   CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
f1c6dfa426 layerscape: Remove some unused CONFIG symbols
All of these symbols are not referenced anywhere else in the code, so
remove them.

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
cd6a45a41f Convert CONFIG_USB_OHCI_NEW et al to Kconfig
This converts the following to Kconfig:
    CONFIG_SYS_OHCI_SWAP_REG_ACCESS
    CONFIG_SYS_USB_OHCI_CPU_INIT
    CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
    CONFIG_SYS_USB_OHCI_SLOT_NAME
    CONFIG_USB_ATMEL
    CONFIG_USB_ATMEL_CLK_SEL_PLLB
    CONFIG_USB_ATMEL_CLK_SEL_UPLL
    CONFIG_USB_OHCI_LPC32XX
    CONFIG_USB_OHCI_NEW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
b340199f82 spl: Ensure all SPL symbols in Kconfig have some SPL dependency
Tighten up symbol dependencies in a number of places.  Ensure that a SPL
specific option has at least a direct dependency on SPL.  In places
where it's clear that we depend on something more specific, use that
dependency instead.  This means in a very small number of places we can
drop redundant dependencies.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Joel Stanley
3045d61c1c aspeed/spl: Remove OVERLAY from linker script
The generic arm linker script contains this section:

   .bss __rel_dyn_start (OVERLAY) : {
       ...
   }

The (OVERLAY) syntax in the description causes the .bss section to be
included in the NOR area of the image:

 $ objdump -t -j .bss spl/u-boot-spl
  SYMBOL TABLE:
  0000c61c l    d  .bss	00000000 .bss
  0000c640 l     O .bss	00000040 __value.0
  0000c68c g     O .bss	00000000 __bss_end
  0000c61c g     O .bss	00000000 __bss_start
  0000c680 g     O .bss	0000000c stdio_devices

This is what the custom linker script tries to avoid, as the NOR area is
read-only.

Remove the OVERLAY syntax to fix the BSS location:

 $ objdump -t -j .bss spl/u-boot-spl
  SYMBOL TABLE:
  83000000 l    d  .bss	00000000 .bss
  83000000 l     O .bss	00000040 __value.0
  0000c61c g     O .bss	00000000 __image_copy_end
  8300004c g     O .bss	00000000 __bss_end
  83000000 g     O .bss	00000000 __bss_start
  83000040 g     O .bss	0000000c stdio_devices

This restores the state of the linker script before the patch that fixed
the linker lists issue.

Fixes: f6810b749f ("aspeed/ast2600: Fix SPL linker script")
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:32:00 -04:00
Joel Stanley
0b2a749bc6 ARM: dts: ast2500: Update SDHCI nodes
Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
dedf8e3186 ARM: dts: ast2600: Update SDHCI nodes
Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
b45768ebfe ARM: dts: ast2600-evb: Add I2C devices
The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7,
and a LM75 temp sensor on bus 8.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Joel Stanley
5ff466fade ARM: dts: ast2500-evb: Add I2C devices
The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable
those busses we can test the I2C driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
3ad1d85d3c ARM: dts: ast2600-evb: Remove redundant pinctrl
Now that these are in the dtsi we don't need them in the EVB device
tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Joel Stanley
fc28e02404 ARM: dts: ast2600: Disable I2C nodes by default
Allow boards to enable the buses they use.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
a87273bc40 ARM: dts: ast2600: Add I2C reset properties
The same as the upstream Linux device tree, each i2c bus has a property
specifying the reset line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Eddie James
8c3019216e ARM: dts: ast2600: Add I2C pinctrl
Set the pinctrl groups for each I2C bus. These are essential to
I2C operating correctly.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Georgi Vlaev
362b0d2e6e arm: dts: k3-am625-*: Mark memory with u-boot,dm-spl
Mark the memory node with u-boot,dm-spl so we can use it
from early SPL on both R5 and A53.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Georgi Vlaev
a04bbb83b4 arm: mach-k3: common: Use ddr_init in spl_enable_dcache
The spl_enable_dcache() function calls dram_init_banksize()
to get the total memory size. Normally the dram_init_banksize()
setups the memory banks, while the total size is reported
by ddr_init(). This worked so far for K3 since we set the
gd->ram_size in dram_init_banksize() as well.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Vaishnav Achath
c16b4f14a3 arm: k3: j721e: add dynamic sf bus override support for j721e
implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs()
lookup functions according to bootmode selection, so as to support
both QSPI and OSPI boot using the same build.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2022-07-06 14:30:08 -04:00
Tom Rini
432243cee1 Convert CONFIG_KIRKWOOD_PCIE_INIT et al to Kconfig
This converts the following to Kconfig:
   CONFIG_KIRKWOOD_EGIGA_INIT
   CONFIG_KIRKWOOD_PCIE_INIT
   CONFIG_KIRKWOOD_RGMII_PAD_1V8
   CONFIG_KM_DISABLE_PCIE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
52aaa1840d nxp: config_fsl_chain_trust.h: Clean up and remove unused portions
The way that secure boot is implemented today on NXP ARM platforms does
not reuse the elements found in include/config_fsl_chain_trust.h to
construct CONFIG_SECBOOT but instead board header files have their
environment setup as needed and then fsl_setenv_chain_of_trust() will
set secureboot in the environment.  Remove a large number of unused
defines here.

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:01 -04:00
Tom Rini
5aad0a14ba fsl_validate: Migrate SPL_UBOOT_KEY_HASH to Kconfig
Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig.  As
part of this, change fsl_secboot_validate(...) to check that it is
passed a non-empty string, rather than non-NULL.

Cc: Peng Fan <peng.fan@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:01 -04:00
Tom Rini
540b73a7be arch/Kconfig.nxp: Re-organize slightly
Make all of the CHAIN_OF_TRUST options be under a single menu and add a
comment for the rest, so the resulting config file reads more clearly.
Remove duplicate CHAIN_OF_TRUST options from
board/congatec/common/Kconfig.  Remove duplicate NXP_ESBC config
questions and move to arch/Kconfig.nxp.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:01 -04:00
Tom Rini
601483ffd5 Convert CONFIG_SYS_FSL_SFP_BE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_KEY_REVOCATION
   CONFIG_SYS_FSL_SFP_BE
   CONFIG_SYS_FSL_SFP_LE
   CONFIG_SYS_FSL_SFP_VER_3_0
   CONFIG_SYS_FSL_SFP_VER_3_2
   CONFIG_SYS_FSL_SFP_VER_3_4
   CONFIG_SYS_FSL_SRK_LE

This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for
when CHAIN_OF_TRUST is enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:00 -04:00
Tom Rini
c9f85187e2 Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_SEC_MON
   CONFIG_SYS_FSL_SEC_MON_BE
   CONFIG_SYS_FSL_SEC_MON_LE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:00 -04:00
Tom Rini
2b2817b5c8 Convert CONFIG_ESBC_HDR_LS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_ESBC_HDR_LS
   CONFIG_ESBC_ADDR_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:02 -04:00
Tom Rini
1f7e2fc324 Convert CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR to Kconfig
This converts the following to Kconfig:
   CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
de0a732915 Rename CONFIG_PWM to CONFIG_PWM_S5P and move to Kconfig
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to
Kconfig.  Given the usage of CONFIG_PWM_NX, we have that select this new
symbol.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-07-05 17:03:01 -04:00
Tom Rini
9fcc2fb3fe Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline 2022-07-01 09:14:32 -04:00
Tom Rini
085fea0b65 - search dtb for meson-axg-usb-ctrl on board axg
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Merge tag 'u-boot-amlogic-20220701' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- search dtb for meson-axg-usb-ctrl on board axg
2022-07-01 09:13:58 -04:00
Paweł Anikiel
e26ecebc68 socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea4519 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:15 +08:00
Paweł Anikiel
aea0e80a9f socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
61298270c5 config: Add Chameleonv3 config
Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
8566b3682f arm: dts: Add Chameleonv3 devicetrees
Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
882c00edeb arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
e21b8ac3f1 arm: dts: Add Mercury+ AA1 devicetrees
Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:13 +08:00
Tom Rini
284c1a9b4b First set of u-boot-at91 features for the 2022.10 cycle
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Merge tag 'u-boot-at91-2022.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.10 cycle:

This feature set includes mostly fixes and alignments: DT alignment with
Linux for sama7g5, removal of invalid eeprom compatibles, removal of
extra debug_uart_init calls for all at91 boards, support for pio4 driver
pioE bank, and other minor fixes and enhancements for sam9x60 and
sama5d2_icp boards.
2022-06-30 15:21:52 -04:00
Tom Rini
c5e7003aa8 Versal QSPI/OSPI changes for v2022.10
- Add new flash types
 - Add cadence ospi driver for Xilinx Versal
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Merge tag 'versal-qspi-for-v2022.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Versal QSPI/OSPI changes for v2022.10

- Add new flash types
- Add cadence ospi driver for Xilinx Versal
2022-06-30 09:32:15 -04:00
Mihai Sain
c1cadac793 gpio: atmel_pio4: add support for PIO_PORTE
Add support for gpio PORT E, which is available on e.g. sama7g5 SoC.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-06-30 15:49:00 +03:00
T Karthik Reddy
248fe9f302 spi: cadence_qspi: Enable apb linear mode for apb read & write operations
On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 16:00:31 +02:00
T Karthik Reddy
bf8dae5fcf spi: cadence-qspi: reset qspi flash for versal platform
When flash operated at non default mode like DDR, flash need to be reset
to operate in SDR mode to read flash ids by spi-nor framework. Reset the
flash to the default state before using the flash. This reset is handled
by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we
do raw read and write access by the registers.
Versal platform utilizes spi calibration for read delay programming, so
incase by default read delay property is set in DT. We make sure not to
use read delay from DT by overwriting read_delay with -1.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 16:00:31 +02:00
Peter Robinson
fce1e9bba2 rockchip: pinebook-pro: sync PBP dtb to 5.18
Sync the pinebook pro to upstream 5.18, in particular this brings
brings in a fix so the DP is disabled so Linux will actually boot.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:43:05 +08:00
Chris Morgan
30975fb73d rockchip: Add option to prevent booting on power plug-in
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-29 11:42:10 +08:00
Jerome Forissier
348310233d mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.

Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.

With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].

Link: [1] 5dd1570ac5
Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-29 11:32:35 +08:00
Johan Jonker
6f0037f305 arm: dts: rockchip: rk3288: move dma-controller nodes
In order to better compare the Linux rk3288.dtsi version
with the u-boot version move the dma-controller nodes
to the DT root.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:29:52 +08:00
Johan Jonker
e0bf010ab9 arm: dts: rockchip: rk3288: sort mipi hdmi lvds and dp nodes
In order to better compare the Linux rk3288.dtsi version
with the u-boot version sort the mipi,hdmi,lvds and dp nodes.

Changed:
  Rename mipi_dsi label.
  Rename dp nodename.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:29:03 +08:00
Johan Jonker
170447466c arm: dts: rockchip: rk3288: bulk convert gpios to their constant counterparts
Bulk convert rk3288 DT gpios to their constant counterparts.

Partial Linux sync for the rk3288.dtsi file.

ARM: dts: rockchip: bulk convert gpios to their constant counterparts
https://lore.kernel.org/all/20190402121852.14442-1-heiko@sntech.de/

sed -i -f script.sed rk3288.dtsi

================================

/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:38 +08:00
Johan Jonker
196e0c6223 arm: dts: rockchip: remove usb-phy fallback string for rk3188
With the conversion of rockchip-usb-phy.yaml a long time used fallback
string for rk3066a/rk3188 was added. The linux driver doesn't do much with
the GRF phy address range, however the u-boot driver rockchip_usb2_phy.c
does. The bits in GRF_UOC0_CON2 for rk3066a/rk3188 and rk3288 for example
don't match. Remove the usb-phy fallback string for rk3188
to prevent possible strange side effects.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:16 +08:00
Johan Jonker
e0479b71ed rockchip: board: change condition board_usb_init() in function
Change define condition in board_usb_init() function
to allow rk3066/rk3188 to use the USB PHY driver.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:16 +08:00
Tom Rini
3371eddaa1 Convert CONFIG_USB_MAX_CONTROLLER_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:11:48 -04:00
Tom Rini
3a21d45d33 siemens: Move CONFIG_FACTORYSET to Kconfig
Introduce board/siemens/common/Kconfig and have it hold FACTORYSET to
start with.  Use select for this on the boards that need it.

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:04:38 -04:00
Tom Rini
24ec3dea4b arm: samsung: Migrate a number of symbols to Kconfig
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than
  CONFIG_EXYNOS[45]
- In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX
- Migrate specific SoC CONFIG values to Kconfig
- Use CONFIG_TARGET_x rather than CONFIG_x
- Migrate other CONFIG_EXYNOS_x symbols to Kconfig
- Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE
- Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest
  of U-Boot usage.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:04:37 -04:00
Tom Rini
1e03e03d03 arm: exynos: Remove old pwm backlight driver
Remove the unused older exynos pwm backlight driver.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28 17:03:32 -04:00
Tom Rini
dc2d27ae72 arm: samsung: Remove dead LCD code
Since bb5930d5c9 ("exynos: video: Convert several boards to driver
model for video") there have been no callers of any of the exynos_lcd_*
family of functions.  Remove these from the boards, and then remove
unused logo and related code as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28 17:03:32 -04:00
Tom Rini
aca1f6789a Convert CONFIG_LBA48 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_LBA48
   CONFIG_SYS_64BIT_LBA

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:32 -04:00
Tom Rini
5858b90f50 spl: Move SPL_LDSCRIPT defaults to one place
We want to keep all of the default values for SPL_LDSCRIPT in the same
place both for overall clarity as well as not polluting unrelated config
files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
7ef53a3dc6 Convert CONFIG_TEGRA_GPU to Kconfig
This converts the following to Kconfig:
   CONFIG_TEGRA_GPU

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
093044735f usb: ehci-fsl: Remove non-DM code
The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
d6e9efa6b2 Convert CONFIG_EFLASH_PROTSECTORS to Kconfig
This converts the following to Kconfig:
   CONFIG_EFLASH_PROTSECTORS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:30 -04:00
Joel Stanley
f6810b749f aspeed/ast2600: Fix SPL linker script
The commit 99e2fbcb69 ("linker_lists: Rename sections to remove .
prefix") changed the name of the linker list sections. As the Aspeed SPL
linker wasn't in the tree yet, it missed the change.

This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which
Aspeed was copied from.

Fixes: 442a69c143 ("configs: ast2600: Move SPL bss section to DRAM space")
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-28 09:40:03 -04:00
Fabio Estevam
b5023254b8 kontron-sl-mx8mm: Add CAAM support
Add CAAM support, which is required when enabling HAB secure boot.

Select CONFIG_SPL_DRIVERS_MISC so that CONFIG_IMX_HAB could
build successfully, if selected.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-06-28 15:24:31 +02:00
Francesco Dolcini
6b5ecb8293 mx6: ddr: Fix disabling on-die termination
In case rtt_nom is set to 0 keep ODT disabled (MMDC MPODTCTRL = 0).
No changes required for DDR MR1 Rtt_Nom impedance register, 0 value is
already handled correctly.

No board is currently affected by this change (rtt_nom != 0 on all i.MX6
ddr3 boards), this will be used by a follow-up change.

Fixes: fe0f7f7842 ("mx6: add mmdc configuration for MX6Q/MX6DL")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-06-28 15:24:31 +02:00
Andrejs Cainikovs
0543a1ed27 imx8m: fixup thermal trips
Fixup thermal trips in Linux device tree according to SoC thermal
grade.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tested-by: Adam Ford <aford173@gmail.com>
2022-06-28 13:35:09 +02:00
Eugen Hristev
5ae89b3cfe ARM: dts: at91: sam9x60ek: fix eeprom compatible
The memory on this board is microchip 24aa025e48 which is compatible with
at24c02 with a page size of 16.
Fix the compatible accordingly.

Reported-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-28 10:09:45 +03:00
Eugen Hristev
0d60a93053 ARM: dts: at91: replace microchip, 24aa02e48 with atmel, at24c02
microchip,24aa025e48 does not exist in the bindings of this driver.
It can be replaced with atmel,at24c02 which is a standard compatible
and the memory is compatible with this one, depending on the page size.
microchip 24aa02e48 has a page size of 8, while 24aa025e48 has a page
size of 16 bytes.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-28 10:09:45 +03:00
Eugen Hristev
d4d3c33393 ARM: dts: at91: sama7g5/sama7g5ek: sync with kernel at91 5.19
Sync with at91 maintainer tree for-5.19 branch.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-06-28 10:09:45 +03:00
Sergiu Moga
474130944d ARM: dts: sam9x60: fix compatible for qspi child node
Change the compatible of the qspi child node to
`jedec,spi-nor` so that it can be properly found
when probing the bus.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-06-28 10:09:45 +03:00
Peng Fan
e87da5704f armv8: u-boot-spl.lds: mark __image_copy_start as symbol
In arch/arm/lib/sections.c there is below code:
char __image_copy_start[0] __section(".__image_copy_start");
But actually 'objdump -t spl/u-boot-spl' not able to find out
symbol '__image_copy_start' for binman update image-pos/size.

So update link file

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-28 03:09:52 +01:00
Loic Poulain
0fcc1c76d1 armv8 SHA-256 using ARMv8 Crypto Extensions
This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs
that have support for the SHA-256 part of the ARM v8 Crypto Extensions.

It greatly improves sha-256 based operations, about 17x faster on iMX8M
evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification.

asm implementation is a simplified version of the Linux version (from
Ard Biesheuvel).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27 13:36:28 -04:00
Loic Poulain
084d8e6bf9 armv8 SHA-1 using ARMv8 Crypto Extensions:
This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs
that have support for the SHA-1 part of the ARM v8 Crypto Extensions.

It greatly improves sha-1 based operations, about 10x faster on iMX8M
evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification.

asm implementation is a simplified version of the Linux version (from
Ard Biesheuvel).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-27 13:36:28 -04:00
Tom Rini
c316ee674f Xilinx changes for v2022.10
cpu:
 - Add driver for microblaze cpu
 
 net:
 - Add support for DM_ETH_PHY to AXI emac and emaclite
 
 xilinx:
 - Switch platforms to DM_ETH_PHY
 - DT chagnes in ZynqMP and Zynq
 - Enable support for SquashFS
 
 zynqmp:
 - Add support for KR260 boards
 - Move BSS from address 0
 - Move platform identification from board code to soc driver
 - Improve zynqmp_psu_init_minimize
 
 versal:
 - Enable loading app at EL1
 
 serial:
 - Setup default address and clock rates for DEBUG uarts
 
 pinctrl:
 - Add support for tri state and output enable properties
 
 relocate-rela:
 - Clean relocate-rela implementation for ARM64
 - Add support for Microblaze
 
 microblaze:
 - Add support for runtime relocation
 - Rework cache handling (wiring, Kconfig) based on cpuinfo
 - Remove interrupt support
 
 timer:
 - Extract axi timer driver from Microblaze to generic location
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYrlYngAKCRDKSWXLKUoM
 ITgbAJ9S9xO2QqxtuodWAYMtJfvZ14c7mgCeKnyFTrrBnJkC0wPsGqE71oNJ49o=
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Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
2022-06-27 10:15:50 -04:00
qianfan Zhao
47ca7b574f sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platform
linux system will die if we offline one of the cpu on R40 based board:
eg: echo 0 > /sys/devices/system/cpu/cpu3/online

The reason is that the R40 version of sunxi_cpu_set_power always passes
0 for the CPU number, so we turn off CPU0, regardless of what CPU the
CPU_OFF request came for.

Fix this by passing the proper CPU number, as there are proper power
clamp registers for every of the four cores.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:54 +01:00
Samuel Holland
006ef34bd4 ARM: dts: sun4i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

The previous version of this change was only partially applied.

Fixes: 4746694cba ("ARM: dts: sun4i: Sync from Linux v5.18-rc1")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:53 +01:00
Amit Kumar Mahapatra
a13e0821da ARM: zynq: Fix size-cells for pl353 driver
"size-cells" of the nand controller node should be 0 as the "reg"
property of the nand device node contains the chip select number and not
address information.
The patch fixes the below compilation warning
arch/arm/dts/zynq-zc770-xm011.dtb: Warning (reg_format):
/axi/memory-controller@e000e000/nand-controller@0,0/nand@0:reg: property
has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6e90665a2dad7fe8ade10b8f57101f8144963791.1655288559.git.michal.simek@amd.com
2022-06-24 14:18:02 +02:00
Ashok Reddy Soma
b8745e7eb4 arm64: zynqmp: Fix usb node drive strength and slew rate
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb gorup pins.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
2022-06-24 14:17:18 +02:00
Michal Simek
686c2bbb44 arm64: zynqmp: Fix tps544/u3007 node description
u3007 is removed in zynqmp-m-a2197-02-revA board and on
zynqmp-m-a2197-03-revA it was renamed to v3022 at address 0x18.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f477796bcca6fce09168699a0498d792f4a54acf.1655287013.git.michal.simek@amd.com
2022-06-24 14:14:34 +02:00
Michal Simek
5f5979f430 arm64: zynqmp: Update tps53681 i2c address
TI manual (https://www.ti.com/lit/gpn/TPS53681) is saying that i2c address
is 7bit where c0h is 1100000 which is 0x60.

This will fix issues reported by make dtbs that 0xc0 is above 7bit regular
i2c address range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2f50c1cd258f6b05deb2a6a9af7fa92952f3f8cb.1655287013.git.michal.simek@amd.com
2022-06-24 14:14:33 +02:00
Michal Simek
0b0d433b6c arm64: zynqmp: Fix i2c addresses for vck190 SC
si570 is normally at 0x5d address and address is not aligned with address
in node.
8T49N240 can't be at 0xd8 that's why it is shifter by one bit.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4fa86fffa9cb8abe633fbc5a9c55bea249b5edfb.1655287013.git.michal.simek@amd.com
2022-06-24 14:14:33 +02:00
Michal Simek
b611f7faf9 arm64: zynqmp: Enable DP for kv260-revA board
DP is enabled for revB and should be enabled for kv260-revA too. Changes in
other boards were done by commit 8b82a3a7fe ("arm64: zynqmp: Enable DP
driver for SOMs").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4e273bce3a8acf4495b67b702b1704acec8d9ccb.1654779436.git.michal.simek@amd.com
2022-06-24 14:14:25 +02:00
Michal Simek
baba22addd arm64: zynqmp: Add support for kr260 revA/B boards
Board is using kv260 design for couple of parts defined by spec like i2c
eeproms, ina260, uart, etc.

Board has 4 gems. One gem connected via PS SGMII(GT), another PS RGMII(MIO)
and 2 via EMIO. First two shares the same MIO lines for PHYs. PL based one
have separate EMIO lines via PL.

Also two USB 3.0 with usb hubs are present. USB phys and USB hubs should
have separate reset line. The first usb0 hub also has USB-SD controller
(usb2244) connected to port 0.

To test compatibility with k26 you can run:
fdtoverlay -o /tmp/output.dtb -i arch/arm/dts/zynqmp-sm-k26-revA.dtb \
arch/arm/dts/zynqmp-sck-kr-g-revA.dtbo

Also add support for kr260-revB board. Based on FRU it is revision B
but schematics can be label as revA03.
Changes in revB are:
- SFP light
- GEM2/3 TX_CLK fixes
- PMOD/RPI connector fixes
- Replace si5332 with oscilators

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dac2ee1826e73b89c8cc1e430354eb43d291f675.1652870941.git.michal.simek@amd.com
2022-06-24 14:11:05 +02:00
Michal Simek
254f0c766d arm64: zynqmp: Add debug messages to bl2_plat_get_bl31_params()
It is useful to get information about BL type and entry address that's why
add some debug messages.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fb023b618a009009a0b564c24223cadc10ced5b3.1652871741.git.michal.simek@amd.com
2022-06-24 14:11:05 +02:00
Andrew Scull
99e2fbcb69 linker_lists: Rename sections to remove . prefix
Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.

Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.

Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-23 12:58:18 -04:00
Frieder Schrempf
c0b71a1731 imx: kontron-sl-mx8mm: Remove deprecated phy-mode property
This was previously needed, but U-Boot is now capable of parsing
the new "phy-connection-type" property that is already used in
the main devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-23 08:25:02 -04:00
Frieder Schrempf
fecfe77c48 imx: kontron-sl-mx8mm: Sync dts files and fix ethernet
This syncs the devicetree files with the latest Linux kernel (5.19-rc2).
This also fixes the currently broken ethernet support:

Before:

  Net:   Could not get PHY for FEC0: addr 0

After:

  Net:   eth0: ethernet@30be0000

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-23 08:24:49 -04:00
Janne Grunau
942b54b4ee arm: apple: Increase RTKit timeouts
Timeouts are not expected to happen and are handled as fatal errors.
Increase all timeouts to 1 second as defensive measure to avoid relying
on the timing behaviour of certain firmware versions or configurations.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Janne Grunau
e44d59c6ad arm: apple: nvme: Add SART support and RTKit buffer management
The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's
current minimal RTKit implementation. It does not provide buffers for
the firmware's buffer requests. The ANS2 firmware included in macOS 11
and 12 tolerates this. The firmware included in the first macOS 13 beta
requires buffers for the crashlog and ioreport endpoints to function.

In the case of the NVMe the buffers are physical memory. Access to
physical memory is guarded by what Apple calls SART.
Import m1n1's SART driver (exclusively used for the NVMe controller).
Implement buffer management helpers for RTKit. These are generic since
other devices (none in u-boot so far) require different handling.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Jim Liu
0ae1c77199 misc: nuvoton: Add NPCM7xx otp controller driver
Add Nuvoton BMC npcm750 otp driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Jim Liu
9e03b48dfa crypto: nuvoton: Add NPCM7xx AES driver
add nuvoton BMC npcm750 AES driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Chia-Wei Wang
12770d0df0 ast2600: spl: Add boot mode detection
AST2600 supports boot from SPI(mmap), eMMC, and UART.
This patch adds the boot mode detection and return the
corresponding boot device type.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-06-22 21:30:05 -04:00
Chia-Wei Wang
442a69c143 configs: ast2600: Move SPL bss section to DRAM space
The commit b583348ca8 ("image: fit: Align hash output buffers") places
the hash output buffer at the .bss section. However, AST2600 by default
executes SPL in the NOR flash XIP way. This results in the hash output
cannot be written to the buffer as it is located at the R/X only region.

We need to move the .bss section out of the SPL body to the DRAM space,
where hash output can be written to. This patch includes:
 - Define the .bss section base and size
 - A new SPL linker script is added with a separate .bss region specified
 - Enable CONFIG_SPL_SEPARATE_BSS kconfig option

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>
2022-06-22 21:30:05 -04:00
Nick Hawkins
2b7a89bc94 ARM: dts: Add device tree files for hpe gxp soc
The HPE SoC is new to linux. A basic device tree layout with minimum
required for linux to boot including a timer and watchdog support has
been created.

The dts file is empty at this point but will be updated in subsequent
updates as board specific features are enabled.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22 21:30:05 -04:00
Nick Hawkins
4276c9b2aa ARM: hpe: gxp: add core support
The GXP is the HPE BMC SoC that is used in the majority
of current generation HPE servers. Traditionally the asic will
last multiple generations of server before being replaced.

Info about SoC:

HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
features at HPE. It supports ARMv7 architecture based on the Cortex A9
core. It is capable of using an AXI bus to whicha memory controller is
attached. It has multiple SPI interfaces to connect boot flash and BIOS
flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
i2c engines to drive connectivity with a host infrastructure. There
currently are no public specifications but this process is being worked.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22 21:30:04 -04:00
Rui Miguel Silva
f98457d70a arm: add support to corstone1000 platform
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].

This code adds the support for the Cortex-A35 implementation
at host side, it contains also the necessary bits to support
the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the
FPGA MPS3 board implementation of this platform. [2]

0: https://developer.arm.com/documentation/102360/0000
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://developer.arm.com/documentation/dai0550/c/

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-22 12:35:15 -04:00
Anthoine Bourgeois
a47ce34403 ARM: dts: omap3-devkit8000: Fix CONFIG_DM_ETH warning
Add the missing ethernet node in u-boot dts.

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2022-06-22 10:58:26 -04:00
Anthoine Bourgeois
8d09c7b774 ARM: dts: omap3-devkit8000: Fix CONFIG_DM_I2C warning
Seems that u-boot can't probe i2c bus at 2.6Mhz speed, so lower
the speed to the default value 100Khz.

v2: fix i2c1 frequency in the root omap3-u-boot.dtsi include.

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2022-06-22 10:58:26 -04:00
Anthoine Bourgeois
49df685d32 ARM: dts: omap3-devkit8000: Add support for Devkit8000
This commit adds OMAP3 BeagleBoard devicetree files from Linux
v5.16.0.
This commit fixes CONFIG_DM_MMC warning.

v3: patch clean-up

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2022-06-22 10:58:26 -04:00
Tom Rini
52af0101be Merge branch 'master' into next
Merge in v2022.07-rc5.
2022-06-20 14:40:59 -04:00
Tom Rini
2f7821a927 - Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
 - Activate livetree for stm32mp15 DHSOM boards
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Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
2022-06-20 08:09:24 -04:00
Michael Walle
2a9cf320af armv8: layerscape: add missing RCW source defines
A board might need to get the source of the RCW word, which is also the
boot source in most cases.

These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.

Signed-off-by: Michael Walle <michael@walle.cc>
2022-06-20 15:52:45 +08:00
Sean Anderson
bcb3dae325 ARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDB
These frequency calculations depend on the RCW format, which is not
dependent on any particular board. Switch to using ARCH symbols instead
of TARGET.

This whole function could probably use less ifdefs, but for now just do
a minimal conversion.

Fixes: 24cb6f2295 ("fsl-layerscape: Add fsl_esdhc peripheral clock support")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:26 +08:00
Sean Anderson
7041601141 arch: layerscape: Add SFP binding
This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:26 +08:00
Sean Anderson
f99068a8b1 ARM: dts: ls1021a: update the clockgen node
QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).

This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:26 +08:00
Tom Rini
aad77c215c - Fix the stm32prog command for stm32mp platform
- Add stm32mp15x DHCOR based DRC Compact board
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Merge tag 'u-boot-stm32-20220617' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Fix the stm32prog command for stm32mp platform
- Add stm32mp15x DHCOR based DRC Compact board
2022-06-17 09:41:11 -04:00
Tom Rini
f0843e0c0a Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline 2022-06-17 09:35:28 -04:00
Patrick Delaunay
eae488b779 stm32mp1: fix reference for STMicroelectronics
Replace reference to the correct name STMicroelectronics

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 14:12:27 +02:00
Patrick Delaunay
7171d99296 stm32mp: stpmic1: remove the debug unit request by debugger
Depending on backup register value, U-Boot SPL maintains the debug unit
powered-on for debugging purpose; only BUCK1 is required for powering
the debug unit, so revert the setting for all the other power lanes,
except BUCK3 that has to be always on.

To be functional this patch requires a modification in the debugger
,openocd for example, to update the STM32MP15 backup register when it is
required to debug SPL after reset. After deeper analysis this behavior
will be never supported in tools so the associated code, will be never
used and the associated code can be removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 14:12:27 +02:00
Patrick Delaunay
df68a30979 stm32mp: fdt: update etzpc for STM32MP13x
Add support of STM32MP13x the ETZPC part of fdt.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: If2777fbf66b8525a2a447056780aaa04e6b0a9a0
2022-06-17 10:41:17 +02:00
Patrick Delaunay
ca9c9e7e92 stm32mp: fdt: update etzpc for STM32MP15x
Introduce STM32MP15 function and defines to prepare the
STM32MP13 introduction.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I909b205e73dcf207e0216aae5905c3c52472020e
2022-06-17 10:41:16 +02:00
Patrick Delaunay
44abcf6060 arm: dts: stm32mp: add stm32mp13 device tree for U-Boot
Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 10:41:16 +02:00
Dinesh Maniyam
5474fb894c arm: dts: socfpga: stratix10: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
7f85330782 arm: dts: socfpga: agilex: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:04 +08:00
Dinesh Maniyam
373c1428a0 arch: arm: socfpga: timer_s10: Override udelay for secure section
Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:26:52 +08:00
Patrick Delaunay
46f9eb5dcc arm: stm32mp: support 2 MAC address for STM32MP13
Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in  STM32MP13x family: STM32MP133 and STM32MP135.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
960debbe3c arm: stm32mp: add support of STM32MP13x
Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
741090c510 arm: stm32mp: add CONFIG_STM32MP15_PWR
Add config CONFIG_STM32MP15_PWR to handle the
access to regulators managed by the PWR driver defined in
pwr_regulator.c

This driver is only used in U-Boot by STM32MP15x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
d8b78fd632 arm: stm32mp: add sub config Kconfig.15x
Add sub Kconfig for each SOC in the STM32 CPU family.

It is a preliminary step to introduce a new SOC in the STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
647d319cc9 arm: stm32mp: add choice for STM32MP SOC family
Add mandatory choice for SOC support in ARCH_STM32MP.

This patch is a preliminary step for new SOC introduction
in STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
6df271a70f arm: stm32mp: move code for STM32MP15x
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
3865a7ec95 arm: stm32mp: move the get_otp helper function in bsec
As the get_otp() helper function in bsec are common for all STM32MP family,
move this function in bsec driver

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
2ff0866b45 configs: stm32mp1: move SUPPORT_SPL in STM32MP15x
The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
a82abb15a8 ARM: dts: stm32: add STM32MP13 SoCs support
Add initial support of STM32MP13 family based on v5.18-rc2

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Marek Vasut
4f71c80b0d ARM: dts: stm32: Add DHCOR based DRC Compact board
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
cb6d857db2 ARM: dts: stm32: Add alternate pinmux for SPI2 pins
Add another mux option for SPI2 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
3577cc0632 ARM: dts: stm32: Add alternate pinmux for CAN1 pins
Add another mux option for CAN1 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
9b87f12953 ARM: dts: stm32: Add alternate pinmux for UART5 pins
Add another mux option for UART5 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Marek Vasut
fb6284b5af ARM: dts: stm32: Add alternate pinmux for UART4 pins
Add another mux option for UART4 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Marek Vasut
40beedb052 ARM: dts: stm32: Add alternate pinmux for UART3 pins
Add another mux option for UART3 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Patrick Delaunay
8b91f28bc8 stm32mp: stm32prog: fix the last character of dfu_alt_add third parameter
The third parameter of dfu_alt_add(), the string description of alternate,
is build in stm32prog_alt_add() with a unnecessary character ';' at the
end of the string.

This separator was required in the first implementation of
dfu_alt_add() but is no more needed in the current implementation;
this separator is managed only in dfu_config_interfaces() which call
dfu_alt_add() for this parameter without this separator.

And since the commit 53b406369e ("DFU: Check the number of arguments
and argument string strictly"), this added character cause an error when
the stm32prog command is executed because the third parameter of
dfu_alt_add() must be a string with a numerical value; 's' must be NULL
in the result of call in dfu_fill_entity_mmc():
  third_arg = simple_strtoul(argv[2], &s, 0);

Fixes: 53b406369e ("DFU: Check the number of arguments and argument string strictly")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:30:19 +02:00
Andre Przywara
ce9c579e2b armv8: always use current exception level for TCR_ELx access
Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.

For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.

There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-16 15:22:55 -04:00
Heiko Thiery
b11b5afa6a arm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks
With the move to use DM_CLK the boards uart stops working. The used
properties are not supported by the imx8mq clock driver. Thus
the correct baudrate cannot be selected. Remove this properties here and
the board can start with working uart. Keep it in the main dts because
linux handles these porperties fine.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-06-16 15:22:55 -04:00
Christian Gmeiner
761157d310 arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.

Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2022-06-16 15:22:54 -04:00
Yau Wai Gan
f70e00fa7d arm: dts: socfpga: stratix10: Update MMC smplsel value
This new MMC sample select value is obtained from running
tests on multiple Stratix 10 boards and proven working.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:02:26 +08:00
Peng Fan
4152ea24f2 imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-06-14 21:33:14 +02:00
Peng Fan
722e2b9a2b imx: imx8mp_rsb7320a1: enable wdog driver model in SPL
Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
cbda080ae9 imx: imx8mn-beacon: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
6692cd967d imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
2d7f40cad5 imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:14 +02:00
Peng Fan
ee106eda7e imx: imx8mm_beacon: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-14 21:33:13 +02:00
Josua Mayer
17baba4682 ARM: dts: imx6qdl-sr-som: add support for alternate phy addresses
The Cubox has an unstable phy address - which can appear at either
address 0 (intended) or 4 (unintended).

SoM revision 1.9 has replaced the ar8035 phy with an adin1300, which
will always appear at address 1.

Change the reg property of the phy node to the magic value 0xffffffff,
which indicates to the generic phy driver that all addresses should be
probed. That allows the same node (which is pinned by phy-handle) to match
either the AR8035 PHY at both possible addresses, as well as the new one
at address 1.
Also add the new adi,phy-output-clock property for enabling the 125MHz
clock used by the fec ethernet controller, as submitted to Linux [1].

Linux solves this problem differently:
For the ar8035 phy it will probe both phy nodes in device-tree in order,
and use the one that succeeds. For the new adin1300 it expects U-Boot to
patch the status field in the DTB before booting

While at it also sync the reset-delay with the upstream Linux dtb.

[1] https://patchwork.kernel.org/project/netdevbpf/patch/20220428082848.12191-4-josua@solid-run.com/

Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14 21:25:26 +02:00
Fabio Estevam
e104a9f8eb imx8mn_evk: Add the missing spl.bin entry
The generated flash.bin does not boot the imx8mn evk LPDDR4 variant
as it misses the spl.bin description in binman.

Add its entry to fix the boot on the imx8mn evk LPDDR4 variant.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Arti Zirk <art@zirk.me>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-14 21:25:26 +02:00
Peter Robinson
5b060e465e ARM: tegra: XUSB padctl: Add new lines for errors
Add new lines for error messages to make them easier to read.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13 15:31:00 -07:00
Nishanth Menon
3e48d37f48 arm: dts: Add support for AM62-SK
AM62 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM625 SoC. It supports the following interfaces:
* 2 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display
* x1 Headphone Jack
* x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x4 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 20-pin header for Programmable Realtime Unit (PRU) IO pins
* 15-pin CSI header

Add basic support for AM62-SK.

To keep the changes to minimum. Only UART And SD are supported at the
moment. This should serve as good example for adding new board support
based on AM62x SoC

Schematics: https://www.ti.com/lit/zip/sprr448

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:33 -04:00
Suman Anna
900349b7dd board: ti: Introduce the basic files to support AM62 SK board
Add basic support for AM62 SK. This has 2GB DDR.
Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from
BSS and does not step on BSS section

Add only the bare minimum required to support UART and SD.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:33 -04:00
Suman Anna
1b2f4697c0 arm: dts: Introduce base AM62 SoC dtsi files
Introduce the basic AM62 SoC description dtsi files describing most
peripherals as per kernel dts.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:33 -04:00
Suman Anna
4b8903a999 arm: mach-k3: am62: Introduce autogenerated SoC data
Introduce autogenerated SoC data support clk and device data for the
AM62. Hook it upto to power-domain and clk frameworks of U-Boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:32 -04:00
Suman Anna
d98e860051 arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.

Some highlights of this SoC are:

* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
  Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
  OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
  resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
  in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
  interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
  external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
  1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
  Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
  enabling battery powered system design.

AM625 is the first device of the family. Add DT bindings for the same.

More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
36dafd8045 arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
750d8470cb arm: dts: k3-am654-r5-base-board: Fix the dt properties in usb0 instance
For dfu boot mode, the clocks property needs to be deleted and dr_mode
needs to be set to peripheral. Therefore, add the required fixes for the
same.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-06-10 13:37:32 -04:00
William Zhang
f8209d3051 arm: bcmbca: introduce the bcmbca architecture and 47622 SOC
This is the initial support for Broadcom's ARM-based 47622 SOC.

In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.

The SOC-specific code resides in arch/arm/mach-bcmbca/<soc> and board
related code is in board/broadcom/bcmba.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Signed-off-by: Anand Gore <anand.gore@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-06-10 13:37:32 -04:00
Vaishnav Achath
09d14d7f10 arm: k3: sysfw-loader: add hyperflash support
add support for loading system firmware from hyperflash.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Vaishnav Achath
8fceb0edf4 arm: dts: k3-j721e-common-proc-board: enable hyperflash mux sel GPIO
Add wkup_gpio pinmux setting which will be used for performing the
DT fixup for hbmc node according to mux selection state, on J721E
EVM, hypermux sel is tied to ·WKUP_GPIO0_8.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Vaishnav Achath
fa4f5aabae arm: dts: k3-j721e-common-proc-board-u-boot: enable HyperFlash in SPL
add u-boot,dm-spl pre-relocation property to enable hbmc in SPL.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Vaishnav Achath
30426492d3 arm: dts: k3-j721e-r5-common-proc-board: Add HyperFlash node
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Vaishnav Achath
cbd7790a69 arm: dts: k3-j721e-som-p0: Add HyperFlash node
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Vaishnav Achath
297daac43a arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
Add DT node for HyperBus Memory Controller and hbmc-mux in the
FSS. hbmc-am654 driver uses syscon_get_regmap() call which fails
with current compatible setting.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Pali Rohár
b62450cf22 serial: Replace CONFIG_DEBUG_UART_BASE by CONFIG_VAL(DEBUG_UART_BASE)
CONFIG_VAL(DEBUG_UART_BASE) expands to CONFIG_DEBUG_UART_BASE or
CONFIG_SPL_DEBUG_UART_BASE or CONFIG_TPL_DEBUG_UART_BASE and allows boards
to set different values for SPL, TPL and U-Boot Proper.

For ns16550 driver this support is there since commit d293759d55
("serial: ns16550: Add support for SPL_DEBUG_UART_BASE").

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-06 18:01:21 -04:00
Chris Packham
bfbd62f691 arm: mvebu: Use MVEBU_SPL_BOOT_DEVICE instead of SPL_BOOT_DEVICE
Update the way KWB_CFG_SEC_BOOT_DEV is determined to use
CONFIG_MVEBU_SPL_BOOT_DEVICE_{SPI,MMC} instead of
CONFIG_SPL_BOOT_DEVICE.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-06-06 12:09:29 -04:00
Tom Rini
dc22afb975 spl: Remove CONFIG_SPL_START_S_PATH and rework the logic behind it
In some cases, when we don't use CONFIG_SPL_FRAMEWORK nor are we on
PowerPC using their specific SPL/TPL framework, we need to specify the
start.S file to use for these typically very constrained systems.  Do
this within the Makefile logic, rather than introducing a string-based
CONFIG option, as this would get slightly complex to do in Kconfig for a
very limited number of users.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:29 -04:00
Tom Rini
eaf6ea6a1d Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h
- Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR
- Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack
  pointer directly, otherwise we use the common calculation.
- On some platforms that were using the standard calculation but did not
  set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them.
- On a small number of platforms that were not subtracting
  GENERATED_GBL_DATA_SIZE do so now via the standard calculation.
- CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most
  board config header files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:19 -04:00
Tom Rini
3b2979eefa mvebu: Use CONFIG_SPL_STACK + 4 directly for bootparam location
The definition of CONFIG_SPL_BOOTROM_SAVE is always a fixed
CONFIG_SPL_STACK + 4, while CONFIG_SPL_STACK is not constant.  This
change will make it clear where the location is still, once
CONFIG_SPL_STACK moves to Kconfig.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
3135ba642f arm: pxa: Remove CONFIG_CPU_PXA25X
There are no platforms that set this, remove the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
6074a536d5 ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage
A number of PowerPC platforms define this, for SPL.  To move this to
Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use
CONFIG_IS_ENABLED() to check for usage.  A number of layerscape
platforms bring this logic from PowerPC, but only need a small part of
it, for the fman driver.  Remove their unused portion at least.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
ca8a329a1b Convert CONFIG_SPL_PAD_TO et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_PAD_TO
   CONFIG_SPL_MAX_SIZE
   CONFIG_TPL_PAD_TO
   CONFIG_TPL_MAX_SIZE

Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the
existing places.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:06 -04:00
Tom Rini
12f613cf0e arm: omap2plus: Move CONFIG_SYS_PTV out of CONFIG namespace
This is always defined to 2, and referenced in two places.  Move the
define to <asm/omap_common.h> and make sure the code that uses this
includes that file.  Make <asm/arch-omap*/clock.h> not include that
file, as we don't need to be doing so.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:00 -04:00
Peng Fan
4230d68aa8 imx: imx8mq: default select CLK_IMX8MQ
Since the power domain driver default select CONFIG_CLK, so we will
meet lots failures without CLK_IMX8MQ, so default select it.

Fixes: commit 4eb82c2e56 ("imx: power-domain: Get rid of SMCCC dependency")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-03 11:15:24 -04:00
Andre Przywara
2b641211c5 armv8: Fix TCR 64-bit writes
The AArch64 TCR_ELx register is a 64-bit register, and many newer
architecture features use bits in the upper half. So far U-Boot was
igorant of those bits, trying to leave them alone.
However, in an effort to set bit 31 to 1, it failed doing so, because
the compiler sign-extended "1 << 31", so that all bits[63:31] got set.

Older ARMv8.0 cores don't define anything dangerous up there, but newer
architecture revisions do, and setting all those bits will end badly:
=================
$ qemu-system-aarch64 -cpu max ....
U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100)

DRAM:  1.5 GiB
=================  (hangs here)

Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all
upper bits stay at a safe 0 value. This means no more surprises when
U-Boot runs on a more capable CPU core.

Reported-by: Balaji Anandapadmanaban <Balaji.Anandapadmanaban@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Peter Collingbourne <pcc@google.com>
2022-06-03 11:15:24 -04:00
Georgi Vlaev
e7356f08e9 arm: dts: k3-am642-*: Mark the memory node with u-boot, dm-spl
Since commit dffdb1f8eb ("board: ti: am64x: Use fdt functions
for ram and bank init") ddr_init() and dram_bank_init() have
switched to fdtdec for getting the memory configuration from
the am64xx dts files instead of using hardcoded values. This
requires an accessible memory node in SPL as we already have
in k3-am642-r5-evm.dts.

Make the memory node accessible in A53 SPL for both am642-sk
and am642-evm and in am642-sk R5 SPL.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-26 10:32:26 -04:00
Tom Rini
661f540075 Xilinx changes for v2022.07-rc4
zynqmp:
 - Fix DP PLL configuration for zcu102/zcu106 and SOM
 - Fix split mode for starting R5s
 - DT fixes
 - Remove firmware node for mini configurations
 - Wire TEE for multi DTB fit image
 
 xilinx:
 - Handle board_get_usable_ram_top(0) properly
 
 phy:
 - Extend psgtr timeout
 
 mmc:
 - Fix mini configuration which misses zynqmp_pm_is_function_supported()
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Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc4

zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image

xilinx:
- Handle board_get_usable_ram_top(0) properly

phy:
- Extend psgtr timeout

mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
2022-05-25 09:50:08 -04:00
Tom Rini
7e0edcadb0 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The bulk of it is (finally!) some DT sync from the kernel. We refrained
from syncing one incompatible change, as this would spoil booting Linux
kernels before v5.13 with U-Boot's DT (via UEFI, for instance).
I test booted Linux v5.18 and v5.4 with that new DT on some boards, and
the headless peripherals (MMC, USB, Ethernet) seemed to work.
The rest are fixes:
- silencing missing clock warnings due to the new pinctrl driver
- fixing "UART0 on PortF", allowing UART access through the SD card pins
- add an F1C100s clock driver, to enable MMC support (SPI comes later)
- some cleanups for CONS_INDEX_n in Kconfig

Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and
OrangePi-Zero.
2022-05-24 23:29:00 -04:00
Michal Simek
594f692f49 xilinx: zynqmp: Wire tee for Multi DTB use cases
Fix TEE wiring when MULTI_DTB is selected.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8523a89d910ae6b8a9971b4e7b3bda89be3dc27.1652874088.git.michal.simek@amd.com
2022-05-24 08:44:24 +02:00
Samuel Holland
821fdfbba3 sunxi: Remove obsolete Kconfig selections
ARCH_SUNXI selects DM_SERIAL, so the condition can never be satisfied.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24 01:46:06 +01:00
Andre Przywara
e26ece267e sunxi: board: Fix UART PortF pinmux setup
When CONFIG_UART0_PORT_F is defined, we try to configure two PortF pins
(usually used for the SD card) as UART0. Some SoCs use the mux value of
3 for this, while others use 4.

The combination of Kconfig symbols we currently use was not quite right:
we mis-configure the A31, A64, H6 and H616.

Going through the list in the pinctrl driver, there are only a few older
SoCs that use a value of 4, so revert the #ifdef clause, and name those
explicitly, instead of the other way around.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24 01:45:47 +01:00
Humberto Naves
1b05136a6c arm: socfpga: Add the terasic de10-standard board
Use the de10-nano files as templates for the de10-standard board.
The files in qts directory are generated by quartus from the GHRD
design.

Signed-off-by: Humberto Naves <hsnaves@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2022-05-23 21:28:07 +02:00
Sai Pavan Boddu
2d25f63cc0 arm: gic_v2: Skip gic_init_secure when cpu is not in el3
This would prevent configuring non-secure regs in case gic security
extensions are not emulated in Qemu.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-23 09:33:10 -04:00
Tom Rini
004d30c786 u-boot-imx-20220523
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087
 
 Additionally to u-boot-imx20200520:
 
 - DH MX8MP
 - i.MX GPIO: reading GPIO when direction is output
 - Menlo i.MX53: switch to DM
 
 And from u-boot-imx20200520:
 
 - fix Verdin hang
 - add pca9450 regulator
 - conversion to DM_SERIAL
 - NAND block handling
 - fix crypto
 - enable cache on some boards
 - add ACC board (MX6)
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Merge tag 'u-boot-imx-20220523' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220523
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087

Additionally to u-boot-imx20200520:

- DH MX8MP
- i.MX GPIO: reading GPIO when direction is output
- Menlo i.MX53: switch to DM

And from u-boot-imx20200520:

- fix Verdin hang
- add pca9450 regulator
- conversion to DM_SERIAL
- NAND block handling
- fix crypto
- enable cache on some boards
- add ACC board (MX6)
2022-05-23 09:25:39 -04:00
Marek Vasut
4d573d5c98 ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-23 11:37:58 +02:00
Sergei Antonov
fdc55a6ba8 meson: axg: search dtb for meson-axg-usb-ctrl on board axg
USB controller for AXG is described as meson-axg-usb-ctrl,
see arch/arm/dts/meson-axg.dtsi
Look for that name instead of meson-gxl-usb-ctrl.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220509113618.2891126-1-saproj@gmail.com
2022-05-23 10:40:01 +02:00
Andre Przywara
d037e79f3a sunxi: F1C100s: update DT files from Linux
The initial U-Boot F1C100s port was based on the mainline kernel DT
files, which were quite basic and were missing the essential MMC and
SPI peripherals. While we could work around this in the SPL by
hardcoding the required information, this left U-Boot proper without SD
card or SPI flash support, so actual loading would require FEL boot.

Now the missing DT bits have been submitted and accepted in the kernel
tree, so lets sync back those files into U-Boot to enable MMC and
SPI, plus benefit from some fixes.

This is a verbatim copy of the .dts and .dtsi file from
linux-sunxi/dt-for-5.19[1], which have been part of linux-next for a
while as well.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/log/?h=sunxi/dt-for-5.19

Link: https://lore.kernel.org/linux-arm-kernel/20220317162349.739636-1-andre.przywara@arm.com/
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23 00:37:51 +01:00
Samuel Holland
ce00370b87 ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
Copy the devicetree source for the H6 SoC and all existing boards
from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.

This commit also adds the following new board devicetrees:
 - sun50i-h6-pine-h64-model-b.dts
 - sun50i-h6-tanix-tx6-mini.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
7710282334 ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
Copy the devicetree source for the A64 SoC and all existing boards
from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
7024755bd7 ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
Copy the devicetree for the R40/T3 SoC verbatim from the Linux v5.18-rc1
tag. None of the existing boards had any devicetree updates.

This commit adds the following new board devicetrees:
 - sun8i-r40-oka40i-c.dts
 - sun8i-t3-cqa3t-bv3.dts

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
94539ab840 ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This commit also adds the following new board devicetrees:
 - sun8i-s3-elimo-initium.dts
 - sun8i-v3-sl631-imx179.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
2c597855aa ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
Copy the devicetree source for the H2+/H3/H5 SoCs and all existing
boards from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

This commit also adds the following new board devicetree:
 - sun8i-h3-nanopi-r1.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
2d648e6982 ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
Copy the devicetree source for the A83T SoC and all existing boards
from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

As with the other SoCs, updates of note include adding detection GPIO
properties in the USB PHY nodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
6f97e028ef ARM: dts: sun9i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A80 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
70f24fa02b ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16
SoCs and all existing boards from the Linux v5.18-rc1 tag.

These changes are combined into one commit due to interdependencies:
 - The unit addresses were removed from bitbanged I2C buses, which
   drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts
   and sun6i-a31-colombus.dts.
 - The pinctrl nodes were renamed, including some used by the shared
   header sunxi-reference-design-tablet.dtsi.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts
to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.

This commit also adds the following new board devicetrees:
 - sun5i-a13-licheepi-one.dts
 - sun5i-a13-pocketbook-touch-lux-3.dts
 - sun5i-gr8-evb.dts
 - sun8i-a23-ippo-q8h-v1.2.dts
 - sun8i-a23-ippo-q8h-v5.dts
 - sun8i-a33-et-q8-v1.6.dts
 - sun8i-a33-ippo-q8h-v1.2.dts
 - sun8i-r16-nintendo-super-nes-classic.dts

As with the other SoCs, updates of note are conversion of GPIO pull-up
from pinconf to GPIO flags and renaming the detection GPIO properties in
the USB PHY nodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
4746694cba ARM: dts: sun4i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This commit also adds the following new board devicetree:
 - sun4i-a10-topwise-a721.dts

While this update should not impact any existing U-Boot functionality,
the changes to the USB PHY detection GPIO properties are needed to
convert that driver to use the DM GPIO framework.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
0605ac405c ARM: dts: sun7i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A20 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This commit also adds the following new board devicetrees:
 - sun7i-a20-haoyu-marsboard.dts
 - sun7i-a20-linutronix-testbox-v2.dts
 - sun7i-a20-olinuxino-lime-emmc.dts

This update includes changes to the USB PHY detection GPIO properties
which are needed to convert that driver to use the DM GPIO framework.

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fix Mele M5 U-Boot only DT]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23 00:37:50 +01:00
Samuel Holland
91407bbd41 ARM: dts: sunxi: Remove unused devicetree headers
These files are not included anywhere and do not exist in the Linux
devicetree source.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:50 +01:00
Philip Oberfichtner
c5a46943a2 ARM: dts: imx: Configure FEC for iMX6QDL DRC02
Add a u-boot dtsi for configuring the FEC node of the DH DRC02.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
84d9ce5607 ARM: dts: imx: Configure FEC for iMX6QDL picoITX
Add a u-boot dtsi for configuring the FEC node of the DH picoITX.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
dcb59a1306 ARM: dts: imx: Simplify fec node for iMX6QDL DHCOM boards
Firstly the FEC can now use the regulator reg_eth_vio from
imx6qdl-dhcom-som.dtsi instead of defining its own.

Secondly the &fec node is moved to the more generic SoM device tree
file, because it can be used by multiple boards.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
874c76867a ARM: dts: imx: Migrate iMX6QDL picoITX DTs from Linux
Migrate DH picoITX device trees from Linux commit 42226c989789
(tag v5.18-rc7). No changes have been made, the DTs are exact copies.
Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
45964cbf3c ARM: dts: imx: Migrate iMX6QDL DRC02 DTs from Linux
Migrate DH DRC02 device trees from Linux commit 42226c989789
(tag v5.18-rc7). No changes have been made, the DTs are exact copies.
Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
e1e0d9ab9f ARM: imx6: Fix broken DT path in DH board file
In the DH electronics iMX6 board file fix the outdated eeprom path by
using a DT label instead.

The label has been newly created for all iMX6QDL DHCOM boards.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
55d1537c5b bosch: Add initial board support for ACC
The Bosch ACC (Air Center Control) Board is based on the i.MX6D.

The device tree is copied from Linux, see [1]. The only difference
compared to the Linux DT is the removal of usbphynop properties. They are
defined in the Linux version of imx6qdl.dtsi, but not in the u-boot
version.

[1] Commit 6192cf8ac082 from
    git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Michael Trimarchi
37a7c374a6 arm: mach-imx: cmd_nandbcb fix bad block handling
The badblock should be skipped properly in reading and writing.
Fix the logic. The bcb struct is written, skipping the bad block,
so we need to read using the same logic. This was tested create
bad block in the area and then flash it and read it back.

Acked-by: Han Xu <han.xu@nxp.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:48 +02:00
Gaurav Jain
cad77280c3 i.MX8ULP: add display_ele_fw_version api
implement get f/w version api.
print ele f/w version in spl.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
2022-05-20 12:36:47 +02:00
Ye Li
cda8f87349 caam: Fix crash in case caam_jr_probe failed
If probing caam_jr returns failure, the variable "dev" will not be
initialized, so we can't use dev->name for the error print.
Otherwise it will cause crash.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-20 12:36:47 +02:00
Peng Fan
a38ed61643 imx: imx8mp_evk: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
ba06ea8991 imx: imx8mm_evk: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
6d5cc90670 imx: imx8mn_evk: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
597514e738 imx: imx8mq-phanbell: enable CONFIG_DM_SERIAL
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
1d8c0c2d7b imx: imx8mq-pico: enable CONFIG_DM_SERIAL
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
23df340f32 imx: imx8mq-cm: enable CONFIG_DM_SERIAL
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
56f3888b43 imx: dts: move common changes to imx8mq-u-boot.dtsi
Move some common changes to imx8mq-u-boot.dtsi, so others could reuse it

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Tim Harvey
0cba71c1eb board: gateworks: gw_ventana: add support for GPY111 PHY
The MaxLinear GPY111 PHY is being used on some boards due to part
availability. Add support for this PHY which requires a longer reset
post-delay and RGMII delay configuration.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Peng Fan
a1d675ac77 imx: imx8m: drop uneeded check
All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
waste cpu cycles.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2022-05-20 09:30:28 +02:00
Peng Fan
5dd9db8f7d imx: imx8m: add rproc_att
With rpoc_att, bootaux able to kick elf file for M core

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Peng Fan
40153df63a imx: bootaux: get stack from elf file
To i.MX8, M core stack is pre-coded in source code, so need to get it
before kicking M core. The stack pointer is stored in the first word of
the first PT_LOAD section __isr_vector. So use a num to index the
section loading.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Peng Fan
fd60a87e75 imx: bootaux: add missing newline
Add missing newline

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Peng Fan
56c2dbdaba imx: bootaux: cleanup code
Use if (CONFIG_IS_ENABLED()) to make code cleaner
Enable elf support for i.MX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Rasmus Villemoes
290ffe5788 imx8m: fix reading of DDR4 MR registers
I was trying to employ lpddr4_mr_read() to something similar to what
the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM
type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c
differs from the private one used by that board in how it extracts the
byte value, and I was only getting zeroes. Adding a bit of debug
printf'ing gives me

 tmp = 0x00ffff00
 tmp = 0x00070700
 tmp = 0x00000000
 tmp = 0x00101000

and indeed I was expecting a (combined) value of 0xff070010 (0xff
being Manufacturer ID for Micron). I can't find any documentation that
says how the values are supposed to be read, but clearly the iot-gate
definition is the right one, both for its use case as well as my
imx8mp-based board.

So lift the private definition of lpddr4_mr_read() from the
imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration
in the ddr.h header where e.g. get_trained_CDD() is already declared.

This has only been compile-tested for the imx8mm-cl-iot-gate
board (since I don't have the hardware), but since I've merely moved
its definition of lpddr4_mr_read(), I'd be surprised if it changed
anything for that board.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00
Marek Vasut
c329f9349b ARM: imx: imx31: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
be23774ed1 ARM: imx: imx27: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
52b6b480db ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
ff04a0944d ARM: dts: imx: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is
capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz
to guarantee this I2C device can work correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-19 21:39:36 +02:00
Fabio Estevam
d175982c20 imx8mn/8mp: Allow booting via USB
When trying to boot via USB on i.MX8MN it is necessary to specify
the U-Boot environment location, otherwise the boot process simply
hangs.

Specify the environment location when booting from USB.

Tested on a imx8mn-evk.

Suggested-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>
2022-05-19 21:39:36 +02:00
Marek Vasut
0adf10a87b ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96
The Avenger96 board comes in multiple regulator configurations.
 - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on
   boot and contains extra Enpirion EP53A8LQI DCDC converter which
   supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power.
 - rev.200L have Buck3 preconfigured to 1V8 operation and have no
   Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3.

Configure the Buck3 voltage on this board per PMIC NVM settings and
update buck3 voltage limits in DT passed to OS before booting OS to
prevent potential hardware damage.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-19 18:48:50 +02:00
Michal Simek
11ed38f5dc arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/db66a4bb501183ffbd033da4dd263afdb214f8ec.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
d5b9b22f7b arm64: zynqmp: Add linux,code for fwuen button
BTN_MISC looks like the most reasonable option for this button.
Button is used by firmware to indicate (after reset, power up) that user
wants to do firmware upgrade via firmware update utility.
For bootloader or OS is this just user button which is worth to have it
mapped.
Also button can be used as a wakeup source and pressing it for more time
can generate more chars that's why also adding wakeup-source and autorepeat
properties.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/7f6d627473632c3c3036ec9f6aaa36e00f4615e2.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
e4f1d2881e arm64: zynqmp: Add PHY description for SGMII on vck190 SC
SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8ad8d0c2fc9690cc90f95feddf87b0e94a685a43.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
T Karthik Reddy
725badc5a2 Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"
This reverts commit 50a6bd000f.

As zynqmp mini emmc does not rely on firmware, remove firmware related
device tree modes from zynqmp mini emmc dts files.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e69b30d82b0307c563fe72630d9172e53964aeda.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
dda356db64 arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM
There are couple of IPs which are enabled in origin HW design which are
missing in SOM dt. Add them to match default setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/901401beacbea5931fc18cde20c157e5978a7023.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Vishal Patel
07f8e78af0 arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property
Add pwm-fan node to control fan through hwmon and change
pwm-cells property to 3 to allow fancontrol utility to
function correctly.

Signed-off-by: Vishal Patel <vishal.patel@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21b4dfce3e45136a468974ea3dedca03320e27b8.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
d59fac2f3f arm64: zynqmp: Add power domain description for PL
PL has own power domain which is not described in DT. That's why add it
there by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b38e2ea95dab434bc007f9ed6c438c68149744bf.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
234f8be568 arm64: zynqmp: Fix opp-table-cpu
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement.

The same change was done in Linux by commit c6d4a8977598 ("ARM: tegra:
Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a
("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64:
dts: qcom: qcs404: Rename CPU and CPR OPP tables").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a1176349448df35127dbac15c1eeb2229505bae7.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
e7b390024c arm64: zynqmp: Add gpio labels for modepin
Using labels helps with better identifications of chips.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15b0f68077fb3c86d438caf8562de87367361c60.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Piyush Mehta
a4180c3696 arm64: zynqmp: Add mode-pin GPIO controller DT node
Add mode-pin GPIO controller DT node in zynqmp.dtsi and also setup default
reset-gpios property for usb which is default Xilinx setup.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f2a1f6f541c41075ea36062857031bfc28d6d303.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Amit Kumar Mahapatra
6e38e2ea79 arm64: zynqmp: Set qspi tx-buswidth to 4
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Neal Frager
67bdaa0165 arm64: zynqmp: Fix split mode reset functionality
This patch fixes two issues in the set_r5_reset function.

1. When in split mode, the lpd_amba_rst bit should only be set when
both r5 cpu cores are in reset. Otherwise, if one r5 core is still
running, setting the lpd_amba_rst bit will cause an error for the
running core. The set_r5_reset function has been modified to check
if the other r5 core is still running before setting the lpd_amba_rst
bit.

2. The cpu_disable function was always assuming that the r5 cores
are in split mode when resetting either core 4 or 5. This is
incorrect for lockstep functionality. This patch adds a function
check_r5_mode to handle the cpu_disable function correctly for
the r5 cores by checking the mode and handling the reset appropriately.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d99cbd7f2394ac055ef27457298f554ff0747ba7.1651648344.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Pali Rohár
5bb2c550b1 arm: mvebu: Move internal registers in arch_very_early_init() function
Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
needs to be done very early, prior calling any function which may touch
internal registers, like debug_uart_init().

So do it earlier in arch_very_early_init() instead of arch_cpu_init().

Movement is done in proper U-Boot, not in SPL. SPL may return to bootrom
and bootrom requires internal registers at (old) expected location.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:34 +02:00
Pali Rohár
948da7773e arm: Add new config option ARCH_VERY_EARLY_INIT
When this option is set then ARM _main() function would call
arch_very_early_init() function at the beginning. It would be before
calling any other functions like debug_uart_init() and also before
initializing C runtime environment.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:33 +02:00
Chris Packham
1001a0ab46 arm: mvebu: Remove unused ARMADA_64BIT
Nothing selects ARMADA_64BIT. Instead the 64-bit SoCs just select ARM64
directly. Remove the unused config item.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:33 +02:00
Tom Rini
21e25992c8 Add new STM32 MCU boards and Documentation
STM32 programmer improvements
 video: support several LTDC HW versions and fix data enable polarity
 board: fix stboard error message, consider USB cable connected when boot device is USB
 configs: stm32mp1: set console variable for extlinux.conf
 configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
 ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
 phy: stm32-usbphyc: Add DT phy tuning support
 arm: dts: stm32mp15: alignment with v5.18
 ram: Conditionally enable ASR
 mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
 configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
 ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
 pinctrl: stm32: rework GPIO holes management
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Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
2022-05-10 15:28:02 -04:00
Patrice Chotard
35a15bc12e configs: stm32f746-disco: Migrate SPL flags to defconfig
Migrate SPL flags to stm32f746-disco_spl_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Marek Vasut
6d4619f68c ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.

The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Marek Vasut
d6ae183965 stm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
The SoC seems to lose the values of MCUDIVR, PLL3CR, PLL4CR, RCC_MSSCKSELR
during suspend/resume cycle, cache them and reinstate their values on resume.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Patrick Delaunay
189ec2fee6 arm: dts: stm32mp15: alignment with v5.18
Device tree alignment with Linux kernel v5.18-rc2:
- ARM: dts: stm32: Add support for the emtrion emSBC-Argon
  (only the pincontrol part)
- ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
- ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on
  stm32mp157
- ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151
- ARM: dts: stm32: keep uart4 behavior on *
- ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Patrick Delaunay
655af9aa9c ARM: stm32mp: correctly handle Silicon revision
Handle correctly the silicon revision = REV_ID[15:0] of Device Version
and the associated device marking, A to Z on STMicroelectronics STM32MP
SOCs.

This patch prepare the introduction of next STM32MP family,
with STM32MP13x Rev.Z for REV_ID = 1.1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
6a69eaf6f4 ARM: stm32mp: skip ft_system_setup when the soc node is absent
The function ft_system_setup shouldn't return an error when the
/soc node is absent in the provided device tree but just skip the
updates.

This patch solves an issue when the U-Boot pytest is executed on board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
a9fed5aac5 stm32mp: stm32prog: handle flashlayout without STM32 image header
Accept flashlayout without header in alternate 0, to simplify
the support of stm32prog command with dfu-util.

By default the flashlayout file size is the size of the received binary,
provided with the offset in the DFU alternate.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
152576a598 stm32mp: stm32prog: handle U-Boot script in flashlayout alternate
Update the stm32prog command to allow the reception of U-Boot script in
the FlashLayout alternate during the first USB enumeration.

This patch is aligned with the last TF-A behavior: the Flashlayout
is now loaded by U-Boot; it is no more present at STM32_DDR_BASE when
the stm32prog is launched after a serial boot, on UART or on USB.

The received script must be a U-Boot legacy image, no more need to add
a stm32image header.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
7f1121a85a stm32mp: stm32prog: handle interruption during the first enumeration
When an interruption is received during the first USB enumeration
used to received the FlashLayout, with handle ctrl-c, the second
enumeration is not needed and the result for stm32prog_usb_loop
is false (reset is not needed).

This patch avoids the need of a second ctrl to interrupt the command
stm32prog.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
2a4fe0ee48 stm32mp: stm32prog: add support of UUID for FIP partition
Add support of UUID for FIP parttion, required by Firmware update
support in TF-A:
- UUID TYPE for FIP partition: 19d5df83-11b0-457b-be2c-7559c13142a5
- "fip-a" partition UUID: 4fd84c93-54ef-463f-a7ef-ae25ff887087
- "fip-b" partition UUID: 09c54952-d5bf-45af-acee-335303766fb3

This check is done with a new partition type "FIP" associated
at the FIP UUID.

The A/B partition UUID is detected by the partition name:
"fip-a", "fip-b".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
49d0ecb123 stm32mp: stm32prog: add support of STM32IMAGE version 2
Add support of new header for the STM32IMAGE version V2
in command stm32prog command for STM32MP13x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
e82ab4c890 stm32mp: stm32prog: add TEE support in stm32prog command
When OP-TEE is used, the SMC for BSEC management are not
available and the PTA provisioning for OTP must be used.

U-Boot opens the session to this PTA and use it for OTP
access.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
72450b4b35 stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP
Add a configuration flag CONFIG_CMD_STM32PROG_OTP to enable the support of
OTP update in stm32prog command.

This new configuration allows to deactivate this feature for security reason
and it is a preliminary step for support of OPT update with the OP-TEE
provisioning TA.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
d983e503c4 stm32mp: stm32prog: fix comment
Fix "partition" in comment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Neil Armstrong
28a4c31134 ARM: dts: k3-am642-sk-u-boot: add PMIC node
The E4 revision of the AM64 SKEVM embeds a TPS65219 PMIC,
this adds the PMIC node with the required regulators voltages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-09 13:40:24 -04:00
Gireesh Hiremath
e61374b7af ARM: dts: am335x: guardian: switch to AM33XX_PADCONF
switch the pin definitions from AM33XX_IOPAD to AM33XX_PADCONF macro

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-09 13:40:23 -04:00
Jim Liu
84335544ea arm: nuvoton: Add support for Nuvoton NPCM750 BMC
Add basic support for the Nuvoton NPCM750 EVB (Poleg).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-05-05 09:28:47 -04:00
Marek Behún
0ce0feb046 arm: mvebu: turris_mox: Use DM registered MDIO
In order to be able to get rid of the non-DM MDIO bus registered in
mvneta driver, start using the DM registered one in Turris MOX board
code.

This also allows us to drop the hack introduced in MOX' -u-boot.dtsi
file.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-04 07:05:51 +02:00
Tony Dinh
dbd2a382c1 arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet
The Zyxel NSA310s board has the network chip Marvell Alaska 88E1318S.
Use uclass mvgbe and the compatible driver M88E1310 driver to bring
up Ethernet.

- Use uclass mvgbe to bring up the network. And remove ad-hoc code.
- Remove CONFIG_RESET_PHY_R.
- Enable CONFIG_PHY_MARVELL to properly configure the network.
- Add phy mode RGMII to kirkwood-nsa310s.dts
- Miscellaneous changes: Move constants to .c file and remove header file
board/zyxel/nsa310s/nsa310s.h, add support for large USB and SATA HDDs,
use BIT macro, add/cleanup comments, and cosmetic changes.

Note that this patch is depended on the following patch:
https://patchwork.ozlabs.org/project/uboot/patch/20220412201820.10291-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2022-05-02 07:47:26 +02:00
Tom Rini
8b2b125e95 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
fsl-qoriq: Fixes and updates on fsl-layerscape
mpc85xx: fixes and code cleanup
2022-04-27 09:19:41 -04:00
Tom Rini
24df831cd4 - Add AXG support for SARADC, including minimal ao-clk driver
- Update Amlogic documentation for Matrix & Jethub D1
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Merge tag 'u-boot-amlogic-20220427' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- Add AXG support for SARADC, including minimal ao-clk driver
- Update Amlogic documentation for Matrix & Jethub D1
2022-04-27 09:19:17 -04:00
Stephen Carlson
3b06577ab4 armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs
NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES)
that can be configured for the application. Interfaces not used by the
application can be set to protocol 0 to turn them off and save power, but
U-Boot would emit a warning that 0 was invalid for a SERDES protocol on
boot. Replace the warning text with a notice that the SERDES is disabled.

Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-26 17:13:57 +05:30