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https://github.com/AsahiLinux/u-boot
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imx: imx9: Support booting m33 from Acore
Add bootaux command to support on-demand booting M33 from u-boot. It kicks M33 via ATF by "bootaux 0x201e0000 0" Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
parent
a8753afed7
commit
c383379f25
4 changed files with 147 additions and 1 deletions
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@ -5,3 +5,7 @@
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obj-y += lowlevel_init.o
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obj-y += soc.o clock.o clock_root.o trdc.o
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obj-$(CONFIG_AHAB_BOOT) += ahab.o
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#ifndef CONFIG_SPL_BUILD
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obj-y += imx_bootaux.o
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#endif
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133
arch/arm/mach-imx/imx9/imx_bootaux.c
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133
arch/arm/mach-imx/imx9/imx_bootaux.c
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@ -0,0 +1,133 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <log.h>
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#include <imx_sip.h>
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#include <linux/arm-smccc.h>
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int arch_auxiliary_core_check_up(u32 core_id)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
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0, 0, 0, 0, &res);
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return res.a0;
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}
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int arch_auxiliary_core_down(u32 core_id)
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{
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struct arm_smccc_res res;
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printf("## Stopping auxiliary core\n");
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
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0, 0, 0, 0, &res);
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return 0;
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}
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int arch_auxiliary_core_up(u32 core_id, ulong addr)
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{
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struct arm_smccc_res res;
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u32 stack, pc;
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if (!addr)
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return -EINVAL;
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stack = *(u32 *)addr;
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pc = *(u32 *)(addr + 4);
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printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc);
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arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
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0, 0, 0, 0, &res);
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return 0;
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}
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/*
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* To i.MX6SX and i.MX7D, the image supported by bootaux needs
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* the reset vector at the head for the image, with SP and PC
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* as the first two words.
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*
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* Per the cortex-M reference manual, the reset vector of M4/M7 needs
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* to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
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* of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
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* vector with getting the PC and SP from image and filling them to
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* TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
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* The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
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* accessing the M4/M7 TCMUL/IDTCM.
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*/
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static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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ulong addr;
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int ret, up;
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u32 core = 0;
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u32 stop = 0;
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if (argc < 2)
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return CMD_RET_USAGE;
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if (argc > 2)
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core = simple_strtoul(argv[2], NULL, 10);
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if (argc > 3)
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stop = simple_strtoul(argv[3], NULL, 10);
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up = arch_auxiliary_core_check_up(core);
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if (up) {
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printf("## Auxiliary core is already up\n");
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return CMD_RET_SUCCESS;
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}
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addr = simple_strtoul(argv[1], NULL, 16);
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if (!addr)
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return CMD_RET_FAILURE;
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ret = arch_auxiliary_core_up(core, addr);
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if (ret)
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return CMD_RET_FAILURE;
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return CMD_RET_SUCCESS;
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}
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static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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int ret, up;
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up = arch_auxiliary_core_check_up(0);
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if (!up) {
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printf("## Auxiliary core is already down\n");
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return CMD_RET_SUCCESS;
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}
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ret = arch_auxiliary_core_down(0);
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if (ret)
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return CMD_RET_FAILURE;
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return CMD_RET_SUCCESS;
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}
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U_BOOT_CMD(
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stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux,
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"Stop auxiliary core",
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"<address> [<core>]\n"
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" - start auxiliary core [<core>] (default 0),\n"
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" at address <address>\n"
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);
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U_BOOT_CMD(
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bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
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"Start auxiliary core",
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"<address> [<core>]\n"
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" - start auxiliary core [<core>] (default 0),\n"
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" at address <address>\n"
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);
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@ -131,6 +131,14 @@ static struct mm_region imx93_mem_map[] = {
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.size = 0x100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* TCM */
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.virt = 0x201c0000UL,
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.phys = 0x201c0000UL,
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.size = 0x80000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* OCRAM */
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.virt = 0x20480000UL,
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@ -380,7 +388,7 @@ void soc_power_init(void)
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disable_isolation();
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}
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static bool m33_is_rom_kicked(void)
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bool m33_is_rom_kicked(void)
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{
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struct blk_ctrl_s_aonmix_regs *s_regs =
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(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
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@ -15,5 +15,6 @@
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#define IMX_SIP_SRC 0xC2000005
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#define IMX_SIP_SRC_M4_START 0x00
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#define IMX_SIP_SRC_M4_STARTED 0x01
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#define IMX_SIP_SRC_M4_STOP 0x02
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#endif
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