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imx7s/d: synchronise device trees with linux

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Synchronise device tree with linux-next next-20220708.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-07-21 15:27:34 +02:00 committed by Stefano Babic
parent 868b5cb74e
commit 2f96d4dd95
11 changed files with 1021 additions and 296 deletions
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6
arch/arm/dts/imx7d-pico-hobbit.dts
View file

@ -31,7 +31,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -41,7 +41,7 @@
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};
@ -102,4 +102,4 @@
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
>;
};
};
};

6
arch/arm/dts/imx7d-pico-pi.dts
View file

@ -31,7 +31,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -41,7 +41,7 @@
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};
@ -90,4 +90,4 @@
>;
};
};
};

103
arch/arm/dts/imx7d-pico.dtsi
View file

@ -5,15 +5,44 @@
/dts-v1/;
#include "imx7d.dtsi"
#include "imx7d-pico-u-boot.dtsi"
/ {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 50000 0>;
brightness-levels = <0 36 72 108 144 180 216 255>;
default-brightness-level = <6>;
};
/* Will be filled by the bootloader */
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
panel {
compatible = "vxt,vl050-8048nt-c01";
backlight = <&backlight>;
power-supply = <&reg_lcd_3v3>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
reg_lcd_3v3: regulator-lcd-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_wlreg_on: regulator-wlreg_on {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -231,6 +260,18 @@
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
@ -261,6 +302,8 @@
};
&pwm4 { /* Backlight */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
@ -308,7 +351,7 @@
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
bus-width = <4>;
tuning-step = <2>;
fsl,tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
wakeup-source;
no-1-8-v;
@ -389,7 +432,7 @@
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
>;
};
@ -414,21 +457,61 @@
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78
MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14
>;
};
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
>;
};
pinctrl_pwm2: pwm2 {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
>;
};
pinctrl_pwm3: pwm3 {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
>;
};
pinctrl_pwm4: pwm4grp{
fsl,pins = <
MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f
>;
};
@ -578,9 +661,15 @@
>;
};
pinctrl_reg_lcdreg_on: reglcdongrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};
};

14
arch/arm/dts/imx7d-pinfunc.h
View file

@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX7D_PINFUNC_H
@ -592,11 +588,11 @@
#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2
#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0
#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0
#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0
#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0
#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0
#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1
#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0
#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3
#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0
@ -1112,13 +1108,13 @@
#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0
#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0
#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0
#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0
#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1
#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0
#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0
#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0
#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0
#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0
#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0
#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1
#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0
#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0
#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0

120
arch/arm/dts/imx7d-sdb.dts
View file

@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.
/dts-v1/;
@ -46,7 +45,7 @@
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
@ -147,6 +146,31 @@
};
};
};
sound {
compatible = "fsl,imx7d-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
audio-cpu = <&sai1>;
audio-codec = <&codec>;
hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "AMIC",
"AMIC", "MICB";
};
sound-hdmi {
compatible = "fsl,imx-audio-sii902x";
model = "sii902x-audio";
audio-cpu = <&sai3>;
hdmi-out;
};
};
&adc1 {
@ -163,17 +187,21 @@
cpu-supply = <&sw1a_reg>;
};
&cpu1 {
cpu-supply = <&sw1a_reg>;
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
tsc2046@0 {
compatible = "ti,tsc2046";
reg = <0>;
spi-max-frequency = <1000000>;
pinctrl-names ="default";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2046_pendown>;
interrupt-parent = <&gpio2>;
interrupts = <29 0>;
@ -357,9 +385,16 @@
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
clock-names = "mclk";
wlf,shared-lrclk;
wlf,hp-cfg = <2 2 3>;
wlf,gpio-cfg = <1 3>;
assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
<&clks IMX7D_PLL_AUDIO_POST_DIV>,
<&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <884736000>, <12288000>;
};
};
@ -375,6 +410,41 @@
};
};
&pcie {
reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
&reg_1p0d {
vin-supply = <&sw2_reg>;
};
&reg_1p2 {
vin-supply = <&sw2_reg>;
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
<&clks IMX7D_PLL_AUDIO_POST_DIV>,
<&clks IMX7D_SAI1_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <884736000>, <36864000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
<&clks IMX7D_PLL_AUDIO_POST_DIV>,
<&clks IMX7D_SAI3_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <884736000>, <36864000>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -534,6 +604,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
>;
};
@ -599,6 +670,33 @@
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
>;
};
pinctrl_spi4: spi4grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
@ -760,4 +858,10 @@
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
>;
};
pinctrl_sai3_mclk: sai3grp_mclk {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
>;
};
};

297
arch/arm/dts/imx7d-smegw01.dts
View file

@ -5,6 +5,7 @@
// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx7d.dtsi"
/ {
@ -14,6 +15,9 @@
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc3;
mmc2 = &usdhc2;
rtc0 = &i2c_rtc;
rtc1 = &snvs_rtc;
};
chosen {
@ -24,6 +28,79 @@
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reg_lte_on: regulator-lte-on {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lte_on>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "lte_on";
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_lte_nreset: regulator-lte-nreset {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lte_nreset>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "LTE_nReset";
gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
regulator-name = "wifi_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_wlan_rfkill: regulator-wlan-rfkill {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-2 = <&pinctrl_rfkill>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "wlan_rfkill";
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usbotg_vbus: regulator-usbotg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
sram@0 {
compatible = "microchip,48l640";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <16000000>;
};
};
&fec1 {
@ -43,28 +120,109 @@
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
ethphy1: ethernet-phy@2 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 =<&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
i2c_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_int>;
reg = <0x52>;
interrupt-parent = <&gpio2>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
dr_mode = "otg";
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
enable-sdio-wakeup;
wakeup-source;
keep-power-in-suspend;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
vmmc-supply = <&reg_wifi>;
wakeup-source;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@ -76,13 +234,10 @@
bus-width = <8>;
fsl,tuning-step = <1>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
sd-uhs-ddr50;
sd-uhs-sdr104;
status = "okay";
};
@ -94,6 +249,15 @@
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
@ -102,7 +266,7 @@
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
@ -113,6 +277,69 @@
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
>;
};
pinctrl_lte_on: lteongrp {
fsl,pins = <
MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
>;
};
pinctrl_lte_nreset: ltenresetgrp {
fsl,pins = <
MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
>;
};
pinctrl_rfkill: rfkillrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
@ -120,7 +347,38 @@
>;
};
pinctrl_usdhc1: usdhc1 {
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
>;
};
pinctrl_usbotg1_lpsr: usbotg1 {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
>;
};
pinctrl_usbotg1_pwr: usbotg1-pwr {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
>;
};
pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
@ -132,7 +390,19 @@
>;
};
pinctrl_usdhc3: usdhc3 {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
@ -148,7 +418,7 @@
>;
};
pinctrl_usdhc3_100mhz: usdhc3_100mhz {
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
@ -164,7 +434,7 @@
>;
};
pinctrl_usdhc3_200mhz: usdhc3_200mhz {
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
@ -179,6 +449,13 @@
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
>;
};
};
&iomuxc_lpsr {

211
arch/arm/dts/imx7d.dtsi
View file

@ -1,60 +1,25 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2016 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Freescale Semiconductor, Inc.
// Copyright 2016 Toradex AG
#include "imx7s.dtsi"
#include <dt-bindings/reset/imx7-reset.h>
/ {
aliases {
ethernet1 = &fec2;
usb0 = &usbotg1;
usb1 = &usbotg2;
usb2 = &usbh;
};
cpus {
cpu0: cpu@0 {
operating-points = <
/* KHz uV */
996000 1075000
792000 975000
>;
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
nvmem-cells = <&fuse_grade>;
nvmem-cell-names = "speed_grade";
};
cpu1: cpu@1 {
@ -62,10 +27,58 @@
device_type = "cpu";
reg = <1>;
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_sleep_wait>;
};
};
soc {
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
cpu0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xd>, <0x7>;
opp-suspend;
};
opp-996000000 {
opp-hz = /bits/ 64 <996000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xc>, <0x7>;
opp-suspend;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0x8>, <0x3>;
opp-suspend;
};
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_PHY2_CLK>;
clock-names = "main_clk";
#phy-cells = <0>;
};
soc: soc {
etm@3007d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007d000 0x1000>;
@ -80,24 +93,77 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x31001000 0x1000>,
<0x31002000 0x2000>,
<0x31004000 0x2000>,
<0x31006000 0x2000>;
};
pcie: pcie@33800000 {
compatible = "fsl,imx7d-pcie";
reg = <0x33800000 0x4000>,
<0x4ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
<0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
/*
* Reference manual lists pci irqs incorrectly
* Real hardware ordering is same as imx6: D+MSI, C, B, A
*/
interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
<&clks IMX7D_PCIE_PHY_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
fsl,max-link-speed = <2>;
power-domains = <&pgc_pcie_phy>;
resets = <&src IMX7_RESET_PCIEPHY>,
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
};
};
};
&aips2 {
epdc: epdc@306f0000 {
compatible = "fsl,imx7d-epdc";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x306f0000 0x10000>;
clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
clock-names = "epdc_axi", "epdc_pix";
epdc-ram = <&gpr 0x4 30>;
status = "disabled";
pcie_phy: pcie-phy@306d0000 {
compatible = "fsl,imx7d-pcie-phy";
reg = <0x306d0000 0x10000>;
status = "disabled";
};
};
@ -119,36 +185,35 @@
reg = <0x30b20200 0x200>;
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_PHY2_CLK>;
clock-names = "main_clk";
};
fec2: ethernet@30bf0000 {
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
reg = <0x30bf0000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
interrupt-names = "int0", "int1", "int2", "pps";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
};
&ca_funnel_ports {
&ca_funnel_in_ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&etm1_out_port>;
};
};

70
arch/arm/dts/imx7s-warp.dts
View file

@ -10,10 +10,11 @@
#include "imx7s.dtsi"
/ {
model = "Warp i.MX7 Board";
compatible = "warp,imx7s-warp", "fsl,imx7s";
model = "Element14 Warp i.MX7 Board";
compatible = "element14,imx7s-warp", "fsl,imx7s";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
@ -54,6 +55,14 @@
regulator-always-on;
};
reg_peri_3p15v: regulator-peri-3p15v {
compatible = "regulator-fixed";
regulator-name = "peri_3p15v_reg";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
@ -66,7 +75,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -76,6 +85,10 @@
assigned-clock-rates = <884736000>;
};
&csi {
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@ -120,6 +133,8 @@
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
@ -177,6 +192,27 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov2680: camera@36 {
compatible = "ovti,ov2680";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov2680>;
reg = <0x36>;
clocks = <&osc>;
clock-names = "xvclk";
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
DOVDD-supply = <&sw2_reg>;
DVDD-supply = <&sw2_reg>;
AVDD-supply = <&reg_peri_3p15v>;
port {
ov2680_to_mipi: endpoint {
remote-endpoint = <&mipi_from_sensor>;
clock-lanes = <0>;
data-lanes = <1>;
};
};
};
};
&i2c3 {
@ -196,7 +232,7 @@
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
VDDA-supply = <&vgen4_reg>;
@ -210,6 +246,22 @@
};
};
&mipi_csi {
clock-frequency = <166000000>;
status = "okay";
ports {
port@0 {
reg = <0>;
mipi_from_sensor: endpoint {
remote-endpoint = <&ov2680_to_mipi>;
data-lanes = <1>;
};
};
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
@ -276,6 +328,10 @@
status = "okay";
};
&video_mux {
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
@ -330,6 +386,12 @@
>;
};
pinctrl_ov2680: ov2660grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f

472
arch/arm/dts/imx7s.dtsi
View file

@ -1,51 +1,14 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2016 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Freescale Semiconductor, Inc.
// Copyright 2016 Toradex AG
#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/imx7-reset.h>
#include "imx7d-pinfunc.h"
/ {
@ -55,10 +18,8 @@
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; };
aliases {
gpio0 = &gpio1;
@ -82,18 +43,31 @@
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
spi0 = &qspi1;
spi1 = &ecspi1;
spi2 = &ecspi2;
spi3 = &ecspi3;
spi4 = &ecspi4;
ethernet0 = &fec1;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usb0 = &usbotg1;
usb1 = &usbh;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_sleep_wait: cpu-sleep-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <50>;
min-residency-us = <1000>;
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
@ -101,6 +75,23 @@
clock-frequency = <792000000>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>;
cpu-idle-states = <&cpu_sleep_wait>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
nvmem-cells = <&fuse_grade>;
nvmem-cell-names = "speed_grade";
};
};
cpu0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xf>, <0xf>;
};
};
@ -129,6 +120,7 @@
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
clock-names = "main_clk";
power-domains = <&pgc_hsic_phy>;
#phy-cells = <0>;
};
@ -144,9 +136,9 @@
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell"
*/
compatible = "arm,coresight-replicator";
compatible = "arm,coresight-static-replicator";
ports {
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
@ -163,12 +155,11 @@
remote-endpoint = <&etr_in_port>;
};
};
};
/* replicator input port */
port@2 {
reg = <0>;
in-ports {
port {
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
};
};
@ -177,11 +168,12 @@
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc {
@ -192,33 +184,28 @@
ranges;
funnel@30041000 {
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x30041000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ca_funnel_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
ca_funnel_in_ports: in-ports {
port {
ca_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etm0_out_port>;
};
};
/* funnel output port */
port@2 {
reg = <0>;
/* the other input ports are not connect to anything */
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
/* the other input ports are not connect to anything */
};
};
@ -229,28 +216,28 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
funnel@30083000 {
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x30083000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ports {
in-ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ca_funnel_out_port0>;
};
};
@ -258,18 +245,18 @@
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
slave-mode; /* M4 input */
/* M4 input */
};
};
/* the other input ports are not connect to anything */
};
port@2 {
reg = <0>;
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
/* the other input ports are not connect to anything */
};
};
@ -279,20 +266,16 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
etf_in_port: endpoint {
slave-mode;
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
port@1 {
reg = <0>;
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
@ -306,10 +289,11 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etr_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
@ -320,17 +304,18 @@
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port0>;
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
@ -431,14 +416,14 @@
gpio-ranges = <&iomuxc 0 139 16>;
};
wdog1: wdog@30280000 {
wdog1: watchdog@30280000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
};
wdog2: wdog@30290000 {
wdog2: watchdog@30290000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@ -446,7 +431,7 @@
status = "disabled";
};
wdog3: wdog@302a0000 {
wdog3: watchdog@302a0000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@ -454,7 +439,7 @@
status = "disabled";
};
wdog4: wdog@302b0000 {
wdog4: watchdog@302b0000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x302b0000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
@ -462,52 +447,52 @@
status = "disabled";
};
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
iomuxc_lpsr: pinctrl@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
};
gpt1: gpt@302d0000 {
gpt1: timer@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
<&clks IMX7D_GPT1_ROOT_CLK>;
clock-names = "ipg", "per";
};
gpt2: gpt@302e0000 {
gpt2: timer@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
<&clks IMX7D_GPT2_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
gpt3: gpt@302f0000 {
gpt3: timer@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
<&clks IMX7D_GPT3_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
gpt4: gpt@30300000 {
gpt4: timer@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
<&clks IMX7D_GPT4_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
kpp: kpp@30320000 {
kpp: keypad@30320000 {
compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
reg = <0x30320000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
@ -515,18 +500,53 @@
status = "disabled";
};
iomuxc: iomuxc@30330000 {
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx7d-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
"fsl,imx6q-iomuxc-gpr", "syscon",
"simple-mfd";
reg = <0x30340000 0x10000>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <0>;
mux-reg-masks = <0x14 0x00000010>;
};
video_mux: csi-mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
csi_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_csi_mux>;
};
};
port@2 {
reg = <2>;
csi_mux_to_csi: endpoint {
remote-endpoint = <&csi_from_csi_mux>;
};
};
};
};
ocotp: ocotp-ctrl@30350000 {
ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx7d-ocotp", "syscon";
@ -537,32 +557,19 @@
reg = <0x3c 0x4>;
};
tempmon_temp_grade: temp-grade@10 {
fuse_grade: fuse-grade@10 {
reg = <0x10 0x4>;
};
};
tempmon: tempmon {
compatible = "fsl,imx7d-tempmon";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon =<&anatop>;
nvmem-cells = <&tempmon_calib>,
<&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
anatop: anatop@30360000 {
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg_1p0d: regulator-vdd1p0d@30360210 {
reg = <0x30360210>;
reg_1p0d: regulator-vdd1p0d {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p0d";
regulator-min-microvolt = <800000>;
@ -575,6 +582,30 @@
anatop-max-voltage = <1200000>;
anatop-enable-bit = <0>;
};
reg_1p2: regulator-vdd1p2 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
anatop-reg-offset = <0x220>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0x14>;
anatop-min-voltage = <1100000>;
anatop-max-voltage = <1300000>;
anatop-enable-bit = <0>;
};
tempmon: tempmon {
compatible = "fsl,imx7d-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
};
snvs: snvs@30370000 {
@ -591,24 +622,19 @@
clock-names = "snvs-rtc";
};
snvs_poweroff: snvs-poweroff {
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
value = <0x60>;
mask = <0x60>;
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-pwrkey";
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
};
};
clks: ccm@30380000 {
clks: clock-controller@30380000 {
compatible = "fsl,imx7d-ccm";
reg = <0x30380000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
@ -618,7 +644,7 @@
clock-names = "ckil", "osc";
};
src: src@30390000 {
src: reset-controller@30390000 {
compatible = "fsl,imx7d-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@ -638,11 +664,23 @@
#address-cells = <1>;
#size-cells = <0>;
pgc_pcie_phy: pgc-power-domain@1 {
pgc_mipi_phy: power-domain@0 {
#power-domain-cells = <0>;
reg = <0>;
power-supply = <&reg_1p0d>;
};
pgc_pcie_phy: power-domain@1 {
#power-domain-cells = <0>;
reg = <1>;
power-supply = <&reg_1p0d>;
};
pgc_hsic_phy: power-domain@2 {
#power-domain-cells = <0>;
reg = <2>;
power-supply = <&reg_1p2>;
};
};
};
};
@ -660,6 +698,7 @@
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc";
#io-channel-cells = <1>;
status = "disabled";
};
@ -669,10 +708,11 @@
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc";
#io-channel-cells = <1>;
status = "disabled";
};
ecspi4: ecspi@30630000 {
ecspi4: spi@30630000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -684,6 +724,34 @@
status = "disabled";
};
ftm1: pwm@30640000 {
compatible = "fsl,vf610-ftm-pwm";
reg = <0x30640000 0x10000>;
#pwm-cells = <3>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
<&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
<&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
<&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
status = "disabled";
};
ftm2: pwm@30650000 {
compatible = "fsl,vf610-ftm-pwm";
reg = <0x30650000 0x10000>;
#pwm-cells = <3>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
<&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
<&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
<&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
status = "disabled";
};
pwm1: pwm@30660000 {
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
@ -728,6 +796,23 @@
status = "disabled";
};
csi: csi@30710000 {
compatible = "fsl,imx7-csi";
reg = <0x30710000 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "axi", "mclk", "dcic";
status = "disabled";
port {
csi_from_csi_mux: endpoint {
remote-endpoint = <&csi_mux_to_csi>;
};
};
};
lcdif: lcdif@30730000 {
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
reg = <0x30730000 0x10000>;
@ -737,6 +822,37 @@
clock-names = "pix", "axi";
status = "disabled";
};
mipi_csi: mipi-csi@30750000 {
compatible = "fsl,imx7-mipi-csi2";
reg = <0x30750000 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
clock-names = "pclk", "wrap", "phy";
power-domains = <&pgc_mipi_phy>;
phy-supply = <&reg_1p0d>;
resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_vc0_to_csi_mux: endpoint {
remote-endpoint = <&csi_mux_from_mipi_vc0>;
};
};
};
};
};
aips3: bus@30800000 {
@ -753,7 +869,7 @@
reg = <0x30800000 0x100000>;
ranges;
ecspi1: ecspi@30820000 {
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -765,7 +881,7 @@
status = "disabled";
};
ecspi2: ecspi@30830000 {
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -777,7 +893,7 @@
status = "disabled";
};
ecspi3: ecspi@30840000 {
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@ -868,7 +984,7 @@
};
};
crypto: caam@30900000 {
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@ -879,19 +995,19 @@
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
clock-names = "ipg", "aclk";
sec_jr0: jr0@1000 {
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr1@3000 {
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@ -905,6 +1021,7 @@
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CAN1_ROOT_CLK>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x10 1>;
status = "disabled";
};
@ -915,6 +1032,7 @@
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CAN2_ROOT_CLK>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x10 2>;
status = "disabled";
};
@ -1002,6 +1120,25 @@
status = "disabled";
};
mu0a: mailbox@30aa0000 {
compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_MU_ROOT_CLK>;
#mbox-cells = <2>;
status = "disabled";
};
mu0b: mailbox@30ab0000 {
compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
reg = <0x30ab0000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_MU_ROOT_CLK>;
#mbox-cells = <2>;
fsl,mu-side-b;
status = "disabled";
};
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
@ -1038,7 +1175,7 @@
reg = <0x30b30200 0x200>;
};
usdhc1: usdhc@30b40000 {
usdhc1: mmc@30b40000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@ -1050,7 +1187,7 @@
status = "disabled";
};
usdhc2: usdhc@30b50000 {
usdhc2: mmc@30b50000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@ -1062,7 +1199,7 @@
status = "disabled";
};
usdhc3: usdhc@30b60000 {
usdhc3: mmc@30b60000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@ -1074,12 +1211,12 @@
status = "disabled";
};
qspi1: qspi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
qspi: spi@30bb0000 {
compatible = "fsl,imx7d-qspi";
reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
<&clks IMX7D_QSPI_ROOT_CLK>;
@ -1091,8 +1228,8 @@
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SDMA_CORE_CLK>,
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_SDMA_CORE_CLK>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
@ -1106,15 +1243,16 @@
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
};
@ -1132,7 +1270,7 @@
clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: gpmi-nand@33002000{
gpmi: nand-controller@33002000{
compatible = "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;

13
include/dt-bindings/clock/imx7d-clock.h
View file

@ -1,10 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
@ -168,7 +164,7 @@
#define IMX7D_SPDIF_ROOT_SRC 155
#define IMX7D_SPDIF_ROOT_CG 156
#define IMX7D_SPDIF_ROOT_DIV 157
#define IMX7D_ENET1_REF_ROOT_CLK 158
#define IMX7D_ENET1_IPG_ROOT_CLK 158
#define IMX7D_ENET1_REF_ROOT_SRC 159
#define IMX7D_ENET1_REF_ROOT_CG 160
#define IMX7D_ENET1_REF_ROOT_DIV 161
@ -176,7 +172,7 @@
#define IMX7D_ENET1_TIME_ROOT_SRC 163
#define IMX7D_ENET1_TIME_ROOT_CG 164
#define IMX7D_ENET1_TIME_ROOT_DIV 165
#define IMX7D_ENET2_REF_ROOT_CLK 166
#define IMX7D_ENET2_IPG_ROOT_CLK 166
#define IMX7D_ENET2_REF_ROOT_SRC 167
#define IMX7D_ENET2_REF_ROOT_CG 168
#define IMX7D_ENET2_REF_ROOT_DIV 169
@ -455,5 +451,6 @@
#define IMX7D_SNVS_CLK 442
#define IMX7D_CAAM_CLK 443
#define IMX7D_KPP_ROOT_CLK 444
#define IMX7D_CLK_END 445
#define IMX7D_PXP_CLK 445
#define IMX7D_CLK_END 446
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */

5
include/dt-bindings/power/imx7-power.h
View file

@ -1,9 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2017 Impinj
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_IMX7_POWER_H__