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ARM: dts: stm32: add STM32MP13 SoCs support
Add initial support of STM32MP13 family based on v5.18-rc2 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay
parent
98c4828740
commit
a82abb15a8
8 changed files with 622 additions and 0 deletions
123
arch/arm/dts/stm32mp13-pinctrl.dtsi
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123
arch/arm/dts/stm32mp13-pinctrl.dtsi
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@ -0,0 +1,123 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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sdmmc1_b4_pins_a: sdmmc1-b4-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <1>;
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drive-open-drain;
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bias-disable;
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};
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};
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sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
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<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
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};
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};
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sdmmc1_clk_pins_a: sdmmc1-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2 {
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pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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slew-rate = <1>;
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drive-open-drain;
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bias-pull-up;
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};
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};
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sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
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<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
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<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
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};
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};
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sdmmc2_clk_pins_a: sdmmc2-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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uart4_pins_a: uart4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
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bias-disable;
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};
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};
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};
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358
arch/arm/dts/stm32mp131.dtsi
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358
arch/arm/dts/stm32mp131.dtsi
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@ -0,0 +1,358 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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clocks {
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clk_axi: clk-axi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <266500000>;
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};
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_pclk3: clk-pclk3 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <104438965>;
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};
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clk_pclk4: clk-pclk4 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <133250000>;
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};
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clk_pll4_p: clk-pll4_p {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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clk_pll4_r: clk-pll4_r {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <99000000>;
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};
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&intc>;
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always-on;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_hsi>;
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status = "disabled";
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};
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dma1: dma-controller@48000000 {
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compatible = "st,stm32-dma";
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reg = <0x48000000 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_pclk4>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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};
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dma2: dma-controller@48001000 {
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compatible = "st,stm32-dma";
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reg = <0x48001000 0x400>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_pclk4>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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};
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dmamux1: dma-router@48002000 {
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compatible = "st,stm32h7-dmamux";
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reg = <0x48002000 0x40>;
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clocks = <&clk_pclk4>;
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#dma-cells = <3>;
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dma-masters = <&dma1 &dma2>;
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dma-requests = <128>;
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dma-channels = <16>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp13-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&clk_pclk3>;
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};
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mdma: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_pclk4>;
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#dma-cells = <5>;
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dma-channels = <32>;
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dma-requests = <48>;
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};
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sdmmc1: mmc@58005000 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x20253180>;
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&clk_pll4_p>;
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clock-names = "apb_pclk";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <130000000>;
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status = "disabled";
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};
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sdmmc2: mmc@58007000 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x20253180>;
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reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&clk_pll4_p>;
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clock-names = "apb_pclk";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <130000000>;
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status = "disabled";
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};
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iwdg2: watchdog@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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clocks = <&clk_pclk4>, <&clk_lsi>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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bsec: efuse@5c005000 {
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compatible = "st,stm32mp13-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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part_number_otp: part_number_otp@4 {
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reg = <0x4 0x2>;
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};
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ts_cal1: calib@5c {
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reg = <0x5c 0x2>;
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};
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ts_cal2: calib@5e {
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reg = <0x5e 0x2>;
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};
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};
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/*
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* Break node order to solve dependency probe issue between
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* pinctrl and exti.
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*/
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pinctrl: pin-controller@50002000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp135-pinctrl";
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ranges = <0 0x50002000 0x8400>;
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pins-are-numbered;
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gpioa: gpio@50002000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&clk_pclk4>;
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st,bank-name = "GPIOA";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 0 16>;
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};
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gpiob: gpio@50003000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&clk_pclk4>;
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st,bank-name = "GPIOB";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 16 16>;
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};
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gpioc: gpio@50004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&clk_pclk4>;
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st,bank-name = "GPIOC";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 32 16>;
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};
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gpiod: gpio@50005000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x400>;
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clocks = <&clk_pclk4>;
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st,bank-name = "GPIOD";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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|
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gpioe: gpio@50006000 {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
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reg = <0x4000 0x400>;
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clocks = <&clk_pclk4>;
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st,bank-name = "GPIOE";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 64 16>;
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};
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gpiof: gpio@50007000 {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x400>;
|
||||
clocks = <&clk_pclk4>;
|
||||
st,bank-name = "GPIOF";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&clk_pclk4>;
|
||||
st,bank-name = "GPIOG";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&clk_pclk4>;
|
||||
st,bank-name = "GPIOH";
|
||||
ngpios = <15>;
|
||||
gpio-ranges = <&pinctrl 0 112 15>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&clk_pclk4>;
|
||||
st,bank-name = "GPIOI";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 128 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
37
arch/arm/dts/stm32mp133.dtsi
Normal file
37
arch/arm/dts/stm32mp133.dtsi
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp131.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
m_can1: can@4400e000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&clk_hse>, <&clk_pll4_r>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can2: can@4400f000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&clk_hse>, <&clk_pll4_r>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
12
arch/arm/dts/stm32mp135.dtsi
Normal file
12
arch/arm/dts/stm32mp135.dtsi
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp133.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
};
|
||||
};
|
||||
57
arch/arm/dts/stm32mp135f-dk.dts
Normal file
57
arch/arm/dts/stm32mp135f-dk.dts
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp135.dtsi"
|
||||
#include "stm32mp13xf.dtsi"
|
||||
#include "stm32mp13-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
|
||||
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
vdd_sd: vdd-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_sd";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdd_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
17
arch/arm/dts/stm32mp13xc.dtsi
Normal file
17
arch/arm/dts/stm32mp13xc.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: crypto@54002000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_axi>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
17
arch/arm/dts/stm32mp13xf.dtsi
Normal file
17
arch/arm/dts/stm32mp13xf.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: crypto@54002000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_axi>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3,6 +3,7 @@ M: Patrick Delaunay <patrick.delaunay@foss.st.com>
|
|||
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
||||
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
|
||||
S: Maintained
|
||||
F: arch/arm/dts/stm32mp13*
|
||||
F: arch/arm/dts/stm32mp15*
|
||||
F: board/st/stm32mp1/
|
||||
F: configs/stm32mp15_defconfig
|
||||
|
|
|
|||
Loading…
Reference in a new issue