board: freescale: imx93_evk: support ethernet

Add ethernet support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2022-07-26 16:41:18 +08:00 committed by Stefano Babic
parent a624251461
commit 481f96068e
3 changed files with 48 additions and 0 deletions

View file

@ -7,6 +7,7 @@
#define __ASM_ARCH_IMX9_REGS_H__
#define ARCH_MXC
#define FEC_QUIRK_ENET_MAC
#define IOMUXC_BASE_ADDR 0x443C0000UL
#define CCM_BASE_ADDR 0x44450000UL
@ -39,6 +40,12 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#include <stdbool.h>

View file

@ -38,8 +38,40 @@ int board_early_init_f(void)
return 0;
}
static int setup_fec(void)
{
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
static int setup_eqos(void)
{
struct blk_ctrl_wakeupmix_regs *bctrl =
(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&bctrl->eqos_gpr,
BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
return set_clk_eqos(ENET_125MHZ);
}
int board_init(void)
{
if (CONFIG_IS_ENABLED(FEC_MXC))
setup_fec();
if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
setup_eqos();
return 0;
}

View file

@ -75,6 +75,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@ -89,6 +90,14 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y