ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)

Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut 2022-04-24 23:44:03 +02:00 committed by Stefano Babic
parent 16ee0f2afd
commit 52b6b480db
22 changed files with 31 additions and 21 deletions

View file

@ -48,6 +48,16 @@
#ifdef CONFIG_IMX8MM
#define USDHC3_BASE_ADDR 0x30B60000
#endif
#define UART_BASE_ADDR(n) ( \
!!sizeof(struct { \
static_assert((n) >= 1 && (n) <= 4); \
int pad; \
}) * ( \
(n) == 1 ? UART1_BASE_ADDR : \
(n) == 2 ? UART2_BASE_ADDR : \
(n) == 3 ? UART3_BASE_ADDR : \
UART4_BASE_ADDR) \
)
#define TZASC_BASE_ADDR 0x32F80000

View file

@ -145,7 +145,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -91,7 +91,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -68,7 +68,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -66,7 +66,7 @@
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -102,7 +102,7 @@
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K

View file

@ -107,7 +107,7 @@
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#endif
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -75,7 +75,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -64,7 +64,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K

View file

@ -98,7 +98,7 @@
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K

View file

@ -80,7 +80,7 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -169,7 +169,7 @@
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
#endif
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048

View file

@ -71,7 +71,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024

View file

@ -78,7 +78,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024

View file

@ -106,7 +106,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024

View file

@ -28,7 +28,7 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Board and environment settings */
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#define CONFIG_HOSTNAME "kontron-mx8mm"
#ifdef CONFIG_USB_EHCI_HCD

View file

@ -84,7 +84,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

View file

@ -84,7 +84,7 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K

View file

@ -84,7 +84,7 @@
#define PHYS_SDRAM_SIZE 0x80000000
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K

View file

@ -85,7 +85,7 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024

View file

@ -84,7 +84,7 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K

View file

@ -101,7 +101,7 @@
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
/* UART */
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K